Patent Application
20250093935
The present disclosure relates generally to the field of data communication, and more particularly, to systems and methods for sharing a program such as a connectivity manager between a high-performance processing device and a low-power processing device.
A microcontroller (MCU) is a small processing device that is fabricated on a single integrated circuit (IC) chip. A microcontroller contains a central processing unit (CPU) along with memory and programmable input/output peripherals. Program memory in the form of RAM, NOR flash or ROM is also often included on chip. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers.
A CPU, also called a processing core, is an electronic circuit that executes instructions stored in memory. Principal components of a CPU include the arithmetic-logic unit (ALU) that performs arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations, and a control unit that orchestrates the fetching from memory, decoding and execution of instructions by directing the coordinated operations of the ALU, registers and other components.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
MCUs vary in performance. Factors affecting MCU performance include type (e.g., 8-bit, 16-bit, etc.), clock speed, I/O speed, etc. A high-performance MCU may be more expensive to manufacture than a low-performance MCU because of physical differences. The present disclosure will distinguish high-performance MCUs from low-performance MCUs primarily by clock speed, it being understood that other factors (e.g., type) may affect performance.
High-performance MCUs operate faster and execute more instructions than low-performance MCUs but consume more power, which may be a problem if the high-performance MCU is powered by a battery. Low-performance MCUs are cheaper and to make and consume less power but operate at a slower speed. For purposes of explanation only, the present disclosure will be described with reference to a pair of MCUs that are powered by a battery.
The present disclosure provides a method and apparatus for addressing the high-performance/low-performance MCU dilemma mentioned above.
Both MCUs 104 and 106 are in data communication with shared random-access memory (RAM) 108 via peripheral data bus 110. Because RAM 108 is shared, any specific location in RAM 108 can be accessed by both MCUs. RAM 108 stores a program X, such as a network connectivity manager more fully described below, that can be shared by MCU's 104 and 106. Either MCU 104 or MCU 106 can execute program X, but not at the same time. MCUs 104 and 106 include control logic modules 120 and 120, respectively, that coordinate execution of program X between the MCUs.
High-performance MCU 106 operates at a clock speed that is higher than the clock speed at which low-performance MCU 104 operates. With a higher clock speed, high-performance MCU 106 can execute instructions of program X faster than low-performance MCU 104. However, high-performance MCU 106 will consume more power and drain the battery faster than low-performance MCU 104 when executing program X. MCU 104 may be cheaper to manufacture than MCU 106.
Program X includes multiple functions, which can be allocated on an MCU-by-MCU basis. High-performance MCU 106 can be designated to implement one or more functions of program X, while low-performance MCU 104 can be designated to implement another one or more functions of program X. The designations can be defined through appropriate configuration of control logic modules 120 and 122.
In step 212 high-performance MCU 106 transitions from sleep mode to active mode in response to receiving the one or more IPC messages. Sleep mode, sometimes called standby or suspend mode, is a power-sparing state that an MCU enters when not in use. In step 214 low-performance MCU 104 transitions from active mode to sleep mode. Thereafter, in step 216 high-performance MCU 206 begins implementing program X in shared memory 108 at the handle provided by the one or more IPC messages that were sent by low-performance MCU 104 in step 210. High-performance MCU 106 may begin implementing a second function of program X allocated to it in step 216. For example, high-performance MCU 106 may begin a process for reading/writing data. While executing program X, control logic 122 monitors for the occurrence of a specific transition triggering event B as shown in step 220. For example, high-performance MCU 106 may enter an idle phase in which it is not executing instructions of program X. Transition triggering event B may be defined as a predetermined amount of time in which high-performance MCU 106 is in the idle phase. Control logic 122 can monitor idling time of high-performance MCU 106. If the idling time exceeds the predetermined amount of time, transition triggering event B has occurred.
In response to detecting the occurrence of transition triggering event B, high-performance MCU 106 generates and sends one or more IPC messages to low-performance MCU 104 via peripheral data bus 110 as shown in step 222. The one or more IPC messages sent to low-performance MCU 104 may include an indication that transition triggering event B has occurred. The one or more IPC messages sent to low-performance MCU 104 may include a handle for program X in memory 108. One or more IPC messages may include a message for low-performance MCU 104 to wake up.
In response to sending the one or more IPC messages high-performance MCU 106 transitions from active mode to sleep mode to conserve energy in the battery. In response to receiving the one or more IPC messages from high-performance MCU 106, low-performance MCU 104 transitions from sleep mode to active mode as shown in step 226. Thereafter, MCU 104 resumes executing instructions of program X as shown in step 204, and the process repeats.
MCUs execute instructions of a program. For example, MCUs can execute instructions of a network connectively manager program (hereinafter network-manager). The present disclosure will be made with respect to high-performance and low-performance MCUs executing instructions of a shared network-manager, the present disclosure should not be limited thereto.
A network-manager can perform various networking operations. For example, the network-manager can establish data connections between endpoints (e.g., devices that are at physically end points on a network). The network-manager can transmit data to or receive data from a connected endpoint using a suite of communication protocols such as Transmission Control Protocol/Internet Protocol (TCP/IP) suite. The present disclosure will be made with reference to a network-manager that implements the TCP/IP suite (hereinafter TCP/IP), it being understood the present disclosure should not be limited thereto.
TCP/IP specifies how data is exchanged over the Internet by providing end-to-end communications that identify how data should be broken into packets, addressed, transmitted, routed, and received at the destination. TCP/IP requires little central management and is designed to make networks reliable with the ability to recover automatically from the failure of any device on the network.
TCP and IP are the two main protocols of the TCP/IP suite. TCP and IP serve specific functions. TCP defines how endpoint processes can create data connections across a network. It also manages how a message is assembled into smaller packets before it is then transmitted over the Internet and reassembled in the right order at the destination address. IP defines how to address and route each packet to make sure it reaches the right destination.
Network data is communicated through “ports.” A port is a number assigned to uniquely identify an endpoint process. A port can be seen as a logical channel through which data can be transmitted to or received from an endpoint process. An endpoint may have multiple processes running, and each of these processes is identified using the port number on which it is running. A network-manager can associate its input or output channels via an Internet socket associated with a transport protocol, a network address such as an IP address, and a port number. This is known as binding. A socket is used by an endpoint process to send and receive data via the network. A network-manager can transmit outgoing data from all ports onto the network, and forward arriving network packets to processes by matching the packet's IP address and port number to a socket. For TCP, only one process may bind to a specific IP address and port combination.
To establish a data connection between endpoints, TCP uses a three-way handshake. Before a first endpoint attempts to connect with a second endpoint, the second endpoint may first bind to and listen at a port to open it up for connections. This is called a passive open. Once the passive open is established, the first endpoint may initiate an active open. To establish a connection, a three-way (or 3-step) handshake typically occurs. The active open is performed by the first endpoint sending a synchronization SYN message to the second endpoint. The first endpoint sets a segment's sequence number to a random value A. In response to receiving the SYN message, the second endpoint replies with a synchronization-acknowledgement SYN-ACK message. An acknowledgment number is set to one more than the received sequence number (A+1), and the sequence number that the second endpoint chooses for the packet is another random number, B. Finally, the first endpoint sends an acknowledgement ACK message back to the second endpoint. The sequence number is set to the received acknowledgement value i.e. A+1, and the acknowledgement number is set to one more than the received sequence number i.e., B+1. At that point, both endpoints have received an acknowledgment of the connection. The first two steps establish the connection parameter (sequence number) for one direction and it is acknowledged. The second two steps establish the connection parameter (sequence number) for the other direction and it is acknowledged. With these, a full-duplex communication is established.
Connection termination may use a four-way handshake, with each side of the connection terminating independently. When an endpoint wishes to stop its half of the connection, it transmits a finish FIN message, which the other endpoint acknowledges with an ACK message. Therefore, a typical termination requires a pair of FIN and ACK messages from each endpoint. After both FIN/ACK exchanges are concluded, the endpoint which sent the first FIN before receiving one waits for a timeout before finally closing the connection, during which time the local port is unavailable for new connections; this prevents confusion due to delayed packets being delivered during subsequent connections.
A connection can be “half-open,” in which case one side has terminated its end, but the other has not. The side that has terminated can no longer send any data into the connection, but the other side can. The terminating side should continue reading the data until the other side terminates as well.
Endpoint 300 also includes a connectivity IC 312 in data communication with MCUs 304 and 306 through peripheral data bus 318. Connectivity IC 312 can establish a Wi-Fi or Bluetooth communication link with the Internet. Either MCU 304 or MCU 306 can access connectivity IC 312. Although not shown, it will be presumed that endpoint 300 includes a battery for powering MCU 304 and 306. The magnitude of the supply voltages provided to MCUs 304 and 306 can be different.
High-performance MCU 306 operates at a clock speed that is higher than the clock speed at which low-performance MCU 304 operates. With a higher clock speed, high-performance MCU 306 can execute instructions of a network-manager 330 faster than low-performance MCU 304. However, high-performance MCU 306 will consume more power and drain the battery faster than low-performance MCU 304 when implementing network-manager 330. Moreover, high-performance MCU 306 may be bigger and made with more transistors. As a result, high-performance MCU 306 may cost more to manufacture than low-performance MCU 304.
Network-manager 330 provides networking operations. Either MCU 304 or 306 can implement the operations, but not at the same time. For example, MCU 304 or MCU 306, but not both at the same time, can implement passive and active opens while executing instructions of network-manager 330. After a network connection is established with, for example, endpoint 316, MCU 304 or MCU 306, but not both MCU and MCU 306 at the same time, can transmit data to or receive data from endpoint 316 while MCU 304 or MCU 306 implements TCP/IP stack 332. As will be more fully described below, MCUs 304 and 306 include control logic modules 320 and 322, respectively, that arbitrate with each other to determine which of MCUs 304 and 306 will have exclusive control to implement network-manager 330.
High-performance MCU 306 operates at a clock speed that is higher than the clock speed at which low-performance MCU 304 operates. With a higher clock speed, high-performance MCU 306 can execute instructions of network-manager 330 faster than low-performance MCU 304. For example, high-performance MCU 306 can receive data (i.e., read) from or transmit data (i.e., write) to, for example, endpoint 316 at a rate that is faster than the rate at which MCU 304 can read/write data. However, high-performance MCU 306 may consume more power and drain the battery faster than low-performance MCU 304 when implementing network-manager 330.
Either MCU 304 or MCU 306 could implement the same operations of network manager 330 although at different speeds. The operations of network manager software 330 can be allocated on an MCU-by-MCU basis; High-performance MCU 306 can be designated to implement a first set of one or more operations of network-manager 330, while MCU 304 can be designated to implement a second set of one or more operations of network-manager 330, where the first and second sets are different. The designations can be defined through control logic modules 320 and 322.
Exclusive implementation of network-manager 330 can transfer back and forth between MCUs 304 and 306 based on predefined triggering events. To illustrate, low-performance MCU 304 on power up may be designated to bring up network-manager 330 including its network stack 332 along with BT/Wi-Fi connectivity. Low-performance MCU 304 can then initiate stack 332 and begin listening for any incoming network connections.
After high-performance MCU 306 wakes up from sleep mode and takes control in response to the IPC messages received from low-performance MCU 304, network-manager 330 with its internal state retained is transferred to high-performance MCU 306. High-performance MCU 306 brings up the network-manager 330 in active mode. In active mode, high-performance MCU 306 reads/writes data through the socket provided by low-performance MCU 304. Since high-performance MCU 306 operates at a higher frequency, data transfer between it and interconnectivity IC 312 will be greater, and hence high-performance MCU 306 will be able to provide higher data throughput when compared to the ability of low-performance MCU 304.
Once network-manager 330 determines that no active network connection exists or the network connection is idle, high-performance MCU 306 can initiate a transfer of control over network-manager 330 back to low-performance MCU 304 by providing it the network handle in one or more IPC messages. High-performance MCU 306 may then put itself into a passive mode. Once network-manager 330 and/or high-performance MCU 306 goes to passive mode, high-performance MCU 306 will transition to sleep mode to avoid consuming any unnecessary power from the battery. In this way low-performance MCU 304 assumes control over network-manager 330 and will start listening for and accepting a new network connection. Low-performance MCU 304 may consume less power than high-performance MCU 306 while listening for and accepting a new network connection.
In the above description, some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on analog signals and/or digital signals or data bits within a non-transitory storage medium. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as data, bits, values, elements, symbols, characters, terms, numbers, or the like.
Reference in the description to “an embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” means that a particular feature, structure, step, operation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment of the disclosure. Further, the appearances of the phrases “an embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” in various places in the description do not necessarily all refer to the same embodiment(s).
The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrations in accordance with exemplary embodiments. These embodiments, which may also be referred to herein as “examples,” are described in enough detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter but rather to enable one skilled in the art to practice, make, and/or use the subject matter.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “performing,” “generating,” “determining,” “placing,” or the like, refer to the actions and processes of an integrated circuit (IC) controller, or similar electronic device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the controller's registers and memories into other data similarly represented as physical quantities within the controller memories or registers or other such information non-transitory storage medium.
The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example’ or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an embodiment” or “one embodiment” or “an embodiment” or “one embodiment” throughout is not intended to mean the same embodiment or embodiment unless described as such.
Embodiments described herein may also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise firmware or hardware logic selectively activated or reconfigured by the apparatus. Such firmware may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, flash memory, or any type of media suitable for storing electronic instructions. The term “computer-readable storage medium” should be taken to include a single medium or multiple media that store one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments. The term “computer-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments.
The above description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It is to be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
