SHARED DYNAMIC BUFFER IN IMAGE SIGNAL PROCESSOR

Abstract

Embodiments relate to an image signal processor that includes an image processing circuit, a buffer, and a rate limiter circuit. The image processing circuit perform operations associated with image signal processing. The buffer stores the image data provided by the system memory. The buffer includes a shared that is dynamically allocated among the image processing circuits. The rate limiter circuit arbitrates allocation of the shared section. The arbitration process includes allocating data credits for the shared section to an image processing circuit. The rate limiter circuit determines a first number of blocks in the shared section that are allocated for pending requests and a second number of blocks that include data pending to be consumed by the image processing circuit. If the total allocated blocks occupied by the image processing circuit exceed a throttling threshold, the image processing circuit will be throttled by an exponential factor.

Description

Claims

1. An image signal processor, comprising: image processing circuits configured to perform operations associated with image signal processing;a buffer configured to buffer data between the image processing circuits and the system memory, the buffer comprising a shared section dynamically allocated among the image processing circuits; anda rate limiter circuit coupled to the image processing circuits, the rate limiter circuit configured to arbitrate allocation of the shared section among the image processing circuits, wherein arbitrating the allocation of the shared section comprises: allocating data credits for the shared section to one of the image processing circuits;determining total allocated blocks for the shared section to the one of the image processing circuits, the total allocated blocks comprising a first number of blocks allocated for pending requests made by the one of the image processing circuits and a second number of blocks pending consumption by the one of the image processing circuits; andreducing or preventing allocation of additional data credits to the one of the image processing circuits for at least a duration responsive to determining that the total allocated blocks exceed the throttling threshold.

2. The image signal processor of claim 1, wherein the allocation of the additional data credits to the one of the image processing circuits is reduced by an exponential factor for at least the duration in which the total allocated blocks occupied by the one of the image processing circuits exceeding the throttling threshold.

3. The image signal processor of claim 1, wherein at least one of the image processing circuits coupled to the buffer is allocated for a fixed private section of the buffer.

4. The image signal processor of claim 3, wherein the fixed private section is configured to allow the at least one of the image processing circuits to send at least one pending request.

5. The image signal processor of claim 1, wherein the image processing circuits include a plurality of read direct memory access (DMA) or a plurality of write DMA.

6. The image signal processor of claim 1, wherein arbitrating the allocation of the shared section further comprises: detecting that the one of the image processing circuits has been stalled; andstopping temporarily allocating additional data credits to the one of the image processing circuits.

7. The image signal processor of claim 6, wherein detecting that the one of the image processing circuits has been stalled comprises: determining the second number of blocks in the shared section that include data pending to be consumed by the one of the image processing circuits is larger than zero; anddetecting that the one of the image processing circuits has stopped sending buffer data request to the buffer.

8. The image signal processor of claim 1, wherein the allocation of the additional data credits is reduced until the total allocated blocks occupied by the one of the image processing circuits is below a restoration threshold.

9. The image signal processor of claim 1, wherein an allocation rate of the data credits to the one of the image processing circuits increases until the one of the image processing circuits is stalled or until the total allocated blocks occupied by the one of the image processing circuits exceeding the throttling threshold.

10. The image signal processor of claim 1, wherein each data credit allows the one of the image processing circuits to request to exchange a fixed size of data with the system memory.

11. A method comprising: initiating an exchange with a system memory for image data to be processed in an image processing circuit in an image signal processor;storing, in a buffer of the image signal processor, the image data from a response of the system memory, the buffer comprising a shared section dynamically allocated among the image processing circuit and other image processing circuits in the image signal processor;allocating data credits for the shared section to the image processing circuit;determining total allocated blocks for the shared section to the image processing circuit, the total allocated blocks comprising a first number of blocks allocated for pending requests made by the image processing circuit and a second number of blocks pending consumption by the image processing circuit; andreducing or preventing allocation of additional data credits to the image processing circuit for at least a duration responsive to determining that the total allocated blocks exceed the throttling threshold.

12. The method of claim 11, wherein the allocation of the additional data credits to the image processing circuit is reduced by an exponential factor for at least the duration in which the total allocated blocks occupied by the image processing circuit exceeding the throttling threshold.

13. The method of claim 11, wherein the image processing circuit is allocated for a fixed private section of the buffer.

14. The method of claim 13, wherein the fixed private section is configured to allow the image processing circuit to send at least one pending request.

15. The method of claim 11, further comprising: detecting that the image processing circuit has been stalled; andstopping temporarily allocating additional data credits to the image processing circuit.

16. The method of claim 15, wherein detecting that the image processing circuit has been stalled comprises: determining the second number of blocks in the shared section that include data pending to be consumed by the image processing circuit is larger than zero; anddetecting that the image processing circuit has stopped sending buffer data request to the buffer.

17. The method of claim 11, wherein the allocation of the additional data credits is reduced until the total allocated blocks occupied by the image processing circuit is below a restoration threshold.

18. The method of claim 11, wherein an allocation rate of the data credits to the image processing circuit increases until the image processing circuit is stalled or until the total allocated blocks occupied by the image processing circuit exceeding the throttling threshold.

19. A computing device, comprising: an image sensor configure to capture image data;a system memory coupled to the image sensor, the system memory configured to store the image data; andan image signal processor coupled to the system memory, the image signal processor configured to: initiate an exchange with a system memory for image data to be processed in an image processing circuit in an image signal processor;store, in a buffer of the image signal processor, the image data from a response of the system memory, the buffer comprising a shared section dynamically allocated among the image processing circuit and other image processing circuits in the image signal processor;allocate data credits for the shared section to the image processing circuit;determine total allocated blocks for the shared section to the image processing circuit, the total allocated blocks comprising a first number of blocks allocated for pending requests made by the image processing circuit and a second number of blocks pending consumption by the image processing circuit; andreduce or prevent allocation of additional data credits to the image processing circuit for at least a duration responsive to determining that the total allocated blocks exceed the throttling threshold.

20. The computing device of claim 19, wherein the allocation of the additional data credits to the image processing circuit is reduced by an exponential factor for at least the duration in which the total allocated blocks occupied by the image processing circuit exceeding the throttling threshold.