1. Field of the Invention
The present invention relates to the field of pipelined ADCs (analog to digital converters).
2. Prior Art
Pipelined ADCs and flash ADCs are well known in the prior art. Good reviews of the principles thereof can be found in Maxim Integrated Products'. Application Note 1023 “Understanding Pipelined ADCs”, and in Maxim Integrated Products' Application Note 810 “Understanding Flash ADCs”, respectively. A pipelined ADC typically has a sample and hold circuit on the analog signal input, which dissipates power and injects noise into the ADC. This problem is addressed in prior art by completely eliminating the sample and hold and sampling directly onto the first MDAC (multiplying digital to analog converter) capacitors. In this prior art implementation, an independent sampler in parallel with the MDAC is required for the comparators.
Also known are ADCs that use a shared operational transconductance amplifier (OTA). In such implementations, a single OTA is shared during different phases by multiple multiplying digital to analog converters.
This invention solves the problem of additional noise and power dissipation associated with an input sample and hold circuitry (SHA) in a pipelined ADC. A 4-phase shared OTA stage that implements a SHA (sample and hold), MDAC1, and MDAC2 is described herein. Although there is a speed penalty associated with the additional clock phases, this is largely mitigated by the minimal settling time required for the SHA. Also, the noise penalty of a SHA is eliminated because a charge conserving flip-around architecture is employed.
A simplified circuit schematic of the 4-phase MDAC1/MDAC2 is shown in
In
To follow the switch settings more easily,
In phase D (
At the end of Phase A, the MDAC1 quantizer latches and capacitors Cs<0:3> are connected to the references based on the quantizer decision, and capacitor Cf is connected around the OTA (phase B,
On the falling edge of PHIB (
Now referring to
The present invention solves the problem of additional noise and power dissipation associated with an input SHA in a pipelined ADC. Thus while certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
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Number | Date | Country | |
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20110298645 A1 | Dec 2011 | US |