Patent Application
20250234631
The present application relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to a method of forming shared S/D contact and the structure formed thereby.
As semiconductor industry moves towards smaller node, field-effect-transistors (FETs) are aggressively scaled to fit into the reduced footprint or real estate, which is often dictated by the node size, with increased device density. For example, two transistors may be vertically stacked together to double the density of transistors in a given footprint. In the meantime, backside power rail (BPR) and backside power distribution network (BSPDN) are used to provide signal powering and/or routing functionalities to the stacked transistors.
In an attempt to contact source/drain regions of both the bottom and the top transistor in a stacked transistor structure, it is usually necessary to first form an opening, which has a high-aspect ratio in order to reach the source/drain regions of both the bottom and the top transistors. The opening is then filled with a conductive material to form a contacting via. However, forming high-aspect ratio openings has its own process complexity such as, for example causing complete epi etch-out if not managed properly.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second S/D region being on top of the first S/D region; and a shared S/D contact, the shared S/D contact having a first portion being in direct contact with a bottom surface of the second S/D region of the second transistor and a second portion being wrapped around by the first S/D region of the first transistor.
According to one embodiment, the semiconductor structure further includes a backside S/D contact in contact with a bottom surface of the second portion of the shared S/D contact.
In one embodiment, the first portion of the shared S/D contact has a first horizontal cross-section, and the second portion of the shared S/D contact has a second horizontal cross-section; the first horizontal cross-section being larger than the second horizontal cross-section.
In another embodiment, the backside S/D contact has a third horizontal cross-section, the third horizontal cross-section being larger than the second horizontal cross-section.
In one embodiment, the first portion of the shared S/D contact is in direct contact with a top surface of the first S/D region that surrounds the second portion of the shared S/D contact.
In another embodiment, the backside S/D contact is in direct contact with a bottom surface of the first S/D region that surrounds the second portion of the shared S/D contact.
According to one embodiment, the semiconductor structure further includes a backside interconnect structure underneath the first transistor, where the second portion of the shared S/D contact is insulated from the backside interconnect structure by a dielectric capping layer.
According to another embodiment, the semiconductor structure further includes a contact metal directly above and insulated from the second S/D region of the second transistor, the contact metal extending from a frontside S/D contact of a nearby transistor.
Embodiments of present invention also provide a method of forming a semiconductor structure. The method includes forming a raw source/drain (S/D) region of a first transistor on top of a placeholder, the placeholder being formed in a substrate; forming a middle-dielectric-insulator (MDI) layer on top of the raw S/D region; forming a second S/D region of a second transistor on top of, via the MDI layer, the raw S/D region; replacing the substrate with a dielectric layer and removing the placeholder to create a first opening in the dielectric layer, the first opening exposing a bottom surface of the raw S/D region; removing a portion of the raw S/D region to create a first S/D region and a second opening surrounded by the first S/D region, the second opening exposing a bottom surface of the MDI layer; removing the MDI layer exposed by the second opening to create a third opening; and forming a shared S/D contact by filling the third opening with a conductive material to form a first portion of the shared S/D contact and filling the second opening with the conductive material to form a second portion of the shared S/D contact.
In one embodiment, removing a portion of the raw S/D region includes forming a spacer layer at sidewalls of the first opening, the spacer layer being directly on top of a bottom surface of the first S/D region and exposing the portion of the raw S/D region, and removing the portion of the raw S/D region in a selective etch process.
According to one embodiment, the method further includes removing the spacer layer to expose the bottom surface of the first S/D region; and depositing the conductive material in the first opening to form a backside S/D contact, the backside S/D contact in direct contact with a bottom surface of the second portion of the shared S/D contact and with the bottom surface of the first S/D region.
According to another embodiment, the method further includes covering the backside S/D contact with a dielectric capping layer; and forming a backside interconnect structure, the backside interconnect structure being insulated from the shared S/D region by the dielectric capping layer.
In one embodiment, removing the MDI layer includes etching the MDI layer in an isotropic etch process, through the second opening, to expose a bottom surface of the second S/D region and a top surface of the first S/D region.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity, or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations thereof that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount. Likewise, the terms “on”, “over”, or “on top of” that are used herein to describe a positional relationship between two layers or structures are intended to be broadly construed and should not be interpreted as precluding the presence of one or more intervening layers or structures.
Moreover, although various reference numerals may be used across different drawings, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus detailed explanations of the same or similar features, elements, or structures may not be repeated for each of the drawings for economy of description. Labelling for the same or similar elements in some drawings may be omitted as well in order not to overcrowd the drawings.
Likewise,
Embodiments of present invention provide forming a semiconductor structure 10 by first receiving or providing a semiconductor substrate 100. The semiconductor substrate 100 may include a bulk silicon (Si) substrate 101, an etch-stop layer 102 on top of the Si substrate 101, and a Si layer 103 on top of the etch-stop layer 102. In one embodiment, the etch-stop layer 102 may be a layer of silicon-germanium (SiGe) containing a certain percentage of germanium (Ge) such as, for example, 25 at. % and a layer of such composition is generally referred to as a SiGe25 layer. In other words, the etch-stop layer 102 may be a SiGe25 layer. In another embodiment, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate with an insulating layer of, for example, silicon-oxide (SiO2) or silicon-nitride (SiN) between a bulk substrate 101 and a Si layer 103. This insulating layer may work as an etch-stop layer 102 as well.
Embodiments of present invention further provide proceeding to form a first sacrificial insulation sheet 201 on top of the Si layer 103; a first raw stack of nanosheets 210 on top of the first sacrificial insulation sheet 201; a second sacrificial insulation sheet 202 on top of the first raw stack of nanosheets 210; and a second raw stack of nanosheets 220 on top of the second sacrificial insulation sheet 202.
The first and the second raw stack of nanosheets 210 and 220 may be formed by first forming or depositing a first and a second stack of blanket semiconductor sheets such as, for example, a first and a second stack of alternating blanket silicon (Si) sheets and sacrificial silicon-germanium (SiGe) sheets on top of a first blanket sacrificial insulation sheet. The first and the second stack of blanket semiconductor sheets may be separated by a second blanket sacrificial insulation sheet. This first and second stacks of blanket semiconductor sheets may then be patterned, for example, through a lithographic patterning and etching process to form the first raw stack of nanosheets 210 and the second raw stack of nanosheets 220. In the meantime, the first and the second blanket sacrificial insulation sheet may be patterned to become the first and the second sacrificial insulation sheet 201 and 202 respectively.
After forming the first and the second raw stack of nanosheets 210 and 220, one or more shallow-trench-isolations (STIs) 111 may be formed in the Si layer 103 of the semiconductor substrate 100, in areas not covered by the first and the second raw stack of nanosheets 210 and 220. More specifically, openings or recesses may first be created in the Si layer 103, a dielectric liner 110 such as SiN may then be formed to line the openings or recesses in the Si layer 103. Subsequently, dielectric materials may be used to fill the openings or recesses, for example through a deposition process, to form the one or more STIs 111.
Embodiments of present invention further provide forming one or more dummy gates 401 on top of the first and the second raw stack of nanosheets 210 and 220. For example, a layer of dummy gate material such as, for example, polysilicon or dielectric, may be blanketly deposited to cover the first and the second raw stack of nanosheets 210 and 220. A layer of hard mask material, such as silicon-nitride (SiN), may be formed on top of the dummy gate material and then lithographically patterned to form a hard mask 402. The pattern of the hard mask 402 is then transferred, for example through a selective etch process, onto the dummy gate material thereby forming the one or more dummy gates 401. The one or more dummy gates 401 may be formed in a direction perpendicular to the first and the second raw stack of nanosheets 210 and 220.
Additionally, embodiments of present invention provide removing and replacing the first sacrificial insulation sheet 201 with a self-aligned substrate isolation (SASI) layer 301 such as a dielectric layer of SIN, SiO2, silicon-boron-carbonitride (SiBCN), or other suitable materials, in a deposit and selective etch process. The deposit process may be an atomic-layer deposition (ALD) process and the selective etch may be a self-aligned etch process thereby resulting in the SASI layer 301. Similarly, the second sacrificial insulation sheet 202 may be removed and replaced with a self-aligned middle isolation (SAMI) layer 302, which may be a dielectric layer of SIN, SiO2, SiBCN, or other suitable materials as well and may be patterned together with the patterning of the first and the second stack of nanosheets 211 and 221 in a self-aligned etch process. Thereafter, inner spacers may be formed at end portions of the sacrificial sheets in the first and the second stack of nanosheets 211 and 221.
After forming the placeholders 811, 812, and 813 in the Si layer 103 of semiconductor substrate 100, S/D regions of a set of bottom transistors may be formed through an epitaxially growth process at the ends of the first stack of nanosheets 211. For example, a raw S/D region 311 may be formed for a first transistor 310 of a first stack of transistors 331, at a first end of the first stack of nanosheets 211. The raw S/D region 311 may later be patterned into a bottom S/D region, i.e., a first S/D region of the first transistor 310 of the first stack of transistors 331 as being described below in more details. In the meantime, a bottom S/D region 312 may be formed for the first transistor 310 at the second end of the first stack of nanosheets 211. In another example, a bottom S/D region 313 may be formed for a bottom transistor of a second stack of transistors 332 as is illustrated in
Embodiments of present invention further provide forming a middle-dielectric-insulator (MDI) layer 501 on top of the raw S/D region 311 of the first transistor 310. The MDI layer 501 may be silicon-carbon (SiC) or silicon-oxycarbide (SiOC), SiBCN, and may be formed in an area adjacent to SAMI layer 302. Further for example, an MDI layer 502 may be formed on top of the bottom S/D region 312 and an MDI layer 503 may be formed on top of the bottom S/D region 313. The MDI layers 501, 502, and 503 may be formed, for example, by depositing a dielectric material layer on top of the bottom S/D regions. The dielectric material layer is then recessed to form the MDI layers 501, 502, and 503. Generally, MDI layers are formed to insulate S/D regions of top transistors from S/D regions of bottom transistors in the structure of stacked transistors 331 and 332. However, according to one embodiment of present invention, at least one of the MDI layers such as the MDI layer 501 may be removed and replaced later to form a shared S/D contact as being described below in more details.
After forming the MDI layers 501, 502 and 503, embodiments of present invention provide forming top S/D regions of a set of top transistors such as forming a top S/D region 321, i.e., a second S/D region of a second transistor 320 of the first stack of transistors 331. The top S/D region 321 may be made through an epitaxial growth process at a first end of the stack of nanosheets 221. Embodiments of present invention further provide forming a top S/D region 322 at a second end of the stack of nanosheets 221. Further for example, a top S/D region 323 may be formed for a top transistor of the second stack of transistors 332 as is illustrated in
After forming the top S/D regions 321, 322, and 323 for the top transistors of the first and the second stack of transistors 331 and 332, dielectric material may be deposited to form a dielectric layer 510 filling spaces between the first and the second stack of transistors 331 and 332 and covering the top S/D regions 321, 322, and 323. A chemical-mechanical-polishing (CMP) process may be applied to planarize a top surface of the dielectric layer 510 and remove the hard masks 402 until the dummy gates 401 underneath the hard masks 402 are revealed or exposed for further processing.
After being revealed, the dummy gates 401 and the sacrificial sheets between the Si nanosheets may be selectively removed, in a replacement-metal-gate (RMG) process, and replaced with a metal gate 410, thereby forming the first and the second transistor 310 and 320 of the first stack of transistors 331. Similarly, and through the same or a different RMG process, a bottom and a top transistor of the second stack of transistors 332 may be formed as well.
Embodiments of present invention further provide forming a back-end-of-line (BEOL) structure 601 on top of the dielectric layer 510. The BEOL structure 601 provide signal powering and routing functionalities to the transistors through, for example, the one or more frontside S/D contacts and/or contacts to the gates of the transistors. A carrier wafer 701 is then bonded onto the BEOL structure 601 such that the semiconductor structure 10 may be flipped up-side-down for further processing from the backside.
Hereinafter, the description will be provided with the understanding that the processing is performed from the backside of the structure, although for the ease of illustration, figures and/or drawings of the semiconductor structure will still be provided in an upside-up fashion or orientation.
According to one embodiment of present invention, a spacer layer 802 may be formed through deposition onto sidewalls of the first opening 820 thereby reducing a width of the first opening 820. For example, in one embodiment, the spacer layer 802 may be a conformal dielectric liner having a width ranging from about 5 nm to about 7 nm, and may be made of, for example, SiC, SiOC, SiN or other suitable materials.
Embodiments of present invention may also remove the spacer layer 802 at the sidewalls of the first opening 820 thereby exposing the bottom surface of the first S/D region 3111 that were previously covered by and in contact with the spacer layer 802.
Next, embodiments of present invention provide filling the third opening 822 with a conductive material such as, for example, copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or other suitable contact materials to form a first portion 5211 of a shared S/D contact 5210. The conductive material may be filled in the third opening 822 using, for example, a CVD process, a plating process, or other suitable processes. A bottom surface of the first portion 5211 of the shared S/D contact 5210 may be in contact with the top surface of the first S/D region 3111.
The same conductive material, or a different conductive material, may be used to further fill the second opening 821, following the filling of the third opening 822, to form a second portion 5212 of the shared S/D contact 5210. The second portion 5212 of the shared S/D contact 5210 is wrapped around by the first S/D region 3111. Here, the first portion 5211 and the second portion 5212 together form the shared S/D contact 5210.
As is demonstratively illustrated in
Upon forming the shared S/D contact 5210, i.e., upon forming the second portion 5212 of the shared S/D contact 5210, embodiments of present invention provide continuing to fill the first opening 820 with the conductive material, or a different conductive material, to form a backside S/D contact 521. The backside S/D contact 521 may be self-aligned with the first S/D region 3111 and the bottom surface of the first S/D region 3111 is in direct contact with the backside S/D contact 521. Here, it is noted that first portion 5211, the second portion 5212, and the backside S/D contact 521 may together form a single backside S/D contact structure, particularly when a same conductive material is used to form the structure.
The same, or different, conductive material may be used to fill openings underneath other bottom S/D regions to form backside S/D contacts such as, for example, backside S/D contacts 522 and 523.
Various examples may possibly be described by one or more of the following features in the following numbered clauses:
It is to be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other high-level carrier) or in a multichip package (such as a ceramic carrier that has surface interconnections and/or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of various embodiments of present invention have been presented for the purposes of illustration and they are not intended to be exhaustive and present invention are not limited to the embodiments disclosed. The terminology used herein was chosen to best explain the principles of the embodiments, practical application or technical improvement over technologies found in the marketplace, and to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all contemplated and considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
