NSF Award
2403144
Today’s general-purpose processors follow the von Neumann model, where programs execute as a sequence of instructions. However, this serial execution proves to be too slow. Processors thus seek instructions that can safely execute in parallel to enhance performance. Yet, implementing parallelism in hardware is extremely complicated. The complexity renders processors inefficient and insecure, leading the industry's shift toward specialized hardware accelerators tailored to run specific programs exceptionally well. Unfortunately, these accelerators are costly and restrictive. To address these issues, this project proposes post-von Neumann, dataflow processors, that explicitly expose program parallelism to dramatically simplify hardware. Through new compilation software and simplified parallel hardware, the project aims to significantly improve energy efficiency and system correctness. These advancements will transcend von Neumann model limitations, fostering innovation while enhancing performance, efficiency, and security. The research will be conducted by a diverse team, including undergraduates through the NSF Research Experiences for Undergraduates program. Moreover, the investigators will develop an outreach program to educate K-12 teachers and the public on various computing models.<br/><br/>The key technical innovation of this award is the innately parallel dataflow representation of programs and a simple, spatial implementation of a dataflow processor. Moreover, the spatial architecture adopts a hierarchical, modular approach that enables scalability in multiple dimensions. Simplicity and modularity admit tractable formal models of the compiler, architecture, and hardware implementation, allowing investigators to prove correctness and security. The proposed architecture builds in security from the beginning, rather than trying to prove security after the fact, as researchers currently struggle to do for von Neumann architectures. Modularity further enables scalable compilation by breaking programs into smaller, independent units with a well-defined interface, each of which can be efficiently compiled onto the proposed architecture, and also enables near-data computation by co-locating data with its corresponding computation to overcome the rising cost of data movement. The resulting processor design promises to be the first a scalable, general-purpose architecture with provable correctness and security.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
