SHF: Small: Collaborative Research: Harvesting Wasted Time and Existing Circuitry for Efficient Field Testing

Information

  • NSF Award
  • 1812777
Owner
  • Award Id
    1812777
  • Award Effective Date
    10/1/2018 - 6 years ago
  • Award Expiration Date
    9/30/2021 - 3 years ago
  • Award Amount
    $ 93,491.00
  • Award Instrument
    Standard Grant

SHF: Small: Collaborative Research: Harvesting Wasted Time and Existing Circuitry for Efficient Field Testing

Digital integrated circuits (ICs) are the "brains" in the electronic devices used throughout modern society. It is essential that these devices work correctly and reliably - especially in critical applications such as autonomous vehicles, infrastructure, the financial system, and health care. In such applications, highly effective and efficient testing should be done in the field to identify problems that may arise after the device has been sent to the customer. Thus, in this project, new ways of using circuitry already present on modern ICs while efficiently creating, applying, and transporting field-based tests to different parts of the chip will be investigated. At the same time, educational opportunities made possible through the project will be pursued, including the use of research findings in courses, the involvement of graduate and undergraduate students in the research, and outreach to high school students through summer camps and research opportunities. The inclusion of members of underrepresented groups in these educational opportunities will be a focus of the investigators, who already have a proven record in mentoring such students in research. <br/><br/>To address the field-testing issues, three major tasks will be performed in this research. First, methods that use existing error-detection circuitry in an IC to make the field testing process more efficient will be explored. In particular, times when the IC is operating in normal functional mode will be used to test for the presence of some faults. Testing for those same faults in dedicated test sessions can then be avoided, reducing test time and the amount of time a circuit must be taken offline for test. Next, methods for effectively using otherwise wasted time during dedicated test sessions to detect faults will be explored. Finally, approaches that optimize the internal test network to efficiently send data used for test throughout a chip will be investigated. Taken together, these approaches should enable field-based test to achieve high fault coverage while minimizing test time, thus enhancing the reliability of devices that so many people depend upon every day.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

  • Program Officer
    Sankar Basu
  • Min Amd Letter Date
    5/18/2018 - 6 years ago
  • Max Amd Letter Date
    5/18/2018 - 6 years ago
  • ARRA Amount

Institutions

  • Name
    University of St. Thomas
  • City
    St. Paul
  • State
    MN
  • Country
    United States
  • Address
    2115 Summit Avenue
  • Postal Code
    551051096
  • Phone Number
    6519626038

Investigators

  • First Name
    Kundan
  • Last Name
    Nepal
  • Email Address
    kundan.nepal@stthomas.edu
  • Start Date
    5/18/2018 12:00:00 AM

Program Element

  • Text
    SOFTWARE & HARDWARE FOUNDATION
  • Code
    7798

Program Reference

  • Text
    SMALL PROJECT
  • Code
    7923
  • Text
    DES AUTO FOR MICRO & NANO SYST
  • Code
    7945