NSF Award
2417619
Modern integrated circuits (ICs) integrate billions of transistors into a single chip. Even key subsystems such as clock distribution networks, power delivery networks (PDNs), embedded memory arrays, and analog and mixed-signal systems can become incredibly complex, consisting of hundreds of millions of circuit components. As a consequence, it has become exceedingly difficult to model, simulate, optimize, and verify future ICs at a large scale using existing design methodologies. Recent research in spectral graph sparsification has made it possible to construct much sparser subgraphs while preserving important graph spectral properties such as the first few eigenvalues and eigenvectors of the graph Laplacian. These findings have already led to the development of highly efficient algorithms for solving large sparse matrices, partial differential equations (PDEs), and simulating large-scale circuit systems. However, existing spectral sparsification methods do not efficiently allow for updating the sparsified graph when only incremental changes are made to the original network. The algorithms and methodologies to be developed in this project will be transferred to technology companies, such as semiconductor and electronic design automation (EDA) companies, as well as social and network companies for potential industrial applications. Furthermore, the source code of the developed EDA algorithms will be made available to other researchers through collaborations. The project also includes compelling education, outreach, and course development plan. The primary research investigator plans to recruit K-12 students from local schools and get them involved in the latest research projects.<br/><br/>This research project aims to investigate scalable algorithms for incremental spectral sparsification of large graph Laplacians and integrated circuit networks. The framework will allow for efficiently handling large graphs that experience streaming edge insertions/deletions in sublinear time, and significantly accelerating SPICE-accurate modeling and simulations of large circuit designs that undergo frequent updates. This research will also investigate efficient approaches for incremental modeling and simulation of integrated circuits leveraging incremental spectral sparsification and involve close collaborations with leading industrial experts in circuit simulation to evaluate the proposed research. The success of the proposed research will potentially contribute to the advancements in spectral graph theory and EDA, leading to the development of highly scalable incremental algorithms for solving partial differential equations, sparse matrix problems, spectral graph partitioning, and design automation of large-scale ICs. <br/><br/>This project is co-funded by the Software and Hardware Foundations (SHF) and Discovery Research PreK-12 (DRK12) programs. DRK12 is an applied research program that supports STEM education PreK-12.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
