Patent Application
20210328384
This disclosure relates to the field of connector assemblies, more specifically to connector assemblies and their components suitable for use in high-speed data rate applications (e.g., at least 100 Gigabits per second (Gbps)).
This section introduces aspects that may help facilitate a better understanding of the inventions. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
To date, it has been challenging for high-speed data connector assemblies to control the temperatures produced by, for example, electronic circuits within plug modules that are connected to the assemblies while at the same time maintaining the alignment of conductors within the assemblies and reducing the effects of potentially deleterious, electromagnetic interference (EMI), among other things. In particular, it is challenging to control the temperatures reached within receptacle cages of an assembly.
Accordingly, it is desirable to provide solutions to these challenges.
The inventors describe various configurations of exemplary compact, high-speed multi-level, multi-port connector assemblies and their components. The inventive assemblies and components are configured to control temperatures and/or alignment while reducing EMI, among other things.
In one embodiment, an inventive high speed, multi-level, multi-port connector assembly may comprise: a shielded cage; and a connector within the cage comprising an internal housing composed of a plastic and configured to enclose one or more wafers, a first supporting side plate on one side of the housing and a second supporting side plate on an opposite side of the housing, wherein each side plate is configured to receive and hold tail portions of the one or more wafers to align tail edges of each tail portion within the same geometrical plane. In embodiments, the plastic may comprise a high-temperature Liquid Crystal Polymer (LCP) and the one or more wafers may equal 1 to 8 wafers, for example.
A number of different internal housings are provided. In one embodiment, an inventive, internal housing encloses portions of a top port and portions of a bottom port, while in another embodiment an internal housing encloses portions of a top port and not a bottom port. When the housing does not enclose a bottom port such a housing may nonetheless comprise one or more notches on both sides to make contact with a bottom port to, for example, support a top port and housing. Alternatively, an alternative housing may comprise a top port support structure fixably configured between a top port and a bottom port, where the top port support structure may comprise one or more apertures, each aperture configured to receive a respective top port protrusion to fixably position the top port support structure.
The housing may be secured in a number of different ways. In one embodiment a housing may comprise one or more board locks to secure the housing to a PCB, where the one or more board locks may be composed of a deformable metal or plastic.
It should be understood that one or more of the wafers of the inventive connector assembly may comprise wafers of a top port wafer assembly while others may comprise wafers of a bottom port assembly, for example.
Each of the wafers of the inventive connector assembly may comprise one or more wafer protrusions, where the first supporting side plate and second supporting side plate may be configured to receive the one or more wafer protrusions and the side plates may be composed of a metal such as a stainless steel or a plastic, such as LCP, for example. In more detail, the first supporting side plate and second supporting side plate may be configured with one or more apertures to receive the one or more wafer protrusions, where each corresponding wafer protrusion and aperture may be configured such that each protrusion is structurally biased to a corner of a respective aperture to control the tail portions of each wafer such that the tail portions of the wafers are within the same geometric plane as a PCB that is also connected to the assembly, for example.
The inventive connector assembly may further comprise a top port tail alignment and support structure (e.g., made form a non-conductive material) comprising one or more protrusions, where the first supporting side plate and second supporting side plate may be configured to receive the one or more protrusions of the top port tail alignment and support structure. Such an inventive, top port tail alignment and support structure may further comprise one or more attachment structures for attaching the structure to a printed circuit board (PCB), where (i) some of the one or more attachment structures may compose a non-conductive plastic covered with a glue and some of the attachment structures may compose a solderable, plated, non-conductive plastic or a metal, or (ii) one or more of the attachment structures may compose a non-conductive plastic covered with a glue, or (iii) one or more of the attachment structures may compose a solderable, plated, non-conductive plastic or a metal, for example.
In addition an inventive assembly may further comprise a bottom port wafer assembly that may be configured to be connected to a PCB by surface-mount technology, a ball grid array, solder charge, press-fit, or by an optical fiber technique, for example. Further, in embodiments, an inventive assembly may additionally comprise a conductive, bottom port tail alignment and support structure configured to align tail edges of each tail portion one or more terminals of bottom port wafers of the bottom port assembly and, yet further, may be configured as a ground reference plane structure surrounding differential high-speed terminals of bottom port wafers and electrically mirror an electrical ground plane structure formed on the surface of a PCB mated to the connector assembly. It should be understood that such a conductive, bottom port tail alignment and support structure need not be connected to a PCB, and may be configured separated from the surface of a PCB by a distance of 0.25-0.50 millimeters, as one non-limiting distance for example In an embodiment, the conductive, bottom port tail alignment and support structure may comprise a plated plastic or a stainless steel and may be configured as an integral part of a bottom port wafer assembly, for example.
In an embodiment, a conductive, ground plastic shield element may be configured to cover the wafers of the bottom port wafer assembly, where such a conductive, ground plastic shield element may comprise a plated plastic, a plated ceramic, or a hybrid laminate with dielectric and conductive elements, or another conductive material with a dielectric coating.
Further, such a conductive, ground plastic shield element may comprise multiple, separate elements.
In embodiments, the inventive connector assembly may comprise quad-small form-factor pluggable input/output (I/O) connector or a quad-double density small form-factor pluggable I/O connector, for example.
Each of the terminals of the inventive connector assembly may comprise terminals overmolded with a plastic or a plated plastic structure, wherein the terminals comprise differential high-speed terminals, low-speed terminals, power terminals and ground terminals, and each differential high-speed signal terminal may be configured with another differential high-speed signal terminal on one side and a ground terminal on the other side, for example
In embodiments, each differential high-speed signal terminal may transport signals up to at least 100 Gigabits per second (Gbps), for example Further, a section of each wafer that corresponds with low-speed terminals and power terminals may electrically isolate a set of differential high-speed terminals that are adjacent to the low-speed terminals and power terminals from another set of adjacent differential high-speed terminals in the same wafer from deleterious electrical interference from one another.
The inventive connector assemblies provided by the present inventors may also include housings that comprise one or more latches on either side of the housing configured to fix or lock the top of each wafer in position, where each latch may be configured as a section of the housing and is operable to deflect to secure the one or more wafers.
In addition to alignment features described above, the inventive connector assemblies may comprise one or more conductive ground shield elements that may be configured to cover some or all terminals of one or more wafers. Accordingly, in some embodiments where each of the one or more wafers supports one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals and one or more ground terminals, an inventive, conductive ground shield may be positioned between some of the one or more wafers.
For example, the one or more conductive ground shields may comprise two or more separate shields with a gap between each shield configured to cover differential high-speed transmission terminals and two or more separate shields with a gap in between each shield configured to cover the high-speed reception terminals to allow for temperature control (i.e., air flow through the gap and over the uncovered low-speed and power terminals). In another embodiment, a first one of the one or more conductive ground shield elements may be configured to cover one or more differential high-speed terminals of one of the wafers and a second one of the one or more conductive ground shield elements may be configured to cover additional differential high-speed terminals of the same wafer. Further, the first and second conductive ground shields may be configured with a gap there between, the dimensions of the gap corresponding to an area of a total number of low-speed and power terminals in a row of terminals plus one terminal multiplied by a required pitch of the terminals. In one embodiment, the gap may comprise 4.0 millimeters, for example.
In an embodiment, one or more conductive ground shield elements may be configured along a vertical axis (with or without a gap in between) or, may be configured along an axis other than a vertical axis (with or without a gap in between). Regardless of the orientation of the shield or shields, in embodiments a ground shield element may be configured to cover one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals and one or more ground terminals of a respective wafer, for example
As noted above and elsewhere herein, one or more differential high-speed terminals may be covered by a conductive ground shield element(s). When the one set of differential high-speed terminals are transmission elements and another set of are receiving elements, then one conductive ground shield element (a “first” one) may cover the transmission terminals and another conductive ground shield element (a “second” one) may cover the receiving terminals, for example.
Further, where each of the one or more wafers supports one or more differential high-speed terminals, and the connector assembly may be further configured to position a conductive ground shield at a first distance proximal to one or more of respective differential high-speed terminals of one or more wafers to generate a field affinity between the respective ground shield and the respective differential high-speed terminals.
Inventive connector assemblies provided by the inventors may include additional temperature controls in addition to the aforementioned gaps in a shield. For example, the low-speed terminals and power terminals in the same row of a wafer may be configured to be offset from low-speed terminals and power terminals in another row of another wafer.
For example, the housing described above and elsewhere herein may comprise one or more gaps to allow air flow through and remove heat generated by at least low-speed and power terminals of one or more wafers.
The inventors also provide connector assemblies that include inventive combinations of ground conductors and plastic ground shields. For example, in one embodiment, one or more insert molded, metal ground conductors (e.g., composed of a copper, a copper alloy, a gold or a platinum) may each be stitchably mated with a ground conductive section that is a part of a plastic, ground shield element, for example, where the ground conductive section or sections may comprise a conductive plastic, a conductive metal, a conductive or plated plastic or a hybrid laminate with dielectric and conductive elements, for example.
Each of the stitched, one or more insert molded, metal ground conductors may comprise a continuous conductive structure, for example.
To reduce unwanted voltage gradients in connector assemblies, the inventors provide one or more wafers (of a top and/or bottom wafer assembly), each of which may comprise dual ground paths, where a first path may be formed by individual ground conductors and a second ground path may be formed by conductive fingers and a conductive, plated plastic shield. The inventors believe that the inventive dual ground paths substantially reduce a shared, composite impedance along the length of each path where the shared, composite impedance may be less than either impedance of an individual path.
With regard to the inventive fingers just described, each of the conductive fingers may be electrically and galvanically connected to a contact portion of one of the individual ground conductors and may comprise fingers of a conductive ground plate, for example. Alternatively, each of the conductive fingers may comprise insert-molded fingers of a plastic, ground shield structure, for example.
In addition to inventive connector assemblies, the inventors provide related inventive methods for that parallel the inventive connector assemblies.
The present invention is illustrated by way of example and is not limited by the accompanying figures in which like reference numerals indicate similar elements and in which:
Specific embodiments of the present invention are disclosed below with reference to various figures and sketches. Both the description and the illustrations have been drafted with the intent to enhance understanding. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements, and well-known elements that are beneficial or even necessary to a commercially successful implementation may not be depicted so that a less obstructed and a more clear presentation of embodiments may be achieved.
Simplicity and clarity in both illustration and description are sought to effectively enable a person of skill in the art to make, use, and best practice the present invention in view of what is already known in the art. One of skill in the art will appreciate that various modifications and changes may be made to the specific embodiments described below without departing from the spirit and scope of the present invention. Thus, the specification and drawings are to be regarded as illustrative and exemplary rather than restrictive or all-encompassing, and all such modifications to the specific embodiments described below are intended to be included within the scope of the present invention.
The detailed description that follows describes exemplary embodiments and is not intended to be limited to the expressly disclosed combination(s). Therefore, unless otherwise noted, features disclosed herein may be combined together to form additional combinations that were not otherwise shown for purposes of brevity.
The disclosure provided herein describes features in terms of preferred and exemplary embodiments thereof. Numerous other embodiments, modifications and variations within the scope and spirit of the appended claims will occur to persons of ordinary skill in the art from a review of this disclosure.
As used herein and in the appended claims, the terms “comprises,” “comprising,” or any other variation thereof and “includes” or “including” and any variation thereof are intended to refer to a non-exclusive inclusion, such that a process, method, article of manufacture, or apparatus that comprises a list of elements does not include only those elements in the list, but may include other elements not expressly listed or inherent to such process, method, article of manufacture, or apparatus.
As used herein the terms “a” or “an” mean one or more than one. As used herein, the term “plurality” means two or more than two. As used herein the term “another” means at least a second or more.
Unless otherwise indicated herein, the use of relational terms, if any, such as “first” and “second”, “top” and “bottom”, “left” or “right” and the like are used solely to distinguish one element, component, entity or action from another element, component, entity or action without necessarily requiring or implying any actual such relationship, order or importance between such elements, components, entities or actions.
The terms “including” and/or “having”, as used herein, are defined as comprising (i.e., open language). The term “coupled”, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The use of “or” or “and/or” herein is defined to be inclusive (A, B or C means any one or any two or all three letters) and not exclusive (unless explicitly indicated to be exclusive); thus, the use of “and/or” in some instances is not to be interpreted to imply that the use of “or” somewhere else means that use of “or” is exclusive. Terminology derived from the word “indicating” (e.g., “indicates” and “indication”) is intended to encompass all the various techniques available for communicating or referencing the object/information being indicated. Some, but not all, examples of techniques available for communicating or referencing the object/information being indicated include the conveyance of the object/information being indicated, the conveyance of an identifier of the object/information being indicated, the conveyance of information used to generate the object/information being indicated, the conveyance of some part or portion of the object/information being indicated, the conveyance of some derivation of the object/information being indicated, and the conveyance of some symbol representing the object/information being indicated.
As used herein the phrases “high-speed”, “high-speed signal”, “high-speed data”, “high-speed data signal” and the like are meant to be synonymous unless the context or knowledge of one skilled in the art indicates otherwise. One example of a high-speed data signal may be at least 100 Gbps signal.
Similarly, the phrases “low-speed”, “low speed signal”, low-speed data”, “low-speed data signal” and the like are meant to be synonymous unless the context or knowledge of one skilled in the art indicates otherwise. Generally, low-speed signals may be considered signals that are associated with control and system maintenance as opposed to signals associated with information transfer. Further, a non-limiting low speed signal may be associated with a data transmission rate below 1-Gbps and typically does not require specialized signal conveyance structures, such as ground supported waveguides. For the sake of brevity, reference to “low-speed terminals” may sometimes include power terminals depending on the context.
As used herein the phrase “configured to” or “operable to” means “functions to” unless the context or knowledge of one skilled in the art indicates otherwise.
As used herein the phrase “a to n” indicates a first element “a” and a last element “n”. For example, one or more apertures, where “a” is a first aperture and “n” is a last aperture. Further, the letters “n” or “nn” indicate one exemplary element among a number of similar elements, e.g., aperture 11n.
As used herein the terms “exemplary” and “embodiment” mean one or more non-limiting examples of an inventive connector assembly, inventive component or element, inventive process or part of an inventive process.
As used herein the words “terminal” and “conductor” may be used synonymously unless the context or knowledge of those skilled in the art dictate differently.
As used herein the words “hold” and “fix” may be used synonymously unless the context or knowledge of those skilled in the art dictate differently.
Referring now to
In more detail, the cage 2 may be positioned over portions of the top and bottom ports 8a, 8b of a connector to provide shielding for at least the connector and other components within the cage 2 from a range of electromagnetic interference (EMI).
Referring now to
In an embodiment, the components 2a, 2b, 2c and 2d may be composed of a sufficiently conductive metal or conductive plated plastic, for example, though these are just two of the types of conductive materials that may be used. Further, these shielded, component structures may be comprised of one or more differently configured perforated and/or non-perforated apertures to allow air flow and contribute to the control of the temperature of components making up the assembly 1. Such apertures may also be configured to reduce the effects of EMI.
In more detail, the front end-shield 2d may comprise one or more associated openings, apertures or vents 5a (collectively “apertures”) that are operable to allow air to flow through into, and/or out of, the interior of the cage 2 in order to reduce the temperature of components enclosed by the cage 2, such as the connector 1a. Further, the front end-shield 2d may further comprise a plurality of conductive, deformable structures or elements 6 that may be formed around part, or substantially all, of the perimeter of the shield 2d. In an embodiment, another device (e.g., paddle card, see component 7b) having corresponding, opposed deformable structures or elements (not shown) may be pushed onto and positioned over elements 6 such that the other device can be said to be “plugged into” port 8b of the connector 1a via a card slot in port 8b. The opposing forces of the two opposing sets of deformable elements along with one or more latches (e.g., one latch usually located on each side of the cage 2, near the front, described elsewhere herein) secures the other device to port 8b of the connector 1a. Yet further, in an embodiment, such a “plugged in” configuration forms a continuous EMI shielding seal. Further, because the elements 6 are conductive an electrical ground path may be established.
Continuing, the assembly 1 may further comprise a top heat sink 2g and second fastening clip 2h and an internal, unitary (e.g., one-piece) central housing 2j enclosing the bottom and top port 8a, 8b, where a paddle card 7b is illustrated as being inserted into the bottom port 8b.
Optionally, the assembly 1 may further comprise a cage midsection that comprises an internal heat sink 2e and fastening clip 2f.
In an embodiment, a top heat sink 2g may extend substantially the full length of the cage 2 while the internal central housing 2j is within the cage 2.
While
Continuing, the first fastening clip 2f may comprise one or more deformable elements 2ff that are operable to apply a spring-like force on the internal heat sink 2e which is within the sides of the cage 2. As a result of such a force the heat sink 2e may make contact with components within the cage 2, such as the top port. Turning to the second fastening clip 2h, in an embodiment the clip 2h may be operable to apply a force to the top heat sink 2g so that the heat sink 2g makes contact with components enclosed by, and within, the cage 2, such as optical-to-electrical (O/E) and/or electrical-to-optical (E/O) conversion circuitry, active devices and/or retiming circuitry (not shown), for example.
In embodiments of the invention, the inventive assembly 1 may comprise additional components other than the front end-shield 2d that are operable to reduce the temperature of components of the assembly 1. For example, the cage 2 and shielded back plate 2c may also comprise one or more correspondingly associated apertures 5b, 5c, respectively, that are configured to allow air to flow through to the interior of the cage 2 in order to reduce the temperature of components enclosed by the cage 2 (see
Depending on the embodiment, one or more of each of the above described apertures may be shaped as a hexagon. Alternatively, one or more of each of the above described apertures may be shaped as a circle to name just two of the many different types of aperture shapes that may be utilized and still allow the apertures to function as temperature controls to reduce the temperature of components of an inventive assembly. Further, a given set of associated apertures may include a subset of hexagonal shaped apertures and a subset of circular shaped apertures, for example. In embodiments, a surface area and/or structure of a component of an inventive assembly (e.g., components 2a, 2c and 2d) may allow inclusion of more hexagon-shaped apertures than circular-shaped apertures due to the dimensions of the component and aperture (i.e., more hexagon-shaped apertures may be formed in a component than circular-shaped apertures).
Further, each aperture may be configured to have a width to reduce the effects of EMI on components within an interior of the assembly 1 depending on the frequency or frequencies sought to be attenuated and may be configured to have an extruded depth to reduce the effects of EMI on interior components depending on the amount of attenuation (e.g., in dB) desired. For example, the smaller the width of the aperture the higher the upper cutoff frequency that can be attenuated while a deeper in extruded depth aperture can attenuate more of a given signal at a given frequency (i.e., reduce the decibel level of a signal). In an embodiment, an aperture used as a part of an inventive assembly may have a width and extruded depth (i.e., may be sized) that corresponds to an amount of attenuation desired.
Further, in embodiments a given sized aperture within a group of apertures may be repeated aperiodically to avoid aperture to aperture enhancement or “gain” at a given frequency or band of frequencies. Still further, exemplary apertures may each have the same width and, therefore, may attenuate signals at substantially the same range of frequencies. However, by changing the extruded depth of a given aperture such an apertures would attenuate a given signal at a given frequency more than an aperture with a lesser (shorter) extruded depth (i.e., an apertures with a greater extruded depth may reduce the decibel level of a signal more than an aperture with a shorter extruded depth).
In an embodiment, the thickness and composition of the cover 2a of the cage 2 may be set to achieve a desirable EMI, attenuation level. For example, a thin thickness composed of a given material may attenuate unwanted frequencies less than a thicker thickness of the same given material. Still further, the cover 2a of the cage 2 may be comprised of multiple layers of the same, or different, attenuating materials (e.g., layers can be composed of metallic material while others can be composed of other conductive materials, such as plated plastics).
Referring now to
Also shown in
As depicted, in an embodiment the connector 1a may be configured as a shielded high-speed, multi-level, multi-port connector with temperature and alignment control features. In one embodiment, the connector 1a may comprise an input/output (I/O) connector, such as those that may be used for optical small form-factor pluggable applications or double density optical small form-factor pluggable applications (e.g., QSFP, OSFP, CDFP applications). As configured, the assembly 1 that includes the connector 1a may be referred to as a shielded high speed, multi-port, multi-level connector assembly 1 with temperature and alignment controls, among other features.
In more detail, referring now to
Further, each terminal may have three sections: a tip, top or contact portion (collectively “contact portion”) that makes contact with a pluggable card, such as cards 7a, 7b, an opposite tail portion and a central body portion between the contact and tail portions. As shown in
As will be seen throughout the drawings herein, terminals of each wafer may be arranged in one or more rows to make contact with a pluggable card (see
In embodiments, the contact portions of one or more terminals of a wafer may be arranged to form a top row of terminals in contact with the card slot or a bottom row of terminals in contact with the card slot, for example (again see
The conductive terminals that are a part of wafers 15a to 15n may be configured to conduct electrical signals. Additionally, in an alternative embodiment, the terminals may also be configured to feed electrical signals to E/O conversion circuitry or receive electrical signals from O/E conversion circuitry, for example In the latter case, such O/E or E/O conversion circuitry may be included in a mated plugged-in module or card (e.g., component 7b) and then connected to respective conductive wafers of connector 1a.
In many instances, the signals being conducted through terminals of a wafer, or through additional O/E and E/O conversion circuitry may generate a substantial amount of heat during operation. Thus, as described herein, the inventors provide inventive solutions to control such temperatures.
Referring to
In embodiments of the invention, the side plates 9a, 9b may be configured with one or more apertures 11a to 11n, where one or more of the apertures may be configured to receive the before-mentioned one or more wafer protrusions of each wafer 15a to 15n of the top port wafer assembly 10 (see elements 10a to 10n in
Further, the housing 2j may comprise one or more latches 12a to 12n on either side of the housing 2j (see
In more detail, side surfaces s2 and SB are line-to-line (i.e., non-overlapping) as are side-surfaces s1 and SA. On the other hand side-surfaces s3 and SC overlap one another, as do side surfaces s4 and SD. In an embodiment, the overlapping side surfaces create an interference fit/compression fit force that is exerted on protrusion 10n and directs the protrusion 10n towards the upper left corner c1. Therefore, the surfaces near c2 (e.g., s2 and SB and s1 and SA) will be forced closer to the corner c2, and surfaces (e.g., s3 and SC and s4 and SD) will be forced farther away from corner c2. In an exemplary embodiment, surfaces s3 and SC and s4 and SD may be 0.03 millimeters farther away from corner c2 than surfaces s2 and SB and s1 and SA are from corner c2, for example.
Thus, it can be said that the protrusions 10a to 10n are “biased” to the top left corner c1, for example. It should be understood, however, that biasing towards the top left corner is merely exemplary. In alternative embodiments, the protrusion 10n may be biased towards any one of the four corners provided the overlapping side surfaces are correctly configured, and the same or similar distance differences are achieved.
Such exemplary, biased protrusions are among one of the inventive alignment control features discovered by the present inventors because the such biased protrusions control the planarity and position of the tail portions of the wafers 15a to 15n as the wafers are connected to the main PCB 3 using surface mount technology (SMT), for example More particularly, such biased protrusions help control the tail portions of terminals of each wafer 15a to 15n to allow the tail edges of each tail portion of a terminal to be aligned in the same plane (i.e., within the same geometric plane as the PCB 3). Absent such biasing, a tail height of one or more of the terminals of wafers 15a to 15n may vary and, thus, the tail edges may not be co-planar (i.e., would be mis-aligned).
Yet further,
In sum, each exemplary side plate 9a, 9b may be configured to receive protrusions 14a to 14n of a tail alignment and support structure 14 and wafer protrusions 10a to 10n to hold each of the plurality of wafers 15a to 15n in order to align tail edges 30a′ to 30n′, 31a′ to 31n′ and/or 32a′ to 32n′ of each tail portion within the same geometrical plane as a PCB, like PCB 3.
As shown in
In the series of figures making up
Similar to before, each side plate 9aa, 9ab and 9ac may be configured to receive protrusions of a tail alignment and support structure and wafer protrusions to hold or fix each of the plurality of wafers and to help align tail edges of each tail portion of terminals of each wafer within the same geometrical plane as the PCB 3.
For ease of understanding the inventors will now set forth a discussion of the inventive features of a top port wafer assembly (e.g., assembly 10) that may be incorporated into an inventive connector assembly, such as assembly 1. Further on herein, the inventors will set forth a discussion of a bottom port wafer assembly. That said, it should be understood that one or more features of an inventive top port wafer assembly may be utilized in an inventive bottom port wafer assembly, and vice-versa.
In an embodiment, the top port wafer assembly 10 may comprise one or more separate power, high-speed and low speed communication signal conductors and ground conductors (sometimes referred to as “terminals”) that form a part of separate ground, power and communication signal paths. In embodiments, each high-speed conductor/terminal may be configured to transport signals up to at least 100 Gigabits per second (Gbps) and, in alternative embodiments, exceeding 100 Gbps may be transported by the high-speed signal terminals of the assembly 10 (as well as the bottom port assembly). In alternative embodiments, communication signals up to 160 Gbps may be transported by the high-speed terminals of an assembly.
In one embodiment, top port wafer assembly 10 may comprise differential high-speed terminals, centrally positioned low-speed/power terminals and ground terminals, respectively. Said another way, differential high-speed terminals may be positioned on the left and right side of each wafer of the top port connector assembly 10 while the low-speed or power terminals may be positioned centrally between the high-speed terminals, for example (i.e., “on-center”). In an embodiment, this “on-center” section of each wafer in assembly 10 that corresponds with the positioning of low-speed terminals and power terminals may electrically isolate differential high-speed terminals on opposite sides of the low-speed terminals and power terminals from deleterious electrical interference. In more detail, this section may function to isolate or “block” one set of high-speed terminals configured to conduct communication (data) signals on one side of the low-speed terminals and power terminals from deleterious electrical interference caused by communication (data) signals being conducted by a second set of high-speed terminals on the opposite side of the same low-speed terminals and power terminals. This “blocking” or isolation section may reduce deleterious electrical crosstalk between the opposed differential high-speed terminals as well as improve the signal-to-noise performance for the respective high-speed data signals being transported by the high-speed terminals.
Referring now to
Further, as depicted, there is no conductive ground shield covering the low-speed and power terminals 31a to 31n within gap “g1”. Said another way, in an embodiment, first and second conductive ground shields 16a, 16n may be configured with a gap g1 there between, the dimensions of the gap g1 corresponding to an area of a total number of low-speed and power terminals 31a to 31n plus one terminal multiplied by a required pitch of the terminals (length times width) (e.g., if the area of 4 terminals is “X” then the dimensions of gap g1 would be equal to the (area of X plus the area of ¼X) times the terminal pitch. For the reader's benefit, if an exemplary terminal pitch is 0.8 millimeters and there are five exemplary low-speed and power terminals then the gap g1 may be 4.0 millimeters, for example
Because the exemplary conductive, multi-piece ground shield does not cover all of the terminals of the wafer, heat generated and dissipated by at least the uncovered low-speed and power terminals 31a to 31n during operation of at least the low-speed and power terminals 31a to 31n may be cooled by air that flows through and over the terminals, for example Said another way, air that flows over the terminals may remove heat that is generated by such terminals, for example In addition, in embodiments where one of the conductive ground shields 16a is configured to cover high-speed transmission/transmitter terminals and the other 16n is configured to cover high-speed reception/receiver terminals the separation of the ground shields may function to electrically isolate the transmission terminals from the reception terminals, for example, in order to reduce the effect of deleterious, electrical interference and/or noise. The separate conductive ground shield(s) 16a to 16n is just one of the inventive temperature and electrical controls discovered by the present inventors. The use of multiple, separated (e.g., two) elements 16a, 16n may be referred to herein as a “split, conductive ground shield” or simply as a “split-shield”.
Though the shield in
Yet further, the two shields 16a, 16n may be combined into a single shield having an opening, vent or aperture in its central portion to allow for air flow and temperature control. Said another way, one (or more) conductive ground shield elements may be configured to cover some or all of the differential high-speed terminals of a wafer.
As shown the low speed/power terminals in rows 3 and 4 may be offset to the left by 1/2 pitch, while the terminals in rows 1 and 2 may be offset to the right by ½ pitch. In embodiments, the offsets allow the terminals in each row 1 to 4 to line up and allow air to pass through. In an embodiment, the distance a terminal (e.g., 31a to 31n) may be offset from the vertical axis Y” may be ½ pitch, for example
In addition, by configuring one set of terminals in a row offset from a vertical axis “Y” the terminals (e.g., low-speed and power terminals) may be more easily aligned.
Referring now to
In more detail, each of the one or more wafers 15a to 15n supporting one or more differential high-speed terminals may have a conductive ground shield positioned at a first distance proximal to its respective differential high-speed terminals in order to generate a field affinity between the respective ground shield and the differential high-speed terminals. In an embodiment, the differential high-speed terminals of each wafer 15a to 15n may be configured to conduct a communication data signal at a particular power level. Accordingly, a corresponding, respective ground shield 16aa to 16an may function as a conductive ground reference structure that is positioned in close proximity to respective terminals of a given wafer 15a to 15n to generate a field affinity. That is to say, the close proximal positioning of a respective ground shield 16aa to 16an to its respective wafer 15a to 15n and included terminals functions to electrically couple the signals (e.g., high-speed data signals) being conducted within the terminals to a respective shield 16aa to 16an (referred to as signal or field “affinity”).
To create such a field affinity in an inventive connector assembly, in an embodiment, an exemplary respective shield, for example shield 16ac in
In embodiments, this field affinity may be generated between each wafer 15a to 15n and its respective, positioned shield 16aa to 16an. Because of this field affinity no shielding is required between wafers 15b and 15c.
Exemplary, non-limiting distances h1 and h2 may be 0.30 millimeters and 2.40 millimeters, respectively.
Yet further, in an embodiment, the first distance h1 should be smaller than a third distance between any two differential signal terminals of a given wafer (e.g., in
Referring to
Referring now to
It should be understood that while the description above has described split-shields, this is merely exemplary. Alternatively, an inventive conductive ground shield for a wafer (e.g., top port wafer or bottom port wafer) may comprise a single element (i.e., single piece). Accordingly, in an alternative embodiment a conductive ground shield element may be configured to cover one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals and one or more ground terminals of a respective wafer (e.g., one shield per respective wafer).
For example, referring now to
In addition to temperature and alignment control features, the inventors also provide inventive methods and structures that combine metal ground conductors/terminals and plastic conductive ground shields.
Referring now to
In these embodiments the ground conductive sections 23a to 23n may comprise a conductive plastic operable to function as a ground path segment that may connect one conductive metal section 22a to another metal section 22n for example.
Though
It should be noted that stitching conductors/terminals of a wafer is one method of connecting conductors. Alternatively, conductors/terminals may include a support structure to connect the terminals of a wafer to a top port module nose-piece, for example.
Ground conductive sections 23a to 23n of a ground shield element 16a″, 16n″ may be composed of a metal or a conductive or plated plastic or a hybrid laminate with dielectric and conductive elements such as PCB sections. For example, in
It should be noted that sections 22a to 22n may be a continuous conductive structure rather than be separated into sections, for example.
In addition to providing inventive temperature and alignment control features the inventive connection assembles provided by the inventors may also include features that reduce an impedance of a respective ground path as well as reduce deleterious electrical crosstalk. For example, in embodiments of the invention the inventors provide for inventive connector assemblies that include electrical ground structures that function to maintain substantially the same voltage gradient (i.e., voltage difference) along substantially the length of the ground structure. While a zero-voltage gradient along an entire ground structure may not be practically achievable, in embodiments of the invention the ground structures discovered and provided by the present inventors minimize such a gradient along substantially the entire structure at operating temperatures. The ability to minimize such voltage gradients along substantially the entire ground structure provides the inventive connector assemblies with high quality ground reference structures that in-turn may reduce conducted crosstalk and even reduce coupled crosstalk between terminals providing a reduction of shared voltages as well as providing an effective ground drain for any induced or coupled voltages due to electrical noise.
For example, the inventors provide connectors that include structures that are configured to form dual ground paths. Referring now to
As shown, a view of a top port ground path assembly 10″ may comprise dual ground paths, where one ground path may be formed by the individual ground conductors 30a to 30n and the other ground path may be formed by conductive, deflectable, spring “fingers” or tabs 28a to 28n (collectively “fingers”) of an insert-molded, conductive ground plate 28 and conductive, plated plastic shield 21a. In more detail, each of the fingers 28a to 28n may be inserted into channels 36a to 36n formed in the shield 21a.
In an embodiment, each of the ground conductors 30a to 30n may function as a first ground path that comprises a structure that is connected to a terminal of an input/output module (e.g., card 7b) on one end, is positioned parallel and inline to respective differential signal conductors, and is connected on an opposite end to the surface of a PCB (e.g., PCB 3).
When assembled, each of the fingers 28a to 28n may be electrically and galvanically connected to (i.e., in contact with) a respective contact portion of a ground conductor 30a to 30n (i.e., a tip of conductor 30a to 30n), thereby functioning to provide a portion of a second ground path. The second ground path may pass from such a contact point, through a respective finger 28a to 28n and conductive plate 28 and then through the conductive, plated plastic 21a.
Though the figures and description herein describes a second ground path formed with respect to differential high-speed terminals 32a to 32n, it should be understood that similar additional ground paths may be formed with respect to low-speed terminals 31a to 31n as well. In either case (high-speed and low speed applications) the inventors discovered that the formation of dual or multiple ground paths provides an overall improvement in the integrity of an assembly's ground path structure. This ensures that the electrical impedance of the ground structure and steady-state resistance along the length of the ground path is controlled. The ability to control impedances and resistances further allows the control of the temperature of ground-associated power terminals/conductors where the dual ground path shares an electrical current (i.e., the lower the resistance, the less power may be lost or dissipated) when such power conductors are conducting higher currents, for example
As noted herein, the shield 21a may be a plated plastic. Alternatively, shield 21a may be composed of a plated ceramic (i.e., ceramic with a conductive flashing), plated metal or another conductive material with a dielectric coating such as a nickel, tin, gold or copper coating, for example Though the conductive, deflectable fingers are shown as part of an overall plate, it should be understood that this is merely exemplary. Alternatively, each of the fingers may be insert molded into a respective plastic, ground shield structure, for example.
It should be note that in an embodiment that includes a discrete finger type of structure, terminals that can be supported by a redundant isolated ground path, could take advantage of the overall lower longitudinal resistance along the path to board termination and thus share in the advantage of reduced path resistance and have lower heat generation in a power delivery function.
Other dual ground path structures/configurations may also be included in an inventive assembly. For example,
In each of the dual ground paths described herein, each path has an associated voltage difference that can be measured between opposite ends of the path (e.g., a path from the tip of each finger 28a to 28n to a PCB 3 or from the top of each conductor 30a to 30n to a PCB 3) due to the impedance of each path. In embodiments, the existence of dual ground paths substantially reduces a shared, composite impedance along the length of each path. For example, if the first path has an impedance of Z1 and the second path has an impedance of Z2, then the shared, composite impedance Z3 would be less than Z1 or Z2 and may be given by the relationship: Z3=1/[(1/Z1)+(1/Z2)].
Referring now to
The structure 14 may comprise tail alignment protrusions 14a to 14n, each of which may be inserted into apertures of, or affixed to, a side plate 9a, 9b (see
The inventors now turn their attention to a bottom port wafer assembly. Recall that assembly 1 in
In one embodiment the bottom port wafer assembly 40 may be configured to be connected to the PCB 3 using SMT, for example In alternative embodiments, the bottom port wafer assembly 40 may be connected to the PCB 3 using a ball grid array, solder charge, press-fit, SMT, an optical fiber technique or a combination of such techniques, for example.
Similar to the top port wafer assembly, each wafer of the bottom port wafer assembly 40 may comprise one or more separate power and low-speed communication signal conductors/terminals, one or more differential high-speed conductors/terminals and one or more ground conductors. In embodiments, at least exemplary high-speed communication signals up to, and exceeding, 100 gigabits Gbps may be transported by the high-speed signal conductors of the assembly 40. In alternative embodiments, communication signals up to 160 Gbps may be transported by the high-speed conductors.
In one embodiment, the low-speed/power terminals may be positioned in the center of a wafer, for example. Further, each differential high-speed terminal may be configured such that another differential high-speed signal terminal is positioned on one side and a ground terminal is positioned on the other side.
In
The bottom port wafer assembly may also comprise dual ground path configurations similar to those described previously. For example, one ground path may be formed by the individual ground conductors 43a to 43n and the other ground path may be formed by conductive, deflectable “fingers” 45a to 45n. In more detail, each of the ground conductors 43a to 43n may function as a ground path to a PCB, such as PCB 3. In an embodiment, when assembled each of the fingers 45a to 45n may be electrically and galvanically connected to a respective contact portion of a ground conductor 43a to 43n (i.e., tip or top portion), thereby functioning to provide a second ground path that passes from such a contact point, through a respective finger 45a to 45n and then through the conductive, plated plastic 41 to a PCB. Also shown are high-speed terminals 42a to 42n and low-speed and power terminals 49a to 49n.
Other dual ground path configurations may also be utilized. For example, rather than provide fingers 45a to 45n that are insert molded into shield 41, the fingers may be a part of a plate, similar to plate 28 described previously. In each of the dual ground path embodiments, the dual ground path configurations may provide the features as set forth previously herein.
Referring to
Enlarged views of the exemplary wafer 40a are depicted in
Referring now to
In addition to alignment control, structure 46 may provide control of undesirable electrical interference (e.g., noise). For example, structure 46 may be configured as a ground reference plane structure surrounding differential high-speed terminals 42a to 42n and their tail edges 42a′ to 42n′, for example. Such a ground reference plane structure may be configured to electrically “mirror” (i.e., be configured similar to) an electrical ground plane structure formed on the surface of a mated PCB (e.g., PCB 3). In embodiment, it should be understood that the “mirrored”, conductive ground structures (e.g., structure 46 and surface of the PCB 3) and conductive surfaces need not be in direct galvanic contact with one another to electrically isolate the differential signals being conducted in the high-speed terminals 32a to 32n from the differential signals being conducted by terminals/conductors on the surface of the PCB, for example. In an embodiment, to provide such electrical isolation the structure 46 may be separated from the surface of the PCB by 0.25-0.50 mm to name just one non-limiting distance. Though not in direct galvanic contact, the two facing, mirrored structures/surfaces may function as an electrical capacitor; i.e. two conductive structures/surfaces separated by a dielectric (in this case, generally air).
In an embodiment, structure 46 may be an integral part of a bottom port wafer assembly.
In our earlier discussion the assembly 1 included a central housing 2j that encloses portions of both the top and bottom ports 8a, 8b. In an embodiment, an alternative housing may enclose a single port.
Referring now to
In an embodiment, housing 102, ports 88a, 88b, internal wafers and their respective terminals as well as additional components within the housing 102 may form a high-speed, shielded, multi-level, multi-port connector with temperature and alignment controls, among other features. In one embodiment, the connector 1b may comprise an input/output (I/O) connector, such as those that may be used for small form-factor pluggable applications or double density small form-factor pluggable applications (e.g., QSFP, SFP, QSFP-DD, SFP-DD, QSFP, CDFP applications). Accordingly, the assembly 100 that includes housing 102 may be referred to as high-speed, shielded multi-port, multi-level connector assembly with temperature and alignment controls, among other features.
The conductive terminals that are a part of wafers within the connector 1b may be configured to conduct electrical signals. Additionally, in an alternative embodiment, the terminals may also be configured to feed electrical signals to E/O conversion circuitry or receive electrical signals from O/E conversion circuitry, for example In the latter case, such O/E or E/O conversion circuitry may be included and connected to respective conductive wafers where a cage is mated to the active electronic circuitry, for example
In many instances, the signals being conducted through the conductive wafers, the O/E, E/O conversion circuitry, active devices and retiming circuitry may generate a substantial amount of heat during operation. Thus, as described herein, the inventors provide inventive solutions to control such temperatures.
Housing 102 may be configured with one or more notches 101a to 101n on both sides to make contact with the bottom port 88b. Alternatively, pillars or trusses may also be used (see
Referring now to
In a further embodiment, the top port 88a may be separately connected to the PCB 3 using an SMT technique, for example. Such an exemplary top port assembly is depicted in
In
Referring now to
Though the terminals of the ground conductors, high speed conductors, low-speed conductors and power conductors are illustrated as down-facing, it should be understood that assembly may also comprise lead frame structures that comprise up-facing terminals that may be supported by similar lead-frames and may be covered by a similar ground shield. That is to say, a top port assembly may comprise a plurality of lead frame structures.
In embodiments of the invention, the signal and field affinity between terminals of each lead-frame structures of assembly 115a to 115n and its respective ground shield may be sufficient to limit deleterious lead-frame to lead-frame coupling and crosstalk, for example, as explained previously herein.
Referring now to
As described herein, the inventors have discovered inventive connector assemblies and related methods that include multiple alignment controls, both to a mated device (e.g., high-speed, active plug modules) as well as internal conductor and ground wafer alignment. Further, the temperature controls included in the inventive connector assemblies allow such connectors to control the temperatures generated by electronic circuitry within connected plug-in modules (up to 20+ watts, for example) enabling the effective transport of communications (data) signals at least up to 100 Gbps.
It should be understood that while certain inventive features and functions have been described with respect to one inventive embodiment or illustrative figure, this is merely exemplary. That is to say, some features and functions may be applicable and incorporated into many embodiments other than the embodiment or figure specifically described.
The claim language included below is incorporated herein by reference in expanded form, that is, hierarchically from broadest to narrowest, with each possible combination indicated by the multiple dependent claim references described as a unique standalone embodiment.
While benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments of the present invention. However, the benefits, advantages, solutions to problems, and any element(s) that may cause or result in such benefits, advantages, or solutions, or cause such benefits, advantages, or solutions to become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims.
This application claims priority to U.S. Provisional Application 63/010,061, filed Apr. 15, 2020 and to U.S. Provisional Application 63/116,648, filed Nov. 20, 2020, both of which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63010061 | Apr 2020 | US | |
| 63116648 | Nov 2020 | US |
