The present invention claims priority under 35 U.S.C. 119(a-d) to CN 201310522075.1, filed Oct. 31, 2013.
1. Field of Invention
The present invention relates to a technical field of digital IC (integrated circuit), and more particularly to a shift frequency demultiplier.
2. Description of Related Arts
Generally, there are two kinds of frequency demultiplier: shift frequency demultiplier and counting frequency demultiplier.
Compared with the shift frequency demultiplier, control logic of the phase of the counting frequency demultiplier is more complex. Therefore, the counting frequency demultiplier is usually utilized in the frequency demultiplier for clock with medium or low frequency. The shift frequency demultiplier requires simple logic for satisfying sequence requirement in high frequency designs. Therefore, the shift frequency demultiplier is usually utilized in the frequency demultiplier for clock with high frequency. However, a disadvantage of the shift frequency demultiplier is that: clock quality after frequency demultiplication depends on an initial state of the register set and state transformation during operation. In case that unforeseen reasons lead to state error, the frequency demultiplication problems or even total error will be caused.
Referring to
Referring to
Therefore, for solving the above problems, an improved shift frequency demultiplier should be provided.
An object of the present invention is to provide a shift frequency demultiplier which has a simple structure in such a manner that less registers and logic devices are needed to fulfill a same requirement of frequency demultiplier, and is able to regain normal frequency demultiplier ability after being disturbed.
Accordingly, in order to accomplish the above objects, the present invention provides a shift frequency demultiplier, which is a fractional-N shift frequency demultiplier, wherein the N is a positive integer larger than or equal to 4; the shift frequency demultiplier comprises:
an inverter;
N-2 registers; and
N-4 OR gates;
wherein each reset terminal of the register is connected to a system reset signal terminal; each clock terminal of the register is connected to an external high frequency clock terminal; an output terminal of the No. N-2 register is connected to an input terminal of the inverter, an output terminal of the inverter is respectively connected to an input terminal of the No. 1 register and input terminals of the OR gates; the OR gates are respectively connected between input terminals and output terminals of the No. 1 register to the No. N-3 register, and the output terminal of the No. 1 register is connected to another input terminal of the No. 1 OR gate, the output terminal of the No. N-4 register is connected to another input terminal of the No. N-4 OR gate; an output terminal of the No. 1 OR gate is connected to the input terminal of the No. 2 register, an output terminal of the No. N-4 OR gate is connected to the input terminal of the No. N-3 register; the output terminal of the No. N-3 register is connected to an input terminal of the No. N-2 register.
Preferable, the N equals to 4; the shift frequency demultiplier comprises:
an inverter;
a first register; and
a second register;
wherein an output terminal of the first register is connected to an input terminal of the second register; an output terminal of the second register is connected to an input terminal of the inverter; an output terminal of the inverter is connected to an input terminal of the first register.
Compared with the conventional technology, the shift frequency demultiplier according to the present invention comprises N-4 the OR gate in such a manner that only N-2 the registers are needed for fractional-N frequency demultiplication. A structure of the shift frequency demultiplier is simplified and is convenient to be realized. Furthermore, the inverter of the shift frequency demultiplier according to the present invention inverts an output result of the No. N-2 register in each clock cycle and inputs the output result into the No. 1 register as well as the OR gates, in such a manner that when an intermediate state of the shift frequency demultiplier is wrong, the shift frequency demultiplier will be recovered within a certain period with a same demultiplication ratio. With the foregoing structure, a scope of application of the shift frequency demultiplier is widened and external distribution on the demultiplication is decreased.
These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.
Referring to the drawings, same element numbers refer to same elements. As mentioned above, a shift frequency demultiplier which has a simple structure is provided, in such a manner that less registers and logic devices are needed with a same requirement of frequency demultiplier, and the shift frequency demultiplier is able to regain normal frequency demultiplier ability after being disturbed.
Referring to
an inverter IN;
N-2 registers (wherein the No. 1 register is marked as RE1, the No. 2 register is marked as RE2, . . . , and the No. N-2 register is marked as REN-2); and
N-4 OR gates (wherein the No. 1 OR gate is marked as OR1, the No. 2 OR gate is marked as OR2, . . . , and the No. N-4 OR gate is marked as ORN-4);
wherein N, which is a positive integer larger than or equal to 4, is a frequency demultiplier ratio of the shift frequency demultiplier; D is an input terminal of the register, Q is an output terminal of the register, which are the same as in the following drawings; each reset terminal Sn of the register is connected to a system reset signal terminal; the system reset signal terminal sends a system reset signal RSTn to the reset terminal Sn of each of the registers for wholly resetting the registers at an initial state, in such a manner that all the registers are set to 1 or 0, wherein according to the present invention, all the registers are set to 1 by the system reset signal RSTn; each clock terminal CK of the registers is connected to an external high frequency clock terminal; the output terminal of the external high frequency clock terminal sends a high frequency clock CLK3 to the clock terminals CK of the registers for operating the registers; an output terminal of the No. N-2 register REN2 is connected to an input terminal of the inverter IN, an output terminal of the inverter IN is respectively connected to an input terminal of the No. 1 register RE1 and input terminals of the OR gates for inverting an output result of the No. N-2 register REN-2 and inputting the output result into the No. 1 register RE1 as well as the OR gates; the OR gates are respectively connected between input terminals and output terminals of the No. 1 register to the No. N-3 register, and the output terminal of the No. 1 register RE1 is connected to another input terminal of the No. 1 OR gate OR1, the output terminal QN-4 of the No. N-4 register REN-4 is connected to another input terminal of the No. N-4 OR gate ORN-4; an output terminal of the No. 1 OR gate OR1 is connected to the input terminal D2 of the No. 2 register RE2, an output terminal of the No. N-4 OR gate ORN-4 is connected to the input terminal of the No. N-3 register REN-3; the output terminal of the No. N-3 register REN-3 is connected to an input terminal of the No. N-2 register REN-2.
When the shift register works, an initial state of each of the registers is set to 1. The registers shift in turn. And each output result of the registers is reversed and OR-calculated before being inputted into the next register. That is to say, the output result of the No. 1 register RE1 and the output result of the No. N-2 register REN-2 are reversed and are inputted into the No. 2 register RE2 after passing through the No. 1 OR gate OR1; the output result of the No. 2 register RE2 and the output result of the No. N-2 register REN-2 are reversed and are inputted into the No. 3 register RE3 after passing through the No. 2 OR gate OR2; and so forth. By this way, after N clock pulses, the No. N-2 register REN-2 can always completely reset the other registers to the initial state. Thereafter, a cycle of the N states is provided again in such a manner that when an intermediate state of the shift frequency demultiplier is wrong, the shift frequency demultiplier will be recovered within a period for ensuring that the shift frequency demultiplier works normally.
Specifically, referring to
an inverter IN;
four registers: RE1, RE2, RE3 and RE4; and
two OR gates: OR1 and OR2.
Connection relationship thereof is as shown in the
Referring to
an inverter IN′;
a first register RE1′; and
a second register RE2′.
Connection relationship thereof is as shown in the
One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.
It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.
Number | Date | Country | Kind |
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201310522075.1 | Oct 2013 | CN | national |