Patent Grant
8744038
1. Field of the Invention
The present invention relates to a shift register circuit. Further, the present invention relates to a display device in which a shift register circuit is formed over the same substrate as a pixel portion. Furthermore, the present invention relates to an electronic device including the display device.
2. Description of the Related Art
Display devices such as liquid crystal televisions are required to be manufactured at lower cost so as to be more widely used, so that development thereof have been conducted. In particular, a technique in which a driver circuit such as a scan line driver circuit is formed using a thin film transistor (TFT) over the same substrate as a pixel portion has been actively developed.
As an example of a driver circuit that can be formed over the same substrate as a pixel portion, there is a driver circuit having a configuration in which transistors having the same conductivity type (one conductivity type) are used in combination (for example, see Patent Document 1).
In a driver circuit including transistors having one conductivity type, a doping step or the like in a manufacturing process of the transistors can be skipped unlike in the case of a driver circuit in which transistors having different conductivity types are used in combination; therefore, manufacturing cost can be made lower.
When a driver circuit in which transistors having different conductivity types are used in combination is formed, the layout of a p-channel transistor and that of an n-channel transistor need to be different because the mobility of the p-channel transistor and that of the n-channel transistor are different. As a result, there is a problem in that the layout area is increased. By forming a driver circuit including transistors having one conductivity type and thus having the same mobility, the layout area can be reduced.
On the other hand, when a driver circuit including transistors having the same conductivity type is formed, there is a problem in that both a depletion transistor (also referred to as normally-on transistor) and an enhancement transistor (also referred to as normally-off transistor) are provided due to a shift in threshold voltage of the transistors. Since the normally-on transistor is provided, through current in the circuit is increased; thus, power consumption is increased. Therefore, a structure by which a shift in threshold voltage of the transistors is prevented needs to be provided.
In order to control the threshold voltage, a back gate electrode (second gate electrode) is provided in addition to a gate electrode (first gate electrode) in a transistor, and the potential of the back gate electrode is made to switch between two values; accordingly, the transistor can be made to switch between a normally-on state and a normally-off state. However, in the case where a signal is input to the gate electrode while the potential of the back gate electrode is made to switch between two values, both the potential of the gate electrode and that of the back gate electrode are made to switch between two values, and thus power consumption is increased.
In view of this, an object of one embodiment of the present invention is to provide a shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate electrode without changing the potential of a gate electrode.
According to one embodiment of the present invention, in a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode of the second transistor are formed from the same layer.
One embodiment of the present invention is a shift register circuit including a logic circuit including a first transistor and a second transistor which have the same conductivity type. A first gate electrode of the first transistor is electrically connected to a source electrode or a drain electrode of the first transistor. A second gate electrode of the first transistor is electrically connected to a wiring to which an input signal is supplied. A gate electrode of the second transistor is electrically connected to a wiring to which a clock signal is supplied. The first gate electrode and the gate electrode of the second transistor are formed from the same layer.
Another embodiment of the present invention is a shift register circuit including a logic circuit including a first transistor and a second transistor which have the same conductivity type. The first transistor includes a first gate electrode; a first semiconductor film over the first gate electrode; and a second gate electrode over the first semiconductor film. The first gate electrode is electrically connected to a source electrode or a drain electrode of the first transistor. The second gate electrode of the first transistor is electrically connected to a wiring to which an input signal is supplied. The second transistor includes a gate electrode; and a second semiconductor film over the gate electrode. The gate electrode of the second transistor is electrically connected to a wiring to which a clock signal is supplied. The first gate electrode and the gate electrode of the second transistor are formed from the same layer.
Another embodiment of the present invention is a shift register circuit including a logic circuit including a first transistor and a second transistor which have the same conductivity type. The first transistor includes a first gate electrode; a gate insulating film over the first gate electrode; a first semiconductor film over the gate insulating film; a source electrode and a drain electrode over the first semiconductor film; an interlayer insulating film over the source electrode and the drain electrode; and a second gate electrode over the interlayer insulating film. The first gate electrode is electrically connected to the source electrode or the drain electrode. The second gate electrode of the first transistor is electrically connected to a wiring to which an input signal is supplied. The second transistor includes a gate electrode; the gate insulating film over the gate electrode; and a second semiconductor film over the gate insulating film. The gate electrode of the second transistor is electrically connected to a wiring to which a clock signal is supplied. The first gate electrode and the gate electrode of the second transistor are formed from the same layer.
In the above embodiment, the thickness of the gate insulating film is preferably smaller than that of the interlayer insulating film in the shift register circuit.
In the above embodiment, the first semiconductor film and the second semiconductor film are preferably formed from the same layer in the shift register circuit.
In the above embodiment, the first transistor and the second transistor are preferably n-channel transistors in the shift register circuit.
According to one embodiment of the present invention, a shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate electrode without changing the potential of a gate electrode can be provided.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Note that the present invention can be carried out in many different modes, and it is easily understood by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. Note that in the structures of the present invention described below, reference numerals denoting the same portions are used in common in different drawings.
Note that the size, the thickness of a layer, and a region in structures illustrated in the drawings and the like in the embodiments are exaggerated for simplicity in some cases. Therefore, the scale is not necessarily limited to that illustrated in the drawings.
Note that in this specification, terms such as “first”, “second”, “third”, and “N-th” (N is a natural number of 2 or larger) are used in order to avoid confusion between components and thus do not limit the components numerically.
First, a configuration of a logic circuit which is provided in a shift register circuit and includes a first transistor and a second transistor will be described.
A logic circuit 10 illustrated in
Although each of the first transistor 11 and the second transistor 12 is described in this embodiment as being an n-channel transistor, each of the first transistor 11 and the second transistor 12 may be a p-channel transistor.
In the first transistor 11 of
In the second transistor 12 of
Note that since the source electrode and the drain electrode of the transistor may be switched depending on the structure, the operating condition, or the like of the transistor, it is difficult to define which is a source electrode or a drain electrode in some cases. Therefore, one of the source electrode and the drain electrode may also be referred to as a first electrode and the other may also be referred to as a second electrode.
The wiring 16 is a wiring to which a high power supply potential VDD is supplied. The wiring 17 is a wiring to which a low power supply potential VSS is supplied. The wiring 13 is a wiring to which an input signal IN is supplied. The wiring 14 is a wiring to which a clock signal CLK is supplied. The wiring 15 is a wiring from which an output signal OUT is output.
The input signal IN supplied to the wiring 13 is, for example, a start pulse in the shift register circuit or a signal output from a circuit in the preceding stage. The clock signal CLK supplied to the wiring 14 is, for example, a signal having a predetermined duty ratio generated by a clock signal generating circuit or the like.
As described above, the logic circuit 10 has a configuration in which the first gate electrode and the source electrode of the first transistor 11 are connected to each other. Therefore, the voltage applied between the gate and the source (gate-source voltage Vgs) is 0.
In the case where the first transistor 11 is made to switch between a normally-on state and a normally-off state, this switching can be controlled by adjusting the potential of the second gate electrode. That is, the first transistor 11 can be made to switch to a normally-on state by positively shifting the potential of the second gate electrode, and can be made to switch to a normally-off state by negatively shifting the potential of the second gate electrode. Since the first transistor 11 can be made to switch between a normally-on state and a normally-off state by adjusting the potential of the second gate electrode, the amount of the drain current Id at a Vgs of 0 V can be adjusted.
Therefore, with an input signal corresponding to the potential of the second gate electrode, current flowing to the first transistor 11 can be controlled without changing the potential of the first gate electrode from the outside. Accordingly, with the configuration of this embodiment, the potential of the first gate electrode is not changed, which leads to a reduction in power consumption.
In
As described above, in this embodiment, in the case where the first transistor 11 is made to switch between a normally-on state and a normally-off state, this switching is controlled by adjusting the potential of the second gate electrode. If a structure is employed in which the first transistor 11 is made to switch between a normally-on state and a normally-off state by adjusting the potential of the first gate electrode 32 in
In this embodiment, in the case where the first transistor 11 is made to switch between a normally-on state and a normally-off state, this switching is controlled by adjusting the potential of the second gate electrode 37 illustrated in
In this manner, the first transistor 11 can be made to switch between a normally-on state and a normally-off state without making the potential of the second gate electrode high. Accordingly, with the configuration of this embodiment, the potential of the second gate electrode is not made high, which leads to a reduction in power consumption.
As described above, according to one embodiment of the present invention, a signal corresponding to an input signal can be output by changing only the potential of the second gate electrode without changing the potential of the first gate electrode while the threshold voltage of the transistor is controlled. Accordingly, power consumption at the time of making the first transistor 11 switch between a normally-on state and a normally-off state can be reduced.
Next, the operation of the logic circuit in
In
The first transistor 11 and the second transistor 12 preferably have different current supply capabilities. Specifically, it is preferable that the current supply capability of the second transistor 12 be superior to that of the first transistor 11. By making the current supply capability of the first transistor 11 and that of the second transistor 12 different from each other, the output signal OUT can be surely made at L level when both the first transistor 11 and the second transistor 12 are on.
In order that the current supply capability of the first transistor 11 and that of the second transistor 12 are different from each other, the L/W ratio of the first transistor 11 may be larger than that of the second transistor 12.
First, the case where the input signal IN is at H level and the clock signal CLK is at L level is described with reference to
Since the first transistor 11 is on and the second transistor 12 is off, the output signal OUT becomes a signal corresponding to the high power supply potential VDD and thus is at H level.
The case where the input signal IN is at L level and the clock signal CLK is at H level is described with reference to
Since the first transistor 11 is off and the second transistor 12 is on, the output signal OUT becomes a signal corresponding to the low power supply potential VSS and thus is at L level.
The case where the input signal IN is at H level and the clock signal CLK is at H level is described with reference to
The output signal OUT depends on the current supply capabilities of the first transistor 11 and the second transistor 12; when the first transistor 11 and the second transistor 12 are on, the output signal OUT becomes a signal corresponding to the low power supply potential VSS and thus is at L level as described above.
The case where the input signal IN is at L level and the clock signal CLK is at L level is described with reference to
When the first transistor 11 and the second transistor 12 are off, a terminal outputting the output signal OUT is brought into an electrically floating state; thus, the output signal OUT keeps the potential in the preceding period (this state is denoted by “Z” in
As described above, according to one embodiment of the present invention, a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal IN by changing only the potential of a second gate electrode without changing the potential of a first gate electrode can be provided. Accordingly, power consumption at the time of making the transistor switch between a normally-on state and a normally-off state can be reduced.
Next, a configuration of a shift register circuit formed using plural stages of pulse output circuits each including a logic circuit with a first transistor and a second transistor, one example of which is illustrated in
In a shift register circuit 100 in
Note that the shift register circuit 100 in
Note that the shift register circuit 100 in
In the case where the shift register circuit in
For a semiconductor film of each of the transistors in the shift register circuit 100, a semiconductor film containing a semiconductor belonging to Group 14 of the periodic table (e.g., silicon) can be used, for example. In that case, the semiconductor film may be a single crystal semiconductor film, a polycrystalline semiconductor film, a microcrystalline semiconductor film, or an amorphous semiconductor film. Further, for the semiconductor film of the transistor, an oxide semiconductor may be used.
Next, a configuration of the pulse output circuit 103 will be described with reference to
In
The connection relation in each of the first logic circuit 111, the second logic circuit 112, and the fourth logic circuit 114 in
Specifically, a first gate electrode of the first transistor 121 is connected to a source electrode of the first transistor 121. A second gate electrode of the first transistor 121 is connected to the wiring to which the input signal IN is supplied. A drain electrode of the first transistor 121 is connected to a wiring to which a high power supply potential VDD is supplied. A gate electrode of the second transistor 122 is connected to the wiring to which the clock signal CLK is supplied. A drain electrode of the second transistor 122 is connected to the source electrode of the first transistor 121 and a first terminal of the first switch 115. A source electrode of the second transistor 122 is connected to a wiring to which a low power supply potential VSS is supplied.
A first gate electrode of the third transistor 123 is connected to a source electrode of the third transistor 123. A second gate electrode of the third transistor 123 is connected to a second terminal of the first switch 115. A drain electrode of the third transistor 123 is connected to the wiring to which the high power supply potential VDD is supplied. A gate electrode of the fourth transistor 124 is connected to the wiring to which the inverted clock signal CLKB is supplied. A drain electrode of the fourth transistor 124 is connected to the source electrode of the third transistor 123, a first terminal of the second switch 116, and a gate electrode of the sixth transistor 126. A source electrode of the fourth transistor 124 is connected to the wiring to which the low power supply potential VSS is supplied.
A first gate electrode of the fifth transistor 125 is connected to a source electrode of the fifth transistor 125. A second gate electrode of the fifth transistor 125 is connected to a drain electrode of the fifth transistor 125 and the wiring to which the high power supply potential VDD is supplied. A drain electrode of the sixth transistor 126 is connected to the source electrode of the fifth transistor 125 and a first terminal of the third switch 117. A source electrode of the sixth transistor 126 is connected to the wiring to which the low power supply potential VSS is supplied.
A first gate electrode of the seventh transistor 127 is connected to a source electrode of the seventh transistor 127. A second gate electrode of the seventh transistor 127 is connected to a second terminal of the second switch 116. A drain electrode of the seventh transistor 127 is connected to the wiring to which the high power supply potential VDD is supplied. A gate electrode of the eighth transistor 128 is connected to a second terminal of the third switch 117. A drain electrode of the eighth transistor 128 is connected to the source electrode of the seventh transistor 127 and a wiring to which the output signal OUT1 is supplied. A source electrode of the eighth transistor 128 is connected to the wiring to which the low power supply potential VSS is supplied.
A description is given of the case where transistors functioning as the first switch 115, the second switch 116, and the third switch 117 in
The on/off state of the first switch 115 is controlled by the potential of the wiring to which the inverted clock signal CLKB is supplied. The on/off state of the second switch 116 is controlled by the potential of the wiring to which the clock signal CLK is supplied. The on/off state of the third switch 117 is controlled by the potential of the wiring to which the clock signal CLK is supplied.
In
Next, the operation of the shift register circuit including the pulse output circuit in
As for the marks denoting the nodes in
As shown in the timing chart of
The shift register circuit described in this embodiment includes the logic circuit capable of controlling the threshold voltage of the transistor and outputting a signal corresponding to the input signal N by changing only the potential of the second gate electrode without changing the potential of the first gate electrode. Accordingly, power consumption at the time of making the transistor switch between a normally-on state and a normally-off state can be reduced.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
In this embodiment, a top view and a cross-sectional view of the shift register circuit described in the above embodiment will be described; particularly, a top view and a cross-sectional view of the first transistor and the second transistor included in the logic circuit will be described. Note that a display device including a shift register circuit in this embodiment can be applied to a liquid crystal display device and a display device including a light-emitting element such as an organic EL element. The shift register circuit described in the above embodiment can be employed as a driver circuit of an electronic paper including an electrophoresis element. Note that the shift register circuit described in the above embodiment can be applied to not only a driver circuit of a display device but also other devices such as a driver circuit for a photosensor.
First, a base film 902 is formed over a substrate 901. Next, a conductive film is formed over the base film 902, and then gate electrode layers 903A and 903B are formed by a photolithography process.
As the substrate 901, a glass substrate, a ceramic substrate, a plastic substrate with heat resistance, or the like can be used.
The base film 902 has a function of preventing diffusion of an impurity element from the substrate 901, and can be formed with a single-layer structure or a layered structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.
The conductive film for forming the gate electrode layers 903A and 903B can be formed with a single-layer structure or a layered structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or nickel, or an alloy material which contains any of these materials as a main component.
Then, a gate insulating film 904 is formed over the gate electrode layers 903A and 903B.
The gate insulating film 904 can be formed with a single-layer structure or a layered structure using a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer by a plasma CVD method, a sputtering method, or the like.
Note that here, silicon oxynitride contains more oxygen than nitrogen. In the case where measurements are performed using Rutherford backscattering spectrometry (RBS) and hydrogen forward scattering spectrometry (HFS), silicon oxynitride preferably contains oxygen, nitrogen, silicon, and hydrogen at 50 at. % to 70 at. %, 0.5 at. % to 15 at. %, 25 at. % to 35 at. %, and 0.1 at. % to 10 at. %, respectively. Further, silicon nitride oxide contains more nitrogen than oxygen. In the case where measurements are performed using RBS and HFS, silicon nitride oxide preferably contains oxygen, nitrogen, silicon, and hydrogen at 5 at. % to 30 at. %, 20 at. % to 55 at. %, 25 at. % to 35 at. %, and 10 at. % to 30 at. %, respectively. Note that percentages of nitrogen, oxygen, silicon, and hydrogen fall within the ranges given above, where the total number of atoms contained in the silicon oxynitride or the silicon nitride oxide is defined as 100 at. %.
Next, the gate insulating film 904 is selectively etched by a photolithography process, so that a contact hole reaching the gate electrode layer 903B is formed.
Then, a semiconductor film is formed over the gate insulating film 904. As a semiconductor that can be applied to the semiconductor film, a semiconductor containing an element belonging to Group 14 of the periodic table (e.g., silicon) can be used. For example, the semiconductor film containing silicon may be a single crystal semiconductor film, a polycrystalline semiconductor film, a microcrystalline semiconductor film, or an amorphous semiconductor film. Note that in the cross-sectional view of
As a semiconductor that can be applied to the semiconductor film, an oxide semiconductor such as a metal oxide may also be used; examples of the metal oxide include an In-based oxide (e.g., indium oxide), a Sn-based oxide (e.g., tin oxide), and a Zn-based oxide (e.g., zinc oxide).
Next, an impurity semiconductor film is formed over the semiconductor film. The impurity semiconductor film is formed using amorphous silicon to which phosphorus is added or the like. Note that when a p-channel transistor is used as the transistor, the impurity semiconductor film is formed using amorphous silicon to which boron is added or the like. In the case where the semiconductor film and electrode layers 906 form an ohmic contact, the impurity semiconductor film is not necessarily formed.
Then, by a photolithography process, the semiconductor film and the impurity semiconductor film are processed into an island-shaped semiconductor film 905A, an island-shaped semiconductor film 905B, and island-shaped impurity semiconductor films 907.
Then, a conductive film is formed over the gate insulating film 904, the semiconductor films 905A and 905B, and the impurity semiconductor films 907. After that, a resist mask is formed by a photolithography process, and then selective etching is performed. In this manner, the electrode layers 906 are formed. The conductive film can be formed with a single-layer structure or a layered structure using any of aluminum, copper, titanium, neodymium, scandium, molybdenum, chromium, tantalum, tungsten, and the like.
Next, an insulating layer 908 is formed over the gate insulating film 904, the semiconductor films 905A and 905B, and the electrode layers 906. The insulating layer 908 has a thickness of at least 1 nm, and can be formed in a manner similar to that of the gate insulating film 904. Alternatively, the insulating layer 908 can be formed using an organic resin layer. For the organic resin layer, for example, an acrylic-based resin, an epoxy-based resin, a polyimide-based resin, a polyamide-based resin, a polyvinylphenol-based resin, a benzocyclobutene-based resin, or the like can be used. Alternatively, a siloxane polymer can be used.
Then, a conductive film is formed over the insulating layer 908. After that, a resist mask is formed by a photolithography process, and then selective etching is performed. In this manner, a back gate electrode layer 909 is formed. The conductive film for forming the back gate electrode layer 909 can be formed in a manner similar to that of the conductive film for forming the electrode layers 906. Further, the back gate electrode layer 909 can be formed using indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like.
Through the above process, the first transistor 11 and the second transistor 12 can be manufactured.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
In this embodiment, an example of providing, over the same substrate, a transistor to be disposed in a pixel portion, and part of a signal line driver circuit and/or a scan line driver circuit including a shift register circuit will be described below.
In
The timing control circuit 5305 supplies, for example, a first scan line driver circuit start signal (GSP1) and a scan line driver circuit clock signal (GCLK1) to the first scan line driver circuit 5302. In addition, the timing control circuit 5305 supplies, for example, a second scan line driver circuit start signal (GSP2) (also referred to as start pulse) and a scan line driver circuit clock signal (GCLK2) to the second scan line driver circuit 5303. The timing control circuit 5305 supplies a signal line driver circuit start signal (SSP), a signal line driver circuit clock signal (SCLK), video signal data (DATA) (also simply referred to as video signal), and a latch signal (LAT) to the signal line driver circuit 5304. Each clock signal may be a plurality of clock signals with shifted phases or may be supplied together with a signal (CLKB) obtained by inverting the clock signal. Note that one of the first scan line driver circuit 5302 and the second scan line driver circuit 5303 can be omitted.
In the display device described in this embodiment, the signal line driver circuit and/or the scan line driver circuit including the shift register circuit described in the above embodiment are/is provided. Therefore, the display device described in this embodiment can control the threshold voltage of the transistor and output a signal corresponding to an input signal by changing only the potential of the back gate electrode without changing the potential of the gate electrode.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
In this embodiment, a description is given of a structure of a light-emitting element included in each pixel in the case where the display device described in the above embodiment is applied to a display device including a light-emitting element such as an organic EL element.
The first electrode 511 or the second electrode 514 is formed using a metal, an alloy, or an electrically conductive compound.
For example, the first electrode 511 or the second electrode 514 can be formed using a metal, an alloy, an electrically conductive compound, or the like that has a high work function (a work function of 4.0 eV or more). Specifically, it is possible to use a layer of a light-transmitting conductive metal oxide such as indium oxide-tin oxide (indium tin oxide), indium oxide-tin oxide containing silicon or silicon oxide, indium oxide-zinc oxide (indium zinc oxide), or indium oxide containing tungsten oxide and zinc oxide.
In addition, the first electrode 511 or the second electrode 514 can be formed using a metal, an alloy, an electrically conductive compound, or the like that has a low work function (typically, a work function of 3.8 eV or less). Specifically, any of the following materials can be used, for example: elements that belong to Group 1 or Group 2 of the periodic table (i.e., alkali metals such as lithium and cesium, alkaline-earth metals such as calcium and strontium, and magnesium) and alloys thereof (an alloy of aluminum, magnesium, and silver and an alloy of aluminum and lithium); and rare earth metals (europium and ytterbium) and alloys thereof.
A film of an alkali metal, an alkaline-earth metal, or an alloy thereof is formed by vacuum evaporation, sputtering, or the like. Further, silver paste or the like can be applied by an ink-jet method and baked to form the first electrode 511 or the second electrode 514. The first electrode 511 and the second electrode 514 are not limited to a single-layer structure and can have a layered structure.
In order to extract light emitted from the EL layer 513 to the outside, one of or both the first electrode 511 and the second electrode 514 is/are formed so as to transmit light emitted from the EL layer 513. When only the first electrode 511 has light-transmitting properties, light passes through the first electrode 511 in the direction shown by an arrow 500 and is extracted from the substrate 503 side with a luminance corresponding to a video signal input from a signal line. When only the second electrode 514 has light-transmitting properties, light passes through the second electrode 514 and is extracted from a sealing substrate 516 side with a luminance corresponding to a video signal input from the signal line. When both the first electrode 511 and the second electrode 514 have light-transmitting properties, light passes through the first electrode 511 and the second electrode 514 and is extracted from both the substrate 503 side and the sealing substrate 516 side with a luminance corresponding to a video signal input from the signal line.
For example, the light-transmitting electrode is formed using a light-transmitting conductive metal oxide or formed to a thickness of several nanometers to several tens of nanometers by using silver, aluminum, or the like. Alternatively, the light-transmitting electrode can have a layered structure including a thin layer of metal such as silver or aluminum and a conductive metal oxide layer with light-transmitting properties.
One of the first electrode 511 and the second electrode 514 that serves as the anode is preferably formed using a metal, an alloy, an electrically conductive compound, or the like that has a high work function (a work function of 4.0 eV or more). The other of the first electrode 511 and the second electrode 514 that serves as the cathode is preferably formed using a metal, an alloy, a conductive compound, or the like that has a low work function (a work function of 3.8 eV or less). Typically, the electrode serving as the cathode can be formed using an alkali metal, an alkaline-earth metal, an alloy or a compound containing such a metal, or transition metal (including a rare earth metal in its category).
The EL layer 513 includes the light-emitting layer. The EL layer 513 may include a hole-injection layer, a hole-transport layer, an electron-transport layer, and an electron-injection layer in addition to the light-emitting layer. The hole-transport layer is provided between the anode and the light-emitting layer. The hole-injection layer is provided between the anode and the light-emitting layer or between the anode and the hole-transport layer. The electron-transport layer is provided between the cathode and the light-emitting layer. The electron-injection layer is provided between the cathode and the light-emitting layer or between the cathode and the electron-transport layer. Note that all the hole-injection layer, the hole-transport layer, the electron-transport layer, and the electron-injection layer are not necessarily provided, and a layer to be provided is selected as appropriate depending on a desired function or the like.
The light-emitting layer contains a light-emitting substance. Examples of a light-emitting substance are a fluorescent compound, which exhibits fluorescence, and a phosphorescent compound, which exhibits phosphorescence.
The light-emitting layer, the hole-injection layer, the hole-transport layer, the electron-transport layer, and the electron-injection layer can be formed by evaporation, coating, or the like.
A passivation layer 515 may be formed over the second electrode 514 and the partition 502 by sputtering or CVD. By providing the passivation layer 515, deterioration of the light-emitting element due to entry of moisture and oxygen into the light-emitting element from the outside can be reduced. A space between the passivation layer 515 and the sealing substrate 516 may be filled with nitrogen, and further, a drying agent may be placed. Alternatively, a space between the passivation layer 515 and the sealing substrate 516 may be filled with a light-transmitting organic resin with high water absorbability.
In the case where the light-emitting element emits white light, full-color display can be performed when the substrate 503 or the sealing substrate 516 is provided with a color filter, a color conversion layer, or the like.
In the display device including a light-emitting element such as an organic EL element in this embodiment, the signal line driver circuit and/or the scan line driver circuit including the shift register circuit described in the above embodiment are/is provided. Therefore, the display device including a light-emitting element such as an organic EL element in this embodiment can control the threshold voltage of the transistor and output a signal corresponding to an input signal by changing only the potential of the back gate electrode without changing the potential of the gate electrode.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
In this embodiment, examples of an electronic device in which the display device in any of the above embodiments is included in a display portion will be described.
The content (or part of the content) described in each drawing in the above embodiments can be applied to a variety of electronic devices, specifically to a display portion of an electronic device. Examples of such electronic devices include television sets (also referred to as televisions or television receivers), monitors of computers or the like, cameras such as digital cameras or digital video cameras, digital photo frames, mobile phone sets (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio reproducing devices, large-sized game machines such as pachinko machines, and the like.
A display portion 1702 and a display portion 1703 are incorporated in the housing 1700 and the housing 1701, respectively. The display portion 1702 and the display portion 1703 may be configured to display one image or different images. In the case where the display portions 1702 and 1703 display different images, the display portion on the right side (the display portion 1702 in
Note that the digital photo frame in
The television set illustrated in
The display portion 1732 of the mobile phone in
Any of the electronic devices described in this embodiment is an electronic device having a display device including the shift register circuit described in the above embodiment. Therefore, the electronic device described in this embodiment can control the threshold voltage of a transistor and output a signal corresponding to an input signal IN by changing only the potential of a back gate electrode without changing the potential of a gate electrode.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
This application is based on Japanese Patent Application serial no. 2011-212048 filed with Japan Patent Office on Sep. 28, 2011, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-212048 | Sep 2011 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4615102 | Suzuki et al. | Oct 1986 | A |
| 5338959 | Kim et al. | Aug 1994 | A |
| 5731856 | Kim et al. | Mar 1998 | A |
| 5744823 | Harkin et al. | Apr 1998 | A |
| 5744864 | Cillessen et al. | Apr 1998 | A |
| 5847410 | Nakajima | Dec 1998 | A |
| 6215840 | Malaviya et al. | Apr 2001 | B1 |
| 6294274 | Kawazoe et al. | Sep 2001 | B1 |
| 6462723 | Yamazaki et al. | Oct 2002 | B1 |
| 6563174 | Kawasaki et al. | May 2003 | B2 |
| 6586346 | Yamazaki et al. | Jul 2003 | B1 |
| 6603453 | Yamazaki et al. | Aug 2003 | B2 |
| 6727522 | Kawasaki et al. | Apr 2004 | B1 |
| 6788567 | Fujimori | Sep 2004 | B2 |
| 6960787 | Yamazaki et al. | Nov 2005 | B2 |
| 6960812 | Yamazaki et al. | Nov 2005 | B2 |
| 7049190 | Takeda et al. | May 2006 | B2 |
| 7061014 | Hosono et al. | Jun 2006 | B2 |
| 7064346 | Kawasaki et al. | Jun 2006 | B2 |
| 7067843 | Carcia et al. | Jun 2006 | B2 |
| 7105868 | Nause et al. | Sep 2006 | B2 |
| 7145174 | Chiang et al. | Dec 2006 | B2 |
| 7202863 | Kimura et al. | Apr 2007 | B2 |
| 7211825 | Shih et al | May 2007 | B2 |
| 7247882 | Yamazaki et al. | Jul 2007 | B2 |
| 7262463 | Hoffman | Aug 2007 | B2 |
| 7282782 | Hoffman et al. | Oct 2007 | B2 |
| 7297977 | Hoffman et al. | Nov 2007 | B2 |
| 7298084 | Baude et al. | Nov 2007 | B2 |
| 7298176 | Ngo et al. | Nov 2007 | B2 |
| 7301211 | Yamazaki et al. | Nov 2007 | B2 |
| 7323356 | Hosono et al. | Jan 2008 | B2 |
| 7385224 | Ishii et al. | Jun 2008 | B2 |
| 7402506 | Levy et al. | Jul 2008 | B2 |
| 7411209 | Endo et al. | Aug 2008 | B2 |
| 7453065 | Saito et al. | Nov 2008 | B2 |
| 7453087 | Iwasaki | Nov 2008 | B2 |
| 7462862 | Hoffman et al. | Dec 2008 | B2 |
| 7468304 | Kaji et al. | Dec 2008 | B2 |
| 7470607 | Carcia et al. | Dec 2008 | B2 |
| 7491987 | Genrikh et al. | Feb 2009 | B2 |
| 7501293 | Ito et al. | Mar 2009 | B2 |
| 7507618 | Dunbar | Mar 2009 | B2 |
| 7544967 | Kim et al. | Jun 2009 | B2 |
| 7566904 | Ishii | Jul 2009 | B2 |
| 7575966 | Lai et al. | Aug 2009 | B2 |
| 7576394 | Furuta et al. | Aug 2009 | B2 |
| 7601984 | Sano et al. | Oct 2009 | B2 |
| 7608531 | Isa et al. | Oct 2009 | B2 |
| 7622371 | Pan et al. | Nov 2009 | B2 |
| 7635889 | Isa et al. | Dec 2009 | B2 |
| 7645478 | Thelss et al. | Jan 2010 | B2 |
| 7663302 | Shin et al. | Feb 2010 | B2 |
| 7674650 | Akimoto et al. | Mar 2010 | B2 |
| 7687807 | Koo et al. | Mar 2010 | B2 |
| 7691666 | Levy et al. | Apr 2010 | B2 |
| 7732251 | Hoffman et al. | Jun 2010 | B2 |
| 7732819 | Akimoto et al. | Jun 2010 | B2 |
| 7733015 | Saito | Jun 2010 | B2 |
| 7767106 | Chang | Aug 2010 | B2 |
| 7772021 | Lee et al. | Aug 2010 | B2 |
| 7786985 | Kimura et al. | Aug 2010 | B2 |
| 7791072 | Kumomi et al. | Sep 2010 | B2 |
| 7791082 | Iwasaki | Sep 2010 | B2 |
| 7795613 | Ito et al. | Sep 2010 | B2 |
| 7829444 | Yabuta et al. | Nov 2010 | B2 |
| 7863611 | Abe et al. | Jan 2011 | B2 |
| 7867636 | Nakagawara et al. | Jan 2011 | B2 |
| 7868326 | Sano et al. | Jan 2011 | B2 |
| 7872259 | Den et al. | Jan 2011 | B2 |
| 7884360 | Takechi et al. | Feb 2011 | B2 |
| 7923722 | Ryu et al. | Apr 2011 | B2 |
| 7932521 | Akimoto et al. | Apr 2011 | B2 |
| 7935641 | Kim et al. | May 2011 | B2 |
| 7939822 | Maekawa et al. | May 2011 | B2 |
| 8044906 | Kimura et al. | Oct 2011 | B2 |
| 8059078 | Kimura et al. | Nov 2011 | B2 |
| 8067775 | Miyairi et al. | Nov 2011 | B2 |
| 8106400 | Miyairi et al. | Jan 2012 | B2 |
| 8243873 | Koyama et al. | Aug 2012 | B2 |
| 20010015657 | Ye | Aug 2001 | A1 |
| 20010030323 | Ikeda | Oct 2001 | A1 |
| 20010046027 | Tai et al. | Nov 2001 | A1 |
| 20020043662 | Yamazaki et al. | Apr 2002 | A1 |
| 20020044111 | Yamazaki et al. | Apr 2002 | A1 |
| 20020056838 | Ogawa | May 2002 | A1 |
| 20020132454 | Ohtsu et al. | Sep 2002 | A1 |
| 20030189401 | Kido et al. | Oct 2003 | A1 |
| 20030218222 | Wager, III et al. | Nov 2003 | A1 |
| 20040038446 | Takeda et al. | Feb 2004 | A1 |
| 20040051823 | Choi | Mar 2004 | A1 |
| 20040127038 | Carcia et al. | Jul 2004 | A1 |
| 20040184027 | Mizutani et al. | Sep 2004 | A1 |
| 20050017302 | Hoffman | Jan 2005 | A1 |
| 20050162579 | Jeong et al. | Jul 2005 | A1 |
| 20050199959 | Chiang et al. | Sep 2005 | A1 |
| 20050199960 | Hoffman et al. | Sep 2005 | A1 |
| 20050275038 | Shih et al. | Dec 2005 | A1 |
| 20060035452 | Carcia et al. | Feb 2006 | A1 |
| 20060043377 | Hoffman et al. | Mar 2006 | A1 |
| 20060091793 | Baude et al. | May 2006 | A1 |
| 20060108529 | Saito et al. | May 2006 | A1 |
| 20060108636 | Sano et al. | May 2006 | A1 |
| 20060110867 | Yabuta et al. | May 2006 | A1 |
| 20060113536 | Kumomi et al. | Jun 2006 | A1 |
| 20060113539 | Sano et al. | Jun 2006 | A1 |
| 20060113549 | Den et al. | Jun 2006 | A1 |
| 20060113565 | Abe et al. | Jun 2006 | A1 |
| 20060169973 | Isa et al. | Aug 2006 | A1 |
| 20060170111 | Isa et al. | Aug 2006 | A1 |
| 20060197092 | Hoffman et al. | Sep 2006 | A1 |
| 20060208977 | Kimura | Sep 2006 | A1 |
| 20060228974 | Thelss et al. | Oct 2006 | A1 |
| 20060231882 | Kim et al. | Oct 2006 | A1 |
| 20060238135 | Kimura | Oct 2006 | A1 |
| 20060244107 | Sugihara et al. | Nov 2006 | A1 |
| 20060284171 | Levy et al. | Dec 2006 | A1 |
| 20060284172 | Ishii | Dec 2006 | A1 |
| 20060292726 | Akimoto et al. | Dec 2006 | A1 |
| 20060292777 | Dunbar | Dec 2006 | A1 |
| 20070024187 | Shin et al. | Feb 2007 | A1 |
| 20070046191 | Saito | Mar 2007 | A1 |
| 20070052025 | Yabuta | Mar 2007 | A1 |
| 20070054507 | Kaji et al. | Mar 2007 | A1 |
| 20070072439 | Akimoto et al. | Mar 2007 | A1 |
| 20070090365 | Hayashi et al. | Apr 2007 | A1 |
| 20070096816 | Paul et al. | May 2007 | A1 |
| 20070108446 | Akimoto | May 2007 | A1 |
| 20070152217 | Lai et al. | Jul 2007 | A1 |
| 20070172591 | Seo et al. | Jul 2007 | A1 |
| 20070187678 | Hirao et al. | Aug 2007 | A1 |
| 20070187760 | Furuta et al. | Aug 2007 | A1 |
| 20070194379 | Hosono et al. | Aug 2007 | A1 |
| 20070252928 | Ito et al. | Nov 2007 | A1 |
| 20070272922 | Kim et al. | Nov 2007 | A1 |
| 20070287296 | Chang | Dec 2007 | A1 |
| 20080006877 | Mardilovich et al. | Jan 2008 | A1 |
| 20080038882 | Takechi et al. | Feb 2008 | A1 |
| 20080038929 | Chang | Feb 2008 | A1 |
| 20080042217 | Jeong et al. | Feb 2008 | A1 |
| 20080050595 | Nakagawara et al. | Feb 2008 | A1 |
| 20080073653 | Iwasaki | Mar 2008 | A1 |
| 20080080221 | Koo et al. | Apr 2008 | A1 |
| 20080083950 | Pan et al. | Apr 2008 | A1 |
| 20080106191 | Kawase | May 2008 | A1 |
| 20080128689 | Lee et al. | Jun 2008 | A1 |
| 20080129195 | Ishizaki et al. | Jun 2008 | A1 |
| 20080166834 | Kim et al. | Jul 2008 | A1 |
| 20080182358 | Cowdery-Corvan et al. | Jul 2008 | A1 |
| 20080197350 | Park et al. | Aug 2008 | A1 |
| 20080203387 | Kang et al. | Aug 2008 | A1 |
| 20080224133 | Park et al. | Sep 2008 | A1 |
| 20080254569 | Hoffman et al. | Oct 2008 | A1 |
| 20080258139 | Ito et al. | Oct 2008 | A1 |
| 20080258140 | Lee et al. | Oct 2008 | A1 |
| 20080258141 | Park et al. | Oct 2008 | A1 |
| 20080258143 | Kim et al. | Oct 2008 | A1 |
| 20080296568 | Ryu et al. | Dec 2008 | A1 |
| 20080308796 | Akimoto et al. | Dec 2008 | A1 |
| 20080308797 | Akimoto et al. | Dec 2008 | A1 |
| 20080308804 | Akimoto et al. | Dec 2008 | A1 |
| 20080308805 | Akimoto et al. | Dec 2008 | A1 |
| 20080308806 | Akimoto et al. | Dec 2008 | A1 |
| 20090008639 | Akimoto et al. | Jan 2009 | A1 |
| 20090033818 | Nakajima et al. | Feb 2009 | A1 |
| 20090065771 | Iwasaki et al. | Mar 2009 | A1 |
| 20090068773 | Lai et al. | Mar 2009 | A1 |
| 20090073325 | Kuwabara et al. | Mar 2009 | A1 |
| 20090091678 | Jeong et al. | Apr 2009 | A1 |
| 20090114910 | Chang | May 2009 | A1 |
| 20090128476 | Lee et al. | May 2009 | A1 |
| 20090134399 | Sakakura et al. | May 2009 | A1 |
| 20090152506 | Umeda et al. | Jun 2009 | A1 |
| 20090152541 | Maekawa et al. | Jun 2009 | A1 |
| 20090278122 | Hosono et al. | Nov 2009 | A1 |
| 20090280600 | Hosono et al. | Nov 2009 | A1 |
| 20100025678 | Yamazaki et al. | Feb 2010 | A1 |
| 20100051937 | Kaji et al. | Mar 2010 | A1 |
| 20100065844 | Tokunaga | Mar 2010 | A1 |
| 20100084650 | Yamazaki et al. | Apr 2010 | A1 |
| 20100084651 | Yamazaki et al. | Apr 2010 | A1 |
| 20100085081 | Ofuji et al. | Apr 2010 | A1 |
| 20100092800 | Itagaki et al. | Apr 2010 | A1 |
| 20100102313 | Miyairi et al. | Apr 2010 | A1 |
| 20100102314 | Miyairi et al. | Apr 2010 | A1 |
| 20100109002 | Itagaki et al. | May 2010 | A1 |
| 20100117079 | Miyairi et al. | May 2010 | A1 |
| 20100252826 | Yamazaki et al. | Oct 2010 | A1 |
| 20100301326 | Miyairi et al. | Dec 2010 | A1 |
| 20110221475 | Koyama et al. | Sep 2011 | A1 |
| 20120032943 | Kimura et al. | Feb 2012 | A1 |
| 20120061668 | Miyairi et al. | Mar 2012 | A1 |
| 20120104386 | Miyairi et al. | May 2012 | A1 |
| Number | Date | Country |
|---|---|---|
| 1 737 044 | Dec 2006 | EP |
| 1 770 788 | Apr 2007 | EP |
| 2 226 847 | Sep 2010 | EP |
| 60-198861 | Oct 1985 | JP |
| 63-210022 | Aug 1988 | JP |
| 63-210023 | Aug 1988 | JP |
| 63-210024 | Aug 1988 | JP |
| 63-215519 | Sep 1988 | JP |
| 63-239117 | Oct 1988 | JP |
| 63-265818 | Nov 1988 | JP |
| 63-301565 | Dec 1988 | JP |
| 02-156676 | Jun 1990 | JP |
| 03-231472 | Oct 1991 | JP |
| 05-251705 | Sep 1993 | JP |
| 06-202156 | Jul 1994 | JP |
| 08-264794 | Oct 1996 | JP |
| 10-290012 | Oct 1998 | JP |
| 11-505377 | May 1999 | JP |
| 2000-044236 | Feb 2000 | JP |
| 2000-150900 | May 2000 | JP |
| 2001-051292 | Feb 2001 | JP |
| 2002-076356 | Mar 2002 | JP |
| 2002-289859 | Oct 2002 | JP |
| 2003-086000 | Mar 2003 | JP |
| 2003-086808 | Mar 2003 | JP |
| 2003-273228 | Sep 2003 | JP |
| 2003-280034 | Oct 2003 | JP |
| 2003-309266 | Oct 2003 | JP |
| 2004-103957 | Apr 2004 | JP |
| 2004-222256 | Aug 2004 | JP |
| 2004-273614 | Sep 2004 | JP |
| 2004-273732 | Sep 2004 | JP |
| 2005-051228 | Feb 2005 | JP |
| 2005-164802 | Jun 2005 | JP |
| 2006-203241 | Aug 2006 | JP |
| 2006-237624 | Sep 2006 | JP |
| 2007-096055 | Apr 2007 | JP |
| 2007-123861 | May 2007 | JP |
| 2007-150158 | Jun 2007 | JP |
| 2007-250983 | Sep 2007 | JP |
| 2007-529119 | Oct 2007 | JP |
| 2004114391 | Dec 2004 | WO |
| 2005093850 | Oct 2005 | WO |
| 2007119386 | Oct 2007 | WO |
| 2008105250 | Sep 2008 | WO |
| 2008143304 | Nov 2008 | WO |
| Entry |
|---|
| Yong-Soo Cho et al.; “Characteristics of a-Si:H Dual-Gate TFTS Using ITO Electrode for LCD Driver”; AM-FPD '08 Digest of Technical Papers; Jul. 2, 2008; pp. 229-232. |
| K. Takahashi et al.; “4p-N-10 Back-channel control in amorphous In-Ga-Zn-O TFTs”; 69TH Japan Society of Applied Physics; Sep. 1, 2008; p. 851; No. 2 (with English translation). |
| Asakuma, N. et al., “Crystallization and Reduction of Sol-Gel-Derived Zinc Oxide Films by Irradiation With Ultraviolet Lamp,” Journal of Sol-Gel Science and Technology, 2003, vol. 26, pp. 181-184. |
| Asaoka, Y et al., “29.1: Polarizer-Free Reflective LCD Combined With Ultra Low-Power Driving Technology,” SID Digest '09 : SID International Symposium Digest of Technical Papers, 2009, pp. 395-398. |
| Chern, H et al., “An Analytical Model for the Above-Threshold Characteristics of Polysilicon Thin-Film Transistors,” IEEE Transactions on Electron Devices, Jul. 1, 1995, vol. 42, No. 7, pp. 1240-1246. |
| Cho, D et al., “21.2: AL and SN-Doped Zinc Indium Oxide Thin Film Transistors for Amoled Back-Plane,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 280-283. |
| Clark, S et al., “First Principles Methods Using Castep,” Zeitschrift fur Kristallographie, 2005, vol. 220, pp. 567-570. |
| Coates. D et al., “Optical Studies of the Amorphous Liquid-Cholesteric Liquid Crystal Transition: The Blue Phase,” Physics Letters, Sep. 10, 1973, vol. 45A, No. 2, pp. 115-116. |
| Costello, M et al., “Electron Microscopy of a Cholesteric Liquid Crystal and Its Blue Phase,” Phys. Rev. A (Physical Review. A), May 1, 1984, vol. 29, No. 5, pp. 2957-2959. |
| Dembo, H et al., “RFCPUS on Glass and Plastic Substrates Fabricated by TFT Transfer Technology,” IEDM 05: Technical Digest of International Electron Devices Meeting, Dec. 5, 2005, pp. 1067-1069. |
| Fortunato, E et al., “Wide-Bandgap High-Mobility ZNO Thin-Film Transistors Produced at Room Temperature,” Appl. Phys. Lett. (Applied Physics Letters), Sep. 27, 2004, vol. 85, No. 13, pp. 2541-2543. |
| Fung, T et al., “2-D Numerical Simulation of High Performance Amorphous In-Ga-Zn-O TFTs for Flat Panel Displays,” AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 251-252, The Japan Society of Applied Physics. |
| Godo, H et al., “P-9: Numerical Analysis on Temperature Dependence of Characteristics of Amorphous In-Ga-Zn-Oxide TFT,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 1110-1112. |
| Godo, H et al., “Temperature Dependence of Characteristics and Electronic Structure for Amorphous In-Ga-Zn-Oxide TFT,” AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 41-44. |
| Hayashi, R et al., “42.1: Invited Paper: Improved Amorphous In-Ga-Zn-O TFTS,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 621-624. |
| Hirao, T et al., “Novel Top-Gate Zinc Oxide Thin-Film Transistors (ZNO TFTS) for AMLCDS,” Journal of the SID , 2007, vol. 15, No. 1, pp. 17-22. |
| Hosono, H et al., “Working hypothesis to explore novel wide band gap electrically conducting amorphous oxides and examples,” J. Non-Cryst. Solids (Journal of Non-Crystalline Solids), 1996, vol. 198-200, pp. 165-169. |
| Hosono, H, “68.3: Invited Paper:Transparent Amorphous Oxide Semiconductors for High Performance TFT,” SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1830-1833. |
| Hsieh, H et al., “P-29: Modeling of Amorphous Oxide Semiconductor Thin Film Transistors and Subgap Density of States,” SID Digest '08 : SID International Symposium Digest of Technical Papers, 2008, vol. 39, pp. 1277-1280. |
| Ikeda, T et al., “Full-Functional System Liquid Crystal Display Using CG-Silicon Technology,” SID Digest '04 : SID International Symposium Digest of Technical Papers, 2004, vol. 35, pp. 860-863. |
| Janotti, A et al., “Native Point Defects in ZnO,” Phys. Rev. B (Physical Review. B), 2007, vol. 76, No. 16, pp. 165202-1-165202-22. |
| Janotti, A et al., “Oxygen Vacancies in ZnO,” Appl. Phys. Lett. (Applied Physics Letters), 2005, vol. 87, pp. 122102-1-122102-3. |
| Jeong, J et al., “3.1: Distinguished Paper: 12.1-Inch WXGA Amoled Display Driven by Indium-Gallium-Zinc Oxide TFTs Array,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, No. 1, pp. 1-4. |
| Jin, D et al., “65.2: Distinguished Paper:World-Largest (6.5″) Flexible Full Color Top Emission Amoled Display on Plastic Film and its Bending Properties,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 983-985. |
| Kanno, H et al., “White Stacked Electrophosphorecent Organic Light-Emitting Devices Employing MOO3 as a Charge-Generation Layer,” Adv. Mater. (Advanced Materials), 2006, vol. 18, No. 3, pp. 339-342. |
| Kikuchi, H et al., “39.1: Invited Paper: Optically Isotropic Nano-Structured Liquid Crystal Composites for Display Applications,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 578-581. |
| Kikuchi, H et al., “62.2: Invited Paper: Fast Electro-Optical Switching in Polymer-Stabilized Liquid Crystalline Blue Phases for Display Application,” SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1737-1740. |
| Kikuchi, H et al., “Polymer-Stabilized Liquid Crystal Blue Phases,” Nature Materials, Sep. 1, 2002, vol. 1, pp. 64-68. |
| Kim, S et al., “High-Performance oxide thin film transistors passivated by various gas plasmas,” The Electrochemical Society, 214TH ECS Meeting, 2008, No. 2317, 1 page. |
| Kimizuka, N et al., “Spinel,YBFE2O4, and YB2FE3O7 Types of Structures for Compounds in the IN2O3 and SC2O3-A2O3-BO Systems [A; FE, GA, or AL; B: MG, MN, FE, NI, CU,or ZN] At Temperatures Over 1000°C,” Journal of Solid State Chemistry, 1985, vol. 60, pp. 382-384. |
| Kimizuka, N. et al., “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3-ZnGa2O4-ZnO System,” Journal of Solid State Chemistry, Apr. 1, 1995, vol. 116, No. 1, pp. 170-178. |
| Kitzerow, H et al., “Observation of Blue Phases in Chiral Networks,” Liquid Crystals, 1993, vol. 14, No. 3, pp. 911-916. |
| Kurokawa, Y et al., “UHF RFCPUS on Flexible and Glass Substrates for Secure RFID Systems,” Journal of Solid-State Circuits , 2008, vol. 43, No. 1, pp. 292-299. |
| Lany, S et al., “Dopability, Intrinsic Conductivity, and Nonstoichiometry of Transparent Conducting Oxides,” Phys. Rev. Lett. (Physical Review Letters), Jan. 26, 2007, vol. 98, pp. 045501-1-045501-4. |
| Lee, H et al., “Current Status of, Challenges to, and Perspective View of AM-OLED,” IDW '06 : Proceedings of the 13th International Display Workshops, Dec. 7, 2006, pp. 663-666. |
| Lee, J et al., “World's Largest (15-Inch) XGA AMLCD Panel Using IGZO Oxide TFT,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 625-628. |
| Lee, M et al., “15.4: Excellent Performance of Indium-Oxide-Based Thin-Film Transistors by DC Sputtering,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 191-193. |
| Li, C et al “Modulated Structures of Homologous Compounds InMO3(ZnO)m (M=In,Ga; m=Integer) Described by Four-Dimensional Superspace Group,” Journal of Solid State Chemistry, 1998, vol. 139, pp. 347-355. |
| Masuda, S et al., “Transparent thin film transistors using ZnO as an active channel layer and their electrical properties,” J. Appl. Phys. (Journal of Applied Physics), Feb. 1, 2003, vol. 93, No. 3, pp. 1624-1630. |
| Meiboom, S et al., “Theory of the Blue Phase of Cholesteric Liquid Crystals,” Phys. Rev. Lett. (Physical Review Letters), May 4, 1981, vol. 46, No. 18, pp. 1216-1219. |
| Miyasaka, M, “Suftla Flexible Microelectronics on Their Way to Business,” SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1673-1676. |
| Mo, Y et al., “Amorphous Oxide TFT Backplanes for Large Size AMOLED Displays,” IDW '08 : Proceedings of the 6th International Display Workshops, Dec. 3, 2008, pp. 581-584. |
| Nakamura, “Synthesis of Homologous Compound with New Long-Period Structure,”NIRIM Newsletter, March. 1995, vol. 150, pp. 1-4 with English translation. |
| Nakamura, M et al., “The phase relations in the In2O3-Ga2ZnO4-ZnO system at 1350° C,” Journal of Solid State Chemistry, Aug. 1, 1991, vol. 93, No. 2, pp. 298-315. |
| Nomura, K et al., “Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor,” Science, May 23, 2003, vol. 300, No. 5623, pp. 1269-1272. |
| Nomura, K et al., “Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors,” Jpn. J. Appl. Phys. (Japanese Journal of Applied Physics) , 2006, vol. 45, No. 5B, pp. 4303-4308. |
| Nomura, K et al.,“Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors,”Nature, Nov. 25, 2004, vol. 432, pp. 488-492. |
| Nomura, K et al., “Carrier transport in transparent oxide semiconductor with intrinsic structural randomness probed using single-cyrstalline InGaO3(ZnO)5 films,” Appl. Phys. Lett. (Applied Physics Letters) , Sep. 13, 2004, vol. 85, No. 11, pp. 1993-1995. |
| Nowatari, H et al., “60.2: Intermediate Connector with Suppressed Voltage Loss for White Tandem OLEDS,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, vol. 40, pp. 899-902. |
| Oba, F et al., “Defect energetics in ZnO: A hybrid Hartree-Fock density functional study,” Phys. Rev. B (Physical Review. B), 2008, vol. 77, pp. 245202-1-245202-6. |
| Oh, M et al., “Improving the Gate Stability of ZNO Thin-Film Transistors with Aluminum Oxide Dielectric Layers,” J. Electrochem. Soc. (Journal of the Electrochemical Society), 2008, vol. 155, No. 12, pp. H1009-H1014. |
| Ohara, H et al., “21.3: 4.0 IN. QVGA Amoled Display Using In-Ga-Zn-Oxide TFTS With a Novel Passivation Layer,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 284-287. |
| Ohara, H et al., “Amorphous In-Ga-Zn-Oxide TFTs with Suppressed Variation for 4.0 inch QVGA Amoled Display,” AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 227-230, The Japan Society of Applied Physics. |
| Orita, M et al., “Amorphous transparent conductive oxide InGaO3(ZnO)m (m<4):a Zn4s conductor,” Philosophical Magazine, 2001, vol. 81, No. 5, pp. 501-515. |
| Orita, M et al., “Mechanism of Electrical Conductivity of Transparent InGaZnO4,” Phys. Rev. B (Physical Review. B), Jan. 15, 2000, vol. 61, No. 3, pp. 1811-1816. |
| Osada, T et al., “15.2: Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 184-187. |
| Osada, T et al., “Development of Driver-Integrated Panel Using Amorphous In-Ga-Zn-Oxide TFT,” AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 33-36. |
| Park, J et al., “Dry etching of ZnO films and plasma-induced damage to optical properties,” J. Vac. Sci. Technol. B (Journal of Vacuum Science & Technology B), Mar. 1, 2003, vol. 21, No. 2, pp. 800-803. |
| Park, J et al., “Improvements in the Device Characteristics of Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors by Ar Plasma Treatment,” Appl. Phys. Lett. (Applied Physics Letters), Jun. 26, 2007, vol. 90, No. 26, pp. 262106-1-262106-3. |
| Park, J et al., “Electronic Transport Properties of Amorphous Indium-Gallium-Zinc Oxide Semiconductor Upon Exposure to Water,” Appl. Phys. Lett. (Applied Physics Letters), 2008, vol. 92, pp. 072104-1-072104-3. |
| Park, J et al., “High performance amorphous oxide thin film transistors with self-aligned top-gate structure,” IEDM 09: Technical Digest of International Electron Devices Meeting, Dec. 7, 2009, pp. 191-194. |
| Park, Sang-Hee et al., “42.3: Transparent ZnO Thin Film Transistor for the Application of High Aperture Ratio Bottom Emission AM-OLED Display,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 629-632. |
| Park, J et al., “Amorphous Indium-Gallium-Zinc Oxide TFTS and Their Application for Large Size Amoled,” AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 275-278. |
| Park, S et al., “Challenge to Future Displays: Transparent AM-OLED Driven by Peald Grown ZNO TFT,” IMID '07 Digest, 2007, pp. 1249-1252. |
| Prins, M et al., “A Ferroelectric Transparent Thin-Film Transistor,” Appl. Phys. Lett. (Applied Physics Letters), Jun. 17, 1996, vol. 68, No. 25, pp. 3650-3652. |
| Sakata, J et al., “Development of 4.0-IN. Amoled Display With Driver Circuit Using Amorphous In-Ga-Zn-Oxide TFTS,” IDW '09 : Proceedings of the 16th International Display Workshops, 2009, pp. 689-692. |
| Son, K et al., “42.4L: Late-News Paper: 4 Inch QVGA Amoled Driven by the Threshold Voltage Controlled Amorphous GIZO (Ga2O3-In2O3-ZnO) TFT,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 633-636. |
| Takahashi, M et al., “Theoretical Analysis of IGZO Transparent Amorphous Oxide Semiconductor,” IDW '08 : Proceedings of the 15th International Display Workshops, Dec. 3, 2008, pp. 1637-1640. |
| Tsuda, K et al., “Ultra Low Power Consumption Technologies for Mobile TFT-LCDs,” IDW '02 : Proceedings of the 9th International Display Workshops, Dec. 4, 2002, pp. 295-298. |
| Ueno, K et al., “Field-Effect Transistor on SrTiO3 with Sputtered AI2O3 Gate Insulator,” Appl. Phys. Lett. (Applied Physics Letters), Sep. 1, 2003, vol. 83, No. 9, pp. 1755-1757 |
| Van De Walle, C, “Hydrogen as a Cause of Doping in Zinc Oxide,” Phys. Rev. Lett. (Physical Review Letters), Jul. 31, 2000, vol. 85, No. 5, pp. 1012-1015. |
| Number | Date | Country | |
|---|---|---|---|
| 20130077735 A1 | Mar 2013 | US |
