Patent Application
20250182698
The present disclosure relates to the field of display technologies, in particular to a shift register, a gate drive circuit and a display device.
The application of Active Matrix Organic Light Emitting Diode (AMOLED) panels is becoming increasingly widespread. A pixel display device of AMOLED is an Organic Light Emitting Diode (OLED for short). AMOLED can emit light by driving a thin film transistor to generate a driving current in a saturated state, which drives a light emitting device to emit light.
Embodiments of the disclosure provide a shift register, a gate drive circuit and a display device, the specific scheme of which is as follows.
A shift register is according to an embodiment of the present disclosure, including:
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the node control module includes a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; wherein
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the light emitting drive output module includes a fifth switching transistor, a sixth switching transistor, and a seventh switching transistor; wherein
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the light emitting cascade output module includes an eighth switching transistor, a first capacitor, a ninth switching transistor and a second capacitor; wherein
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the voltage regulating module includes:
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the first input sub-module includes a tenth switching transistor, a gate of the tenth switching transistor is electrically connected to the first clock signal terminal, a first pole of the tenth switching transistor is electrically connected to the preceding stage light emitting cascade signal output terminal, and a second pole of the tenth switching transistor is electrically connected to the second node;
In one possible implementation, in a shift register according to an embodiment of the present disclosure, all of the first to seventeenth switching transistors are P-type transistors.
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the node control module includes an eighteenth switching transistor, a nineteenth switching transistor, a twentieth switching transistor and a twenty-first switching transistor; wherein
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the light emitting drive output module includes a twenty-second switching transistor, a twenty-third switching transistor, a twenty-fourth switching transistor, a twenty-fifth switching transistor, and a twenty-sixth switching transistor; wherein
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the light emitting cascade output module includes a twenty-seventh switching transistor, a twenty-eighth switching transistor, a twenty-ninth switching transistor, a fourth capacitor, a thirtieth switching transistor, and a fifth capacitor; wherein
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the voltage regulating module includes:
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the first input sub-module includes a thirty-first switching transistor, a gate of the thirty-first switching transistor is electrically connected to the first clock signal terminal, a first pole of the thirty-first switching transistor is electrically connected to the preceding stage light emitting cascade signal output terminal, and a second pole of the thirty-first switching transistor is electrically connected to the fourth node;
In one possible implementation, in a shift register according to an embodiment of the present disclosure, a reset module is further included, the reset module is coupled to a reset signal terminal, the first power terminal and the fourth node, and the reset module is configured to provide the first voltage of the first power terminal to the fourth node in response to control of a signal of the reset signal terminal.
In one possible implementation, in a shift register according to an embodiment of the present disclosure, the reset module includes a forty-second switching transistor, a gate of the forty-second switching transistor electrically connected to the reset signal terminal, a first pole of the forty-second switching transistor electrically connected to the first power supply terminal, and a second pole of the forty-second switching transistor electrically connected to the fourth node.
In one possible implementation, in a shift register according to an embodiment of the present disclosure, all of the eighteenth to forty-second switching transistors are N-type transistors.
Correspondingly, a gate drive circuit is also provided according to an embodiment of the present disclosure, including a plurality of cascaded first shift registers, wherein the first shift register is any shift register described above according to the embodiments of the present disclosure.
Correspondingly, a display device is also provided according to an embodiment of the present disclosure. The display device includes a display region and a peripheral region located around the display region, wherein the display region includes a plurality of pixel units arranged in an array, each row of pixel units is provided with a corresponding light emitting control signal line, and the light emitting control signal line is connected with a gate of a light emitting control transistor in a corresponding pixel unit, and the light emitting control transistor is a P-type transistor.
The peripheral region includes a first gate drive circuit, and the first gate drive circuit is a gate drive circuit according to the embodiments of the present disclosure.
In one possible implementation, in a display device according to an embodiment of the present disclosure, each row of pixel units is further provided with a corresponding first gate line connected to a gate of a data writing transistor in the pixel units, and a second gate line connected to a gate of a sensing transistor in the pixel units;
To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, technical solutions of the embodiments of the present disclosure will be clearly and completely described below in combination with the accompany drawings of the embodiments of the present disclosure. Apparently, described embodiments are a part of the embodiments of the present disclosure, but not all of the embodiments. The embodiments and features in the embodiments of the present disclosure may be randomly combined with each other in case of no conflicts. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skills in the art without inventive effort are covered by the protection scope of the present disclosure.
Unless otherwise defined, technical terms or scientific terms used in the present disclosure should have common meanings as understood by those of ordinary skill in the art that the present disclosure belongs to. “Include”, “contain”, or similar words in the present disclosure mean that elements or objects appearing before the words cover elements or objects listed after the words and their equivalents, but do not exclude other elements or objects. “Connect”, “join”, or a similar term is not limited to a physical or mechanical connection, but may include an electrical connection, whether direct or indirect. “Inner”, “outer”, “upper”, “lower”, etc., are used to represent relative position relations, and when an absolute position of a described object is changed, the relative position relation may also be correspondingly changed.
It should be noted that sizes and shapes of various figures in the drawings do not reflect actual scales, and are only for the purpose of schematically illustrating contents of the present disclosure. Moreover, same or similar elements and elements having same or similar functions are denoted by same or similar reference numerals throughout the descriptions.
Transistors used in all embodiments of the present disclosure may be thin film transistors or field effect tubes or other devices with same characteristics. In the embodiments of the present disclosure, a coupling mode of a drain with a source of each transistor is interchangeable. Therefore, in the embodiments of the present disclosure, there is no difference between the drain and the source of each transistor, in fact. To distinguish two poles of a transistor except a gate, one of the two poles is referred to as the drain and the other one of the two poles is referred to as the source. A thin film transistor used in the embodiments of the present disclosure may be an N-type transistor or a P-type transistor.
In the embodiments of the present disclosure, an “active level signal” refers to a signal that can control a transistor to turn on after being input to a gate of the transistor, and an “inactive level signal” refers to a signal that can control a transistor to turn off after being input to a gate of the transistor. For an N-type transistor, a high level signal is an active level signal and a low level signal is an inactive level signal. For a P-type transistor, a low level signal is an active level signal and a high level signal is an inactive level signal.
A single pixel unit needs to experience a writing display data stage and a light emitting stage during one frame. During the writing display data stage, the first gate line G1 controls the data writing transistor T1′ to turn on, and the data line DATA writes a data voltage Vdata to a gate of the driving transistor T3′. In the light emitting stage, the driving transistor T3′ outputs a corresponding driving current according to a voltage at the gate of the driving transistor T3′, so as to drive a light emitting element OLED to emit light.
In addition, a blank period (also referred to as Blank period) is generally provided between two adjacent frames, where one frame includes a display drive period and a blank period, and the blank period can generally be used for randomly performing external compensation sensing on a certain pixel unit row.
In the pixel unit shown in
To solve the above-mentioned technical problem, the pixel circuit structure in the pixel unit has been improved in the related technologies.
Referring to
It can be seen from the above contents that by providing the light emitting control transistor T4′, the light emitting element OLED can present the brightness corresponding to the lower gray scales, thereby effectively solving a problem that the pixel unit cannot present the brightness corresponding to the low gray scales with insufficient IC precision. However, in practical applications, it is found that since all shift registers in an existing gate drive circuit for providing the black insertion drive signal (commonly referred to as the light emitting control gate drive circuit) are cascaded sequentially, the existing gate drive circuit for providing the black insertion drive signal continuously and sequentially outputs the black insertion drive signal to various light emitting control signal lines. At that time, it is inevitably that light emitting control signal lines corresponding to some rows of pixel units receives the black insertion drive signal during the blank period. As can be seen from the timing shown in
In order to effectively solve the problem that the random external compensation sensing in the blank period cannot be supported in the related technologies, a shift register is according to an embodiment of the present disclosure, and the inventive principle of the present disclosure will be described in detail in combination with specific embodiments below. It should be noted that, in order to distinguish from shift registers in other gate drive circuits on a display device, a shift register located in the light emitting control gate drive circuit in the present disclosure is referred to as a first shift register, and the first shift register can be used to provide a light emitting control signal (including light emitting drive signals and black insertion drive signals) to a corresponding light emitting control signal line.
The voltage regulating module 10 is connected with a preceding stage light emitting cascade signal output terminal CR<N−1>, a first clock signal terminal CKA, a second clock signal terminal CKB, a first power supply terminal VGH, a second power supply terminal VGL, a first node P1 and a second node P2. The voltage regulating module 10 is configured to adjust voltages at the first node P1 and the second node P2 in response to control of signals provided by the preceding stage light emitting cascade signal output terminal CR<N−1>, the first clock signal terminal CKA, the second clock signal terminal CKB, the first power supply terminal VGH and the second power supply terminal VGL.
The light emitting cascade output module 20 is connected with the first power supply terminal VGH, the second power supply terminal VGL, a light emitting cascade signal output terminal CR<N>, the first node P1, and the second node P2, and the light emitting cascade output module 20 is configured to supply a first voltage of the first power supply terminal VGH or a second voltage of the second power supply terminal VGL to the light emitting cascade signal output terminal CR<N> in response to control of the voltage at the first node P1 and in response to control of the voltage at the second node P2.
The node control module 30 is connected with the first node P1, a subsequent stage gate cascade signal output GCR<N+1>, the second power supply terminal VGL, a third node P3, and the second clock signal terminal CKB, and is configured to adjust a voltage at a third node P3 in response to control of signals provided by the subsequent stage gate cascade signal output terminal GCR<N+1>, the first node P1, and the second clock signal terminal CKB.
As shown in
Alternatively, as shown in
In an embodiment of the present disclosure, the light emitting cascade signal output terminal CR and the light emitting control drive signal output terminal EM<N> of the first shift register are disposed respectively, wherein the light emitting cascade output module 20 is used to control an output of an light emitting cascade signal output terminal CR, and the light emitting drive output module 40 controls an output of the light emitting control drive signal output terminal EM<N>. In other words, the light emitting cascade signal and the light emitting control signal output by the first shift register can be controlled separately. Based on this, in the embodiment of the present disclosure, the light emitting control signals outputted by the first shift registers can be independently controlled in a condition that normal cascaded first shift registers in the light emitting control gate drive circuit are ensured.
When a row of pixel unit needs to perform external compensation sensing and the row of pixel unit receives a black insertion drive signal (i.e. inactive level signal) in a blank period if a conventional light emitting control gate drive circuit is used for driving, in the embodiment of the present disclosure, a light emitting control drive signal output terminal EM<N> of a first shift register corresponding to the row of pixel units which needs to perform the external compensation sensing can be controlled to forcibly output the light emitting drive signal (i.e. active level signal) through the subsequent stage gate cascade signal output terminal GCR<N+1> connected to the first shift register corresponding to the row of pixel units which performs the external compensation sensing, so that the light emitting control signal received by the row of pixel units which needs to perform the external compensation sensing in the blank period is the light emitting drive signal. In other words, the row of pixel units that originally received the black insertion drive signal in the blank period and needed to perform the external compensation sensing in the blank period actually receives the light emitting drive signal in the blank period, thus ensuring the external compensation sensing process of the row of pixel units.
Hereinafter, technical solutions in the embodiments of the present disclosure will be described in detail in combination with specific examples. As shown in
As shown in
A gate of the first switching transistor T1 is electrically connected with the subsequent stage gate cascade signal output terminal GCR<N+1>, a first pole of the first switching transistor T1 is electrically connected with a first node P1, and a second pole of the first switching transistor T1 is electrically connected with a third node P3.
A gate of the second switching transistor T2 is electrically connected with the second clock signal terminal CKB, a first pole of the second switching transistor T2 is electrically connected with the second power supply terminal VGL, and a second pole of the second switching transistor T2 is electrically connected with a gate of the third switching transistor T3.
A first pole of the third switching transistor T3 is electrically connected with the first power supply terminal VGH, and a second pole of the third switching transistor T3 is electrically connected with the third node P3.
A gate of the fourth switching transistor T4 is electrically connected with the subsequent stage gate cascade signal output terminal GCR<N+1>, a first pole of the fourth switching transistor T4 is electrically connected with the first power supply terminal VGH, and a second pole of the fourth switching transistor T4 is electrically connected with the second pole of the second switching transistor T2.
It should be noted that the node control module 30 in the embodiment of the present disclosure is not limited to the case shown in
In some embodiments, in the above-mentioned first shift register according to the embodiments of the present disclosure, as shown in
A gate of the fifth switching transistor T5 is electrically connected with the third node P3, a first pole of the fifth switching transistor T5 is electrically connected with the first power supply terminal VGH, and a second pole of the fifth switching transistor T5 is electrically connected with the light emitting control drive signal output terminal EM<N>.
A gate of the sixth switching transistor T6 is electrically connected to the second node P2, a first pole of the sixth switching transistor T6 is electrically connected with the second power supply terminal VGL, and a second pole of the sixth switching transistor T6 is electrically connected with the light emitting control drive signal output terminal EM<N>.
A gate of the seventh switching transistor T7 is electrically connected with the second pole of the second switching transistor T2, a first pole of the seventh switching transistor T7 is electrically connected with the second power supply terminal VGL, and a second pole of the seventh switching transistor T7 is electrically connected with the light emitting control drive signal output terminal EM<N>.
In some embodiments, in the above-mentioned first shift register according to the embodiments of the present disclosure, as shown in
A gate of the eighth switching transistor T8 is electrically connected with the first node P1, a first pole of the eighth switching transistor T8 is electrically connected with the first power supply terminal VGH, and a second pole of the eighth switching transistor T8 is electrically connected with the light emitting cascade signal output terminal CR<N>.
A first terminal of the first capacitor C1 is electrically connected between the first power supply terminal VGH and the first pole of the eighth switching transistor T8, and a second terminal of the first capacitor C1 is electrically connected with the gate of the eighth switching transistor T8.
A gate of the ninth switching transistor T9 is electrically connected with the second node P2, a first pole of the ninth switching transistor T9 is electrically connected with the second power supply terminal VGL, and a second pole of the ninth switching transistor T9 is electrically connected with the light emitting cascade signal output terminal CR<N>.
A first terminal of the second capacitor C2 is electrically connected with the second clock signal terminal CKB, and a second terminal of the second capacitor C2 is electrically connected with the second node P2. The first capacitor C1 and the second capacitor C2 are configured to improve the voltage stability at the first node P1 and the second node P2.
In some embodiments, in the above-mentioned first shift register according to embodiments of the present disclosure, as shown in
The first input sub-module 101 is connected with the preceding stage light emitting cascade signal output terminal CR<N−1>, the first clock signal terminal CKA and the second node P2, and the first input sub-module 101 is configured to provide a signal of the preceding stage light emitting cascade signal output terminal CR<N−1> to the second node P2 in response to control of a signal of the first clock signal terminal CKA. Optionally, the first input sub-module 101 may include a tenth switching transistor T10, a gate of the tenth switching transistor T10 is electrically connected with the first clock signal terminal CKA, a first pole of the tenth switching transistor T10 is electrically connected with the preceding stage light emitting cascade signal output terminal CR<N−1>, and a second pole of the tenth switching transistor T10 is electrically connected with the second node P2.
The second input sub-module 102 is connected with the first clock signal terminal CKA, the second power supply terminal VGL, the second node P2 and the fourth node P4, and the second input sub-module 102 is configured to supply the second voltage of the second power supply terminal VGL to the fourth node P4 in response to the control of the signal of the first clock signal terminal CKA, and to provide the signal of the first clock signal terminal CKA to the fourth node P4 in response to control of the voltage at the second node P2. Optionally, the second input sub-module 102 includes an eleventh switching transistor T11 and a twelfth switching transistor T12. A gate of the eleventh switching transistor T11 is electrically connected to the first clock signal terminal CKA, a first pole of the eleventh switching transistor T11 is electrically connected with the second power supply terminal VGL, and a second pole of the eleventh switching transistor T11 is electrically connected with the fourth node P4. A gate of the twelfth switching transistor T12 is electrically connected with the second node P2, a first pole of the twelfth switching transistor T12 is electrically connected to the first clock signal terminal CKA, and a second pole of the twelfth switching transistor T12 is electrically connected with the fourth node P4.
The first voltage control sub-module 103 is connected with the first node P1, the second node P2, the fourth node P4, the second clock signal terminal CKB and the first power supply terminal VGH, and the first voltage control sub-module 103 is configured to provide a signal of the second clock signal terminal CKB to the first node P1 in response to control of the voltage at the fourth node P4 and the signal of the second clock signal terminal CKB, and to provide the first voltage of the first power supply terminal VGH to the first node P1 in response to the control of the voltage at the second node P2. Optionally, the first voltage control sub-module 103 may include a thirteenth switching transistor T13, a fourteenth switching transistor T14, a fifteenth switching transistor T15 and a third capacitor C3. A gate of the thirteenth switching transistor T13 is electrically connected with the fourth node P4, a first pole of the thirteenth switching transistor T13 is electrically connected with the second clock signal terminal CKB, and a second pole of the thirteenth switching transistor T13 is electrically connected with a first pole of the fourteenth switching transistor T14. A gate of the fourteenth switching transistor T14 is electrically connected with the second clock signal terminal CKB, and a second pole of the fourteenth switching transistor T14 is electrically connected with the first node P1. A gate of the fifteenth switching transistor T15 is electrically connected with the second node P2, a first pole of the fifteenth switching transistor T15 is electrically connected with the first power supply terminal VGH, and a second pole of the fifteenth switching transistor T15 is electrically connected with the first node P1. A first terminal of the third capacitor C3 is electrically connected with the fourth node P4, and a second terminal of the third capacitor C3 is electrically connected with the second pole of the thirteenth switching transistor T13. The third capacitor C3 is configured to improve the voltage stability at the fourth node P4.
The second voltage control sub-module 104 is connected with the second node P2, the fourth node P4, the second clock signal terminal CKB, and the first power supply terminal VGH, and the second voltage control sub-module 104 is configured to provide a first voltage of the first power supply terminal VGH to the second node P2 in response to the control of the voltage at the fourth node P4 and the signal of the second clock signal terminal CKB. Optionally, the second voltage control sub-module 104 may include a sixteenth switching transistor T16 and a seventeenth switching transistor T17. A gate of the sixteenth switching transistor T16 is electrically connected with the fourth node P4, a first pole of the sixteenth switching transistor T16 is electrically connected with the first power supply terminal VGH, and a second pole of the sixteenth switching transistor T16 is electrically connected with a first pole of the seventeenth switching transistor T17. A gate of the seventeenth switching transistor T17 is electrically connected with the second clock signal terminal CKB, and a second pole of the seventeenth switching transistor T17 is electrically connected with the second node P2.
In some embodiments, in order to unify the fabrication process, in the above-mentioned first shift register according to the embodiments of the present disclosure, as shown in
In the first stage T1, the preceding stage light emitting cascade signal output terminal CR<N−1> provides a high level signal, the subsequent stage gate cascade signal output terminal GCR<N+1> provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. Specifically, when the first clock signal terminal CKA provides a low level signal, the tenth switching transistor T10 and the eleventh switching transistor T11 are turned on. When the high level signal provided by the preceding stage light emitting cascade signal output terminal CR<N−1> is provided to the second node P2, the twelfth switching transistor T12 is turned off. When a low level voltage supplied by the second power supply terminal VGL is supplied to the fourth node P4, since a voltage at the second node P2 is a high level signal, all of the fifteenth switching transistor T15, the ninth switching transistor T9 and the sixth switching transistor T6 are turned off. Since a voltage at the fourth node P4 is a low level signal, the thirteenth switching transistor T13 is turned on, and the high level signal provided by the second clock signal terminal CKB is provided to a point N. Since the second clock signal terminal CKB provides a high level signal, both of the second switching transistor T2 and the fourteenth switching transistor T14 are turned off, the first node P1 remains a high level, then the eighth switching transistor T8 is turned off, and an point M remains a low level signal, both of the third switching transistor T3 and the seventh switching transistor T7 are turned on, a high level signal provided by the first power supply terminal VGH is provided to the third node P3. Since the subsequent stage gate cascade signal output terminal GCR<N+1> provides a high level signal, both of the first switching transistor T1 and the fourth switching transistor T4 are turned off. Since a voltage at the third node P3 is a high level signal, the fifth switching transistor T5 is turned off. Since the seventh switching transistor T7 is turned on, the low level signal provided by the second power supply terminal VGL is provided to the light emitting control drive signal output terminal EM<N>. Therefore, the light emitting control drive signal output terminal EM<N> of the first shift register according to the embodiments of the present disclosure outputs a low level signal in the first stage T1.
In the second stage T2, the preceding stage light emitting cascade signal output terminal CR<N−1> provides a high level signal, the subsequent stage gate cascade signal output terminal GCR<N+1> provides a high level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal. Specifically, the first clock signal terminal CKA provides a high level signal, then the tenth switching transistor T10 and the eleventh switching transistor T11 are turned off. The second clock signal terminal CKB provides a low level signal, then the fourth node P4 turns to a lower level through a bootstrap action of the third capacitor C3. The voltage at the second node P2 remains a high level signal, all of the twelfth switching transistor T12, the fifteenth switching transistor T15, the ninth switching transistor T9 and the sixth switching transistor T6 are turned off, and the thirteenth switching transistor T13 is turned on. The low level signal provided by the second clock signal terminal CKB is provided to the point N, the fourteenth switching transistor T14 is turned on, then the low level signal at the point N is provided to the first node P1, both of the point N and the first node P1 turns to a low potential, then the eighth switching transistor T8 is turned on, CR<N> outputs a high level signal. However, at that time, GCR<N+1> is at a high level, such that the point M turns to a low level signal, then both of the third switching transistor T3 and the seventh switching transistor T7 are turned on, wherein the third switching transistor T3 is turned on to pull up the voltage at the third node P3, and both of the first switching transistor T1 and the fifth switching transistor T5 are turned off; the seventh switching transistor T7 is turned on, then the low level signal provided by the second power supply terminal VGL is provided to the light emitting control drive signal output terminal EM<N>. Therefore, the light emitting control drive signal output terminal EM<N> of the first shift register according to the embodiments of the present disclosure outputs a low level signal in the second stage T2.
In the third stage T3, the preceding stage light emitting cascade signal output terminal CR<N−1> provides a high level signal, the subsequent stage gate cascade signal output terminal GCR<N+1> provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. When the voltage at the second node P2 remains at a high level due to the bootstrap action of the second capacitor C2, the twelfth switching transistor T12, the fifteenth switching transistor T15, the ninth switching transistor T9 and the sixth switching transistor T6 are all turned off, the voltage at the fourth node P4 remains at a low level due to the bootstrap action of the third capacitor C3, the point N and the first node P1 remain at a low level, the eighth switching transistor T8 is turned on, CR<N> outputs a high level signal, and the point M remains at a low level signal, the third switching transistor T3 and the seventh switching transistor T7 are turned on, the third switching transistor T3 is turned on to pull up the voltage at the third node P3, the first switching transistor T1 and the fifth switching transistor T5 are turned off, and the seventh switching transistor T7 is turned on, and the low level signal provided by the second power supply terminal VGL is provided to the light emitting control drive signal output terminal EM<N>. Therefore, the light emitting control drive signal output terminal EM<N> of the first shift register according to the embodiments of the present disclosure outputs a low level signal in the third stage T3.
In the fourth stage T4, the preceding stage light emitting cascade signal output terminal CR<N−1> provides a low level signal, the subsequent stage gate cascade signal output terminal GCR<N+1> provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. Since both of the first clock signal terminals CKA and CR<N−1> provide low level signals, the tenth switching transistor T10 is turned on. The second node P2 turns to a low level signal, all of the twelfth switching transistor T12, the fifteenth switching transistor T15, the ninth switching transistor T9 and the sixth switching transistor T6 are turned on. The fourth node P4 is at a low level, the thirteenth switching transistor T13 is turned on, and the point N turn to a high level. Since the fifteenth switching transistor T15 is turned on, the high level signal of the first power supply terminal VGH is provided to the first node P1, the first node P1 turns to a high level, and the eighth switching transistor T8 is turned off. Since the ninth switching transistor T9 is turned on, the low level signal of the second power supply terminal VGL is provided to the light emitting cascade signal output terminal CR<N>, the point M remains at a low level signal, then both of the third switching transistor T3 and the seventh switching transistor T7 are turned on. When the third switching transistor T3 is turned on and the third node P3 is pulled up, then both of the first switching transistor T1 and the fifth switching transistor T5 are turned off. The seventh switching transistor T7 is turned on, the low level signal provided by the second power supply terminal VGL is provided to the light emitting control drive signal output terminal EM<N>. Therefore, the light emitting control drive signal output terminal EM<N> of the first shift register according to the embodiments of the present disclosure outputs a low level signal in the fourth stage T4.
Therefore, the first shift register, as shown in
A gate of the eighteenth switching transistor T18 is electrically connected with the subsequent stage gate cascade signal output terminal GCR<N+1>, a first pole of the eighteenth switching transistor T18 is electrically connected with the second power supply terminal VGL, and a second pole of the eighteenth switching transistor T18 is electrically connected with a gate of the nineteenth switching transistor T19.
A first pole of the nineteenth switching transistor T19 is electrically connected with the first node P1, and a second pole of the nineteenth switching transistor T19 is electrically connected with the third node P3.
A gate of the twentieth switching transistor T20 is electrically connected with the subsequent stage gate cascade signal output terminal GCR<N+1>, a first pole of the twentieth switching transistor T20 is electrically connected with the second power supply terminal VGL, and a second pole of the twentieth switching transistor T20 is electrically connected with the third node P3.
Both of a gate and a first pole of the twenty-first switching transistor T21 are electrically connected with the second clock signal terminal CKB, and a second pole of the twenty-first switching transistor T21 is electrically connected with the second pole of the eighteenth switching transistor T18.
In some embodiments, in the above-mentioned first shift register according to the embodiments of the present disclosure, as shown in
A gate of the twenty-second switching transistor T22 is electrically connected with the third node P3, a first pole of the twenty-second switching transistor T22 is electrically connected with the second power supply terminal VGL, and a second pole of the twenty-second switching transistor T22 is electrically connected with a gate of the twenty-fifth switching transistor T25.
A gate of the twenty-third switching transistor T23 is electrically connected with the second node P2, a first pole of the twenty-third switching transistor T23 is electrically connected with the first power supply terminal VGH, and a second pole of the twenty-third switching transistor T23 is electrically connected to the gate of the twenty-fifth switching transistor T25.
A gate of the twenty-fourth switching transistor T24 is electrically connected with the subsequent stage gate cascade signal output terminal GCR<N+1>, a first pole of the twenty-fourth switching transistor T24 is electrically connected with the first power supply terminal VGH, and a second pole of the twenty-fourth switching transistor T24 is electrically connected with the gate of the twenty-fifth switching transistor T25.
A first pole of the twenty-fifth switching transistor T25 is electrically connected with the second power supply terminal VGL, and a second pole of the twenty-fifth switching transistor T25 is electrically connected with the light emitting control drive signal output terminal EM<N>.
Both of a gate and a first pole of the twenty-sixth switching transistor T26 is electrically connected with the first power supply terminal VGH, a second pole of the twenty-sixth switching transistor T26 is electrically connected with the light emitting control drive signal output terminal EM<N>.
In some embodiments, in the above-mentioned first shift register according to the embodiments of the present disclosure, as shown in
A gate of the twenty-seventh switching transistor T27 is electrically connected with the first node P1, a first pole of the twenty-seventh switching transistor T27 is electrically connected with the second power supply terminal VGL, and a second pole of the twenty-seventh switching transistor T27 is electrically connected with a first pole of the twenty-eighth switching transistor T28.
A gate of the twenty-eighth switching transistor T28 is electrically connected with the first node P1, and a second pole of the twenty-eighth switching transistor T28 is electrically connected with the light emitting cascade signal output terminal CR<N>.
A gate of the twenty-ninth switching transistor T29 is electrically connected with the light emitting cascade signal output terminal CR<N>, a first pole of the twenty-ninth switching transistor T29 is electrically connected with the first power supply terminal VGH, and a second pole of the twenty-ninth switching transistor T29 is electrically connected with the first pole of the twenty-eighth switching transistor T28.
A first terminal of the fourth capacitor C4 is connected with the first node P1, and a second terminal of the fourth capacitor C4 is connected with the second power supply terminal VGL.
A gate of the thirtieth switching transistor T30 is electrically connected with the second node P2, a first pole of the thirtieth switching transistor T30 is electrically connected with the first power supply terminal VGH, and a second pole of the thirtieth switching transistor T30 is electrically connected to the light emitting cascade signal output terminal CR<N>.
A first terminal of the fifth capacitor C5 is electrically connected with the second node P2, and a second terminal of the fifth capacitor C5 is electrically connected with the light emitting cascade signal output terminal CR<N>.
In some embodiments, in the above-mentioned first shift register according to embodiments of the present disclosure, as shown in
The first input sub-module 101 is connected with the preceding stage light emitting cascade signal output terminal CR<N−1>, the first clock signal terminal CKA and the fourth node P4, and the first input sub-module 101 is configured to provide a signal of the preceding stage light emitting cascade signal output terminal CR<N−1> to the fourth node P4 in response to control of a signal of the first clock signal terminal CKA. Optionally, the first input sub-module 101 may include a thirty-first switching transistor T31, a gate of the thirty-first switching transistor T31 is electrically connected with the first clock signal terminal CKA, a first pole of the thirty-first switching transistor T31 is electrically connected with the preceding stage light emitting cascade signal output terminal CR<N−1>, and a second pole of the thirty-first switching transistor T31 is electrically connected with the fourth node P4.
The second input sub-module 102 is connected with the first clock signal terminal CKA, the first power supply terminal VG, the fourth node P4 and the fifth node P5, and the second input sub-module 102 is configured to supply the first voltage of the first power supply terminal VGH to the fifth node P5 in response to the control of the signal of the first clock signal terminal CKA, and to provide the signal of the first clock signal terminal CKA to the fifth node P5 in response to control of the voltage at the fourth node P4. Optionally, the second input sub-module 102 may include a thirty-second switching transistor T32 and a thirty-third switching transistor T33. A gate of the thirty-second switching transistor T32 is electrically connected with the first clock signal terminal CKA, a first pole of the thirty-second switching transistor T32 is electrically connected with the first power supply terminal VGH, and a second pole of the thirty-second switching transistor T32 is electrically connected with the fifth node P5. A gate of the twelfth switching transistor T33 is electrically connected with the fourth node P4, a first pole of the thirty-third switching transistor T33 is electrically connected with the first clock signal terminal CKA, and a second pole of the thirty-third switching transistor T33 is electrically connected with the fifth node P5.
The first voltage control sub-module 103 is connected with the first node P1, the second node P2, the fourth node P4, the fifth node P5, the second clock signal terminal CKB, the first power supply terminal VGH and the second power supply terminal VGL. The first voltage control sub-module 103 is configured to provide the signal of the second clock signal terminal CKB to the first node P1 in response to the control of the voltage at the fifth node P5 and the signal of the second clock signal terminal CKB, and to provide the voltage at the fourth node P4 to the sixth node P6 in response to the control of the voltage at the fourth node P4 and the first power supply terminal VGH, to supply the voltage at the sixth node P6 to the second node P2 in response to the control of the first power supply terminal VGH, to supply the first voltage at the first power supply terminal VGH to the sixth node P6 in response to the control of the voltage at the second node P2, and to supply the second voltage at the second power supply terminal VGL to the first node P1 in response to the control of the voltage at the second node P2. Optionally, the first voltage control sub-module 103 may include a thirty-fourth switching transistor T34, a thirty-fifth switching transistor T35, a thirty-sixth switching transistor T36, a thirty-seventh switching transistor T37, a thirty-eighth switching transistor T38, a thirty-ninth switching transistor T39 and a sixth capacitor C6. A gate of the thirty-fourth switching transistor T34 is electrically connected with the fifth node P5, a first pole of the thirty-fourth switching transistor T34 is electrically connected with the second clock signal terminal CKB, and a second pole of the thirty-fourth switching transistor T34 is electrically connected with the seventh node P7. A gate of the thirty-fifth switching transistor T35 is electrically connected with the second clock signal terminal CKB, a first pole of the thirty-fifth switching transistor T35 is electrically connected with the seventh node P7, and a second pole of the thirty-fifth switching transistor T35 is electrically connected with the first node P1. A gate of the thirty-sixth switching transistor T36 is electrically connected to the second node P2, a first pole of the thirty-sixth switching transistor T36 is electrically connected with the second power supply terminal VGL, and a second pole of the thirty-sixth switching transistor T36 is electrically connected with the first node P1. A gate of the thirty-seventh switching transistor T37 is electrically connected with the second node P2, a first pole of the thirty-seventh switching transistor T37 is electrically connected with the first power supply terminal VGH, and a second pole of the thirty-seventh switching transistor T37 is electrically connected with the sixth node P6. A gate of the thirty-eighth switching transistor T38 is electrically connected with the first power supply terminal VGH, a first pole of the thirty-eighth switching transistor T38 is electrically connected to the fourth node P4, and a second pole of the thirty-eighth switching transistor T38 is electrically connected to the sixth node P6. A gate of the thirty-ninth switching transistor T39 is electrically connected to the first power supply terminal VGH, a first pole of the thirty-ninth switching transistor T39 is electrically connected with the sixth node P6, and a second pole of the thirty-ninth switching transistor T39 is electrically connected to the second node P2. A first terminal of the sixth capacitor C6 is electrically connected with the fifth node P5, and a second end of the sixth capacitor C6 is electrically connected with the seventh node P7.
The second voltage control sub-module 104 is connected with the fourth node P4, the fifth node P5, the second clock signal terminal CKB, and the second power supply terminal VGL, and the second voltage control sub-module 104 is configured to provide a second voltage of the second power supply terminal VGL to the fourth node P4 in response to the control of the voltage at the fifth node P5 and the signal of the second clock signal terminal CKB. Optionally, the second voltage control sub-module 104 may include a fortieth switching transistor T40 and a forty-first switching transistor T41. A gate of the fortieth switching transistor T40 is electrically connected with the fifth node P5, a first pole of the fortieth switching transistor T40 is electrically connected with the second power supply terminal VGL, and a second pole of the fortieth switching transistor T40 is electrically connected with a first pole of the forty-first switching transistor T41. A gate of the forty-first switching transistor T41 is electrically connected with the second clock signal terminal CKB, and a second pole of the forty-first switching transistor T41 is electrically connected with the fourth node P4.
In some embodiments, in the above-mentioned first shift register according to the embodiments of the present disclosure, as shown in
In some embodiments, in order to unify the fabrication process, in the above-mentioned first shift register according to the embodiments of the present disclosure, as shown in
In the first stage T1, the preceding stage light emitting cascade signal output terminal CR<N−1> provides a low level signal, the subsequent stage gate cascade signal output terminal GCR<N+1> provides a low level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal. The thirty-first switching transistor T31 and the thirty-second switching transistor T32 are both turned on, the forty-first switching transistor T41 is turned off, the fourth node P4 turns to a low potential, the thirty-third switching transistor T33 is turned off, the fifth node P5 turns to a high potential, both of the thirty-fourth switching transistor T34 and the fortieth switching transistor T40 are turned on, the seventh node P7 turns to a low potential, the thirty-fifth switching transistor T35 is turned off, both of the thirty-eighth switching transistor T38 and the thirty-ninth switching transistor T39 are turned on, the second node P2 turns to a low potential, all of the thirty-sixth switching transistor T36, the thirty-seventh switching transistor T37 and the twenty-third switching transistor T23 are turned off, all of the eighteenth switching transistor T18, the nineteenth switching transistor T19, the twentieth switching transistor T20, the twenty-first switching transistor T21, the twenty-second switching transistor T22 and the twenty-fourth switching transistor T24 are turned off, the twenty-third switching transistor T23 and the thirtieth switching transistor T30 are turned on due to a bootstrap action of the fifth capacitor P5, CR<N> outputs a high level signal, P1 is at a low level, both of the twenty-seventh switching transistor 27 and the twenty-eighth switching transistor T28 are turned off, the twenty-fifth switching transistor T25 is turned on, and the twenty-sixth switching transistor T26 is turned on. However, an aspect ratio of the twenty-fifth switching transistor T25 is greater than an aspect ratio of the twenty-sixth switching transistor T26, then the light emitting control drive signal output terminal EM<N> outputs a low level.
In the second stage T2, the preceding stage light emitting cascade signal output terminal CR<N−1> provides a low level signal, the subsequent stage gate cascade signal output terminal GCR<N+1> provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. Both of the thirty-first switching transistor T31 and the thirty-second switching transistor T32 are turned off, the forty-first switching transistor T41 is turned on, the fifth node P5 is further pulled up due to a bootstrap action of the sixth capacitor P6, all of the thirty-fourth switching transistor T34, the thirty-fifth switching transistor T35 and the fortieth switching transistor T40 are turned on, the first node P1 turns to a high potential, both of the twenty-seventh switching transistor T27 and the twenty-eighth switching transistor T28 are turned on, CR<N> outputs a low level signal, the eighteenth switching transistor T18 is turned on, the nineteenth switching transistor T19 is turned off, the twentieth switching transistor T20 is turned on, the twenty-fourth switching transistor T24 is turned on, the twenty-fifth switching transistor T25 is turned on, and the light emitting control drive signal output terminal EM<N> outputs a low level.
The third stage T3 includes a first stage T1 and a second stage T2 which are alternately arranged, so that the light emitting control drive signal output terminal EM<N> still outputs a low level in the third stage T3.
Timing in the fourth stage T4 is also the same as timing in the first stage T1 and timing in the second stage T2, so that the light emitting control drive signal output terminal EM<N> still outputs a low level in the fourth stage T4.
Therefore, the first shift register, as shown in
Based on the same inventive concept, a gate drive circuit 100 is also provided in an embodiment of the present disclosure. As shown in
A signal input terminal INPUT of the first shift register SR_1 located in a first stage is connected with a light emitting start signal line STV, and signal input terminals INPUT of first shift registers (SR_2, SR_3 . . . ) located in the other stages except the first stage are connected with a light emitting cascade signal output terminal CR<N> of first shift registers in a respective preceding stage.
A light emitting control drive signal output terminal EM<N> of each first shift register (SR_1, SR_2, SR_3 . . . ) is electrically connected with a corresponding light emitting control signal line EM.
In some embodiments, a first clock signal line CK1 and a second clock signal line CK2 are configured for the first gate drive circuit. In the first gate drive circuit, a first clock signal terminal CKA of a first shift register located in an odd stage is connected with a first clock signal line CK1, a second clock signal terminal CKB of the first shift register located in the odd stage is connected with a second clock signal line CK2, a first clock signal terminal CKA of a first shift register located in an even stage is connected with the second clock signal line CK2, and a second clock signal terminal CKB of the first shift register located in the even stage is connected with the first clock signal line CK1.
When a light emitting global reset circuit is arranged in the first shift register in the first gate drive circuit, the first gate drive circuit is also provided with a light emitting global reset signal line Reset, and the light emitting global reset signal terminal TRST provided in the first shift registers in each stage is connected with a same light emitting global reset signal line Reset.
Based on the same inventive concept, a display device is also provided in an embodiment of the present disclosure. As shown in
The peripheral region BB includes a first gate drive circuit for providing a light emitting control signal to the light emitting control signal line EM, wherein the first gate drive circuit is the above-mentioned gate drive circuit 100.
In some embodiments, as shown in
As shown in
As shown in
Of course, the pixel unit in the embodiments of the present disclosure may also have other circuit configurations, which are not exemplified for specific cases.
Since the principle for solving problems of the display device is similar to the principle for solving problems of any display panel described above, the implementations of the touch display panel described above may be referred to for the implementations of the display device, and repetitions will not be repeated. The display device may be any product or component with a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator and the like. An implementation of the display device can refer to an embodiment of the display panel described above, and repetitions will not be repeated.
The embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. When a row of pixel unit needs to perform external compensation sensing and the row of pixel unit receives a black insertion drive signal (i.e. inactive level signal) in a blank period if a conventional light emitting gate drive circuit is used for driving, in the embodiment of the present disclosure, a light emitting control drive signal output terminal of a first shift register corresponding to the row of pixel units which needs to perform the external compensation sensing can be controlled to forcibly output the light emitting drive signal (i.e. active level signal) through the subsequent stage gate cascade signal output terminal connected to the first shift register corresponding to the row of pixel units which performs the external compensation sensing, so that the light emitting signal received by the row of pixel units which needs to perform the external compensation sensing in the blank period is the light emitting drive signal. In other words, the row of pixel units that originally received the black insertion drive signal in the blank period and needed to perform the external compensation sensing in the blank period, actually receives the light emitting drive signal in the blank period, thus ensuring the external compensation sensing process of the row of pixel units.
Although preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once underlying inventive concepts are known. Therefore, the appended claims are intended to be interpreted to encompass preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.
Apparently, various modifications and variations to the embodiments of the present disclosure may be made by those skilled in the art without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations to the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent techniques, the present disclosure is intended to include these modifications and variations.
The present application is a U.S. National Phase Entry of International Application PCT/CN2022/128664 having an international filing date of Oct. 31, 2022, and the contents disclosed in the above-mentioned application are hereby incorporated as a part of this application.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/128664 | 10/31/2022 | WO |
