SHIFT REGISTER, SCAN DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME

Abstract

A shift register includes a plurality of stages, each of the stages generate an output signal, in sequence. Each of the shift register includes a present stage and a first capacitor. The present stage outputs an output signal based on one of a scan start signal and a carry signal of the previous stage. The first capacitor reduces a ripple component of the carry signal of the present stage which activates the next stage. Therefore, a carry signal having a reduced ripple component is supplied to the next stage, so that a transient current is intercepted at a transistor receiving the carry signal, which is arranged in the next stage, thus ensuring reliability of the shift register.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspect, features and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIG. 1 is a circuit schematic diagram illustrating a unit stage of a shift register according to a comparative embodiment of the present invention;

FIGS. 2A and 2B are waveform diagrams illustrating a gate signal that is outputted from the shift register shown in FIG. 1, when the shift register is driven in a relatively high temperature and a relatively low temperature, respectively;

FIGS. 3A and 3B are waveform diagrams illustrating gate signals corresponding to the first clock signal (CKV), when the shift register shown in FIG. 1 is driven in a relatively high temperature and a relatively low temperature, respectively;

FIG. 4 is a circuit schematic diagram illustrating a shift register according to an exemplary embodiment of the present invention;

FIG. 5 is a plan view layout diagram illustrating the shift register shown in FIG. 4;

FIG. 6 is a cross-sectional view taken along line I-I′ in FIG. 5;

FIG. 7 is a block diagram illustrating an operation of the shift register shown in FIG. 4; and

FIG. 8 is a block diagram illustrating a liquid crystal panel having a scan driving circuit according to another exemplary embodiment.

Claims

1. A shift register having a plurality of stages in which each of the stages generate an output signal in sequence, the shift register comprising: a present stage;a next stage following the present stage, the present stage outputting an output signal based on one of a scan start signal and a carry signal of a previous stage to the next stage; anda first capacitor reducing a ripple component of the carry signal of the present stage and activating a next stage.

2. The shift register of claim 1, further comprising a first clock wire which transfers a first clock signal to the present stage, wherein the first capacitor is defined by a connecting wire electrically connecting to the present stage and the next stage, the first clock wiring being overlaid with the connecting wire, and a gate insulation layer being disposed between the connecting wire and the first clock wire, the connecting wire transferring the carry signal.

3. The shift register of claim 2, wherein a low level of the first clock signal and a low level of an output signal that is outputted from the present stage are substantially equal to each other.

4. The shift register of claim 2, wherein the connecting wire electrically connects to a first transistor outputting the carry signal and a second transistor receiving the carry signal, the first transistor being arranged in the present stage, and the second transistor being arranged in the next stage.

5. The shift register of claim 4, further comprising a second capacitor electrically connected to a gate of the first transistor and a drain of the first transistor, wherein a ratio of a capacitance of the second capacitor to a capacitance of the first capacitor is set to about 1:1 to about 1:5.

6. The shift register of claim 4, further comprising a second capacitor electrically connected to a gate of the first transistor and a drain of the first transistor, wherein a ratio of a capacitance of the second capacitor to a capacitance of the first capacitor is set to about 1:1 to about 5:1.

7. The shift register of claim 4, further comprising a second capacitor electrically connected to a gate of the first transistor and a drain of the first transistor, wherein a capacitance of the first capacitor is substantially equal to a capacitance of the second capacitor.

8. A scan driving circuit comprising a plurality of stages connected to each other, a first stage of the plurality of stages includes an input terminal into which a scan start signal is inputted, each of the stages receives at least one of a first clock signal and a second clock signal having a phase opposite to the first clock signal, and each of the stages outputting an output signal to the gate lines based on one of a scan start signal and a carry signal of a previous stage,wherein the stages comprise a first capacitor arranged between adjacent stages, the first capacitor reducing a ripple component of the carry signal outputted from the present stage to activate a next stage.

9. The scan driving circuit of claim 8, wherein the first capacitor is defined by a connecting wire electrically connected to the present stage and the next stage and transferring the carry signal, the first clock wire being overlaid by the connecting wire, and a gate insulation layer being disposed between the connecting wire and the first clock wire.

10. The scan driving circuit of claim 9, wherein the connecting wire electrically connects to a first transistor and a second transistor, the first transistor being arranged in the present stage, which outputs the carry signal, and the second transistor being arranged in the next stage, receiving the carry signal.

11. The scan driving circuit of claim 10, further comprising a second capacitor connected to a gate of the first transistor and a drain of the first transistor, wherein a capacitance of the first capacitor is substantially equal to a capacitance of the second capacitor.

12. The scan driving circuit of claim 8, wherein a low level of the first clock signal is substantially equal to a low level of the output signal of the present stage.

13. The scan driving circuit of claim 8, wherein a phase of the first clock signal and that of the second clock signal are substantially opposite to each other.

14. A display device comprising: a cell array circuit formed on a substrate, the cell array circuit having a plurality of data lines and a plurality of gate lines, and each of the cell array circuits being connected to a corresponding pair of data lines and gate lines; anda scan driving circuit formed on the substrate, the scan driving circuit having a shift register including a plurality of stages connected to each other, the stages having a first stage with an input terminal into which a scan start signal is inputted, for sequentially selecting the gate lines based on an output signal of each stage, and the stages receiving at least one of a first clock signal and a second clock signal having a phase opposite to the first clock signal, andeach of the stages outputting an output signal to the gate lines based on one of a scan start signal and a carry signal of a previous stage,wherein the shift register comprises a first capacitor arranged between adjacent stages, the first capacitor reduces a ripple component of the carry signal outputted from a present stage to activate a next stage.