SHIFT REGISTER, SHIFT REGISTER ARRAY, AND FLAT DISPLAY APPARATUS

Abstract

A flat display apparatus comprising a shift register array is provided. The shift register array comprises a plurality of shift registers. At least one of these shift registers comprises a shift register unit, a first TFT, and a second TFT. The shift register unit is configured to receive an activation signal and comprises a first output terminal and a second output terminal. The gate of the first TFT is coupled to the first output terminal. The second electrode of the first TFT receives a clock signal. The gate of the second TFT is coupled to the first electrode of the first TFT. The second electrode of the second TFT is coupled to the second electrode of the first TFT. The first electrode of the second TFT is coupled to the second output terminal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior art shift register;

FIG. 2 is a timing diagram of FIG. 1;

FIG. 3 is a diagram of an output waveform of a shift register of FIG. 1;

FIG. 4A is a diagram of a display panel of the first embodiment;

FIG. 4B is a diagram of a shift register array of the first embodiment;

FIG. 4C is a diagram of a shift register of the first embodiment;

FIG. 5 is a timing diagram of the first embodiment;

FIG. 6 is a diagram of an output waveform of a shift register of the first embodiment; and

FIG. 7 is a diagram of a shift register of the second embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A first embodiment of this invention is a flat display apparatus, such as an LCD. The LCD comprises a display panel 4 as shown in FIG. 4A. The display panel 4 comprises a display array 41, a gate driving circuit 42 and a data driving circuit 43. The display array 41 comprises a plurality of pixels 411. FIG. 4B shows a shift register array 44 comprised in the gate driving circuit 42. The shift register array 44 comprises a plurality of shift registers 45. Each output of these shift registers 45 is coupled to an input of next shift register 45 except the last stage shift register 45. A connection relationship in these shift registers 45 is well known to those skilled in the art and thus is not detailed here. Each of these shift registers 45 is used to drive one row of pixels of the display array. For example, an N-th shift register 45 is used to drive an N-th row of pixels.

In general, a structure for each of the shift registers 45 is the same, but not limited to. However, this invention does not require that the structure of each of the shift registers 45 be the same. FIG. 4C shows the N-th shift register 45 of the first embodiment. The shift register 45 comprises a first TFT 451, a second TFT 452, a third TFT 453, a fourth TFT 454, a fifth TFT 455, a sixth TFT 456, a seventh TFT 457, a eighth TFT 458, a ninth TFT 459, a tenth TFT 460, an eleventh TFT 461, a twelfth TFT 462 and a thirteenth TFT 463. In the figure, STN-1 represents an input signal of the N-th shift register 45, i.e., a signal outputted from the (N-1)th shift register, which corresponds to ST of FIG. 4B. N represents an output of the N-th shift register, CK represents a positive clock signal, and XCK represents a negative clock signal.

In the first embodiment, the third TFT 453, the fourth TFT 454, the fifth TFT 455, the sixth TFT 456, the seventh TFT 457, the eighth TFT 458, the ninth TFT 459, the tenth TFT 460, the eleventh TFT 461, the twelfth TFT 462, and the thirteenth TFT 463 form a shift register unit 470. The shift register unit 470 is configured to receive an activation signal and comprises a first output terminal 471 and a second output terminal 472. The second output terminal 472 is coupled to the N-th row of pixels PIXEL N, and drives the PIXEL N. In addition, the second terminal 472 is coupled to a next shift register 45.

To be more specific, each of the transistors comprises a gate electrode, a first electrode and a second electrode. In this embodiment, the first electrode can be a source electrode and the second electrode can be a drain electrode. The gate electrode of the third TFT 453 receives the input signal STN-1. The gate electrode of the fourth TFT 454 receives the negative clock signal XCK. The first electrode of the fourth TFT 454 is coupled to the first electrode of the third TFT 453. The second electrode of the fourth TFT 454 is coupled to the second electrode of the third TFT 453 and the input signal STN-1. The gate electrode of the fifth TFT 455 receives the input signal STN-1 as well. The first electrode of the fifth TFT 455 is coupled to a power supply VSS. The gate electrode of the sixth TFT 456 receives a positive clock signal CK. The first electrode of the sixth TFT 456 is coupled to the second electrode of the fifth TFT 455. The second electrode of the sixth TFT 456 is coupled to the gate electrode of the sixth TFT 456. The gate electrode of the seventh TFT 457 receives the negative clock signal XCK. The first electrode of the seventh TFT 457 is coupled to the power supply VSS. The second electrode of the seventh TFT 457 is coupled to the second electrode of the fifth TFT 455. The gate electrode of the eighth TFT 458 is coupled to the second electrode of the fifth TFT 455. The first electrode of the eighth TFT 458 is coupled to the power supply VSS. The second electrode of the eighth TFT 458 is coupled to the first electrode of the third TFT 453. The gate electrode of the ninth TFT 459 is coupled to the second electrode of the fifth TFT 455. The first electrode of the ninth TFT 459 is coupled to the power supply VSS. The gate electrode of the tenth TFT 460 is coupled to the second electrode of the ninth TFT 459. The first electrode of the tenth TFT 460 is coupled to the power supply VSS. The second electrode of the tenth TFT 460 is coupled to the second electrode of the fifth TFT 455. The gate electrode of the eleventh TFT 461 receives the negative clock signal XCK. The first electrode of the eleventh TFT 461 is coupled to the power supply VSS. The second electrode of the eleventh TFT 461 is coupled to the second electrode of the ninth TFT 459. The gate electrode of the twelfth TFT 462 receives an output signal N+1 of the next shift register. The first electrode of the twelfth TFT 462 is coupled to power supply VSS. The second electrode of the twelfth TFT 462 is coupled to the second electrode of the ninth TFT 459. The gate electrode of the thirteenth TFT 463 is coupled to the gate electrode of the twelfth TFT 462. The first electrode of the thirteenth TFT 463 is coupled to the power supply VSS. The second electrode of the thirteenth TFT 463 is coupled to the first electrode of the third TFT 453. The twelfth TFT 462 and the thirteenth TFT 463 form a pull down module 473 to keep a node Q at a certain voltage level for a specific time period while a waveform of the node Q rises.

The first output terminal 471 of the shift register unit 470 is the first electrode of the third TFT 453 and the second output terminal 472 is the second electrode of the twelfth TFT 462. Furthermore, the gate electrode of the first TFT 451 is coupled to the first output terminal 471 of the shift register unit 470, i.e. the first electrode of the third TFT 453. The second electrode of the first TFT 451 receives the positive clock signal CK. The gate electrode of the second TFT 452 is coupled to the first electrode of the first TFT 451. The first electrode of the second TFT 452 is coupled to the second output terminal 472 of the shift register unit 470, i.e., the second electrode of the twelfth TFT 462. The second electrode of the second TFT 452 is coupled to the second electrode of the first TFT 451.

In the first embodiment, a channel width of the second TFT 452 is larger than a channel width of the first TFT 451, for example, a ratio between them is 10:1. If the channel width of the second TFT 452 is 12000 μm, the channel width of the first TFT 451 is 1200 μm. Since a parasitic capacitance of the first TFT 451 is smaller than that of the second TFT 452, a coupling effect of the output terminal of the shift register 45 is reduced.

It is important to emphasize that the channel widths for the second TFT 452 and the first TFT 451 are not limited to the mentioned numbers. As long as the channel width of the second TFT 452 is larger than the channel width of the first TFT 451, the object of this invention can be achieved.

FIG. 5 shows a timing diagram of the first embodiment. As shown in the dotted circle 51, when the negative clock signal XCK rises, i.e. the positive clock signal CK falls, some electric charges remain at the node Q, so that the first TFT 451 stays in an activation state to process the output signal PIXEL N continuously, i.e., process a falling portion of the waveform PIXEL N. Consequently, the falling time of the output waveform of first embodiment is shorter. As shown in FIG. 6, the falling time of the output waveform of first embodiment is shorter, which is about 3.9 Is.

FIG. 7 shows a second embodiment of this invention, which is also a shift register. The difference between the first embodiment and the second embodiment is that the first electrode of the first TFT 751 of the shift register 7 in the second embodiment is coupled to the STN, i.e., the ST position of the next shift register, and the first electrode of the second TFT 752 is only coupled to the pixels PIXEL N. The advantage of this configuration is that the operation of the next shift register will not be affected when the second TFT 752 of the shift register or the PIXEL N does not operate normally.

According to the above descriptions, the output terminal of the shift register is properly coupled to two TFTs in this invention. The coupled capacitance is reduced because the size of the first TFT is smaller than the size of the second TFT, which further reduces the possibility of an erroneous operation of a next shift register. Additionally, the pull down module in the invention keeps some electric charges at node Q while the negative clock signal rises, i.e. when the positive clock signal falls, further shortening the falling time of the output waveform. Consequently, a more stable display effect can be achieved with the liquid crystal display apparatus of the invention.

The above disclosure is related to the detailed technical contents and inventive features thereof. Those skilled in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.

Claims

1. A shift register, comprising: a shift register unit, having a first output terminal and a second output terminal, for receiving an activation signal;a first thin-film transistor (TFT), having a gate, a first electrode, and a second electrode, the gate of the first TFT being coupled to the first output terminal, the second electrode of the first TFT receiving a clock signal; anda second TFT, having a gate, a first electrode, and a second electrode, the gate of the second TFT being coupled to the first electrode of the first TFT, the first electrode of the second TFT being coupled to the second output terminal, the second electrode of the second TFT being coupled to the second electrode of the first TFT.

2. The shift register of claim 1, wherein a channel width of the second TFT is larger than a channel width of the first TFT.

3. The shift register of claim 1, wherein a ratio of a channel width of the second TFT to a channel width of the first TFT is 10:1.

4. The shift register of claim 1, wherein a channel width of the first TFT is 1200 μm and a channel width of the second TFT is 12000 μm.

5. The shift register of claim 1, wherein the shift register drives a row of pixels of a display array and the second output terminals is coupled to the row of the pixels.

6. The shift register of claim 1, wherein the second output terminal is coupled to a next shift register.

7. The shift register of claim 1, wherein the first electrode of the first TFT is coupled to a next shift register.

8. A shift register array, including a plurality of shift registers connecting in series, at least one of the shift register comprising: a shift register unit, having a first output terminal and a second output terminal, for receiving an activation signal;a first TFT, having a gate, a first electrode, and a second electrode, the gate of the first TFT being coupled to the first output terminal, and the second electrode of the first TFT receiving a clock signal; anda second TFT, having a gate, a first electrode, and a second electrode, the gate of the second TFT being coupled to the first electrode of the first TFT, the first electrode of the second TFT being coupled to the second output terminal and the second electrode of the second TFT being coupled to the second electrode of the first TFT.

9. The shift register array of claim 8, wherein a channel width of the second TFT is larger than a channel width of the first TFT.

10. The shift register array of claim 8, wherein a ratio of a channel width of the second TFT to a channel width of the first TFT is 10:1.

11. The shift register array of claim 8, wherein a channel width of the first TFT is 1200 μm and a channel width of the second TFT is 12000 μm.

12. The shift register array of claim 8, wherein the shift register drives a display array and the second output terminals is coupled to a corresponding pixel of the display array.

13. The shift register array of claim 8, wherein the second output terminal is coupled to a next shift register.

14. The shift register array of claim 8, wherein the first electrode of the first TFT is coupled to a next shift register.

15. A flat display apparatus, comprising: a display array, having a plurality of pixels; anda shift register array, having a plurality of shift registers, each of the shift registers driving a row of pixels of the display array, at least one of the shift registers comprising: a shift register unit, having a first output terminal and a second output terminal, for receiving an activation signal;a first TFT, having a gate, a first electrode, and a second electrode, the gate of the first TFT being coupled to the first output terminal, and the second electrode of the first TFT receiving a clock signal; anda second TFT, having a gate, a first electrode, and a second electrode, the gate of the second TFT being coupled to the first electrode of the first TFT, the first electrode of the second TFT being coupled to the second output terminal and the second electrode of the second TFT being coupled to the second electrode of the first TFT.

16. The flat display apparatus of claim 15, wherein a channel width of the second TFT is larger than a channel width of the first TFT.

17. The flat display apparatus of claim 15, wherein a ratio of a channel width of the second TFT to a channel width of the first TFT is 10:1.

18. The flat display apparatus of claim 15, wherein a channel width of the first TFT is 1200 μm and a channel width of the second TFT is 12000 μm.

19. The flat display apparatus of claim 15, wherein the second output terminals is coupled to a row of the pixels.

20. The flat display apparatus of claim 15, wherein the second output terminal is coupled to a next shift register.

21. The flat display apparatus of claim 15, wherein the first electrode of the first TFT is coupled to a next shift register.