Patent Application
20230038891
The subject matter disclosed herein relates to neural networks. More particularly, the subject matter disclosed herein relates to a technique for reducing computation and parameters associated with a differentiable architecture search normal cell architecture
An example embodiment provides a method for reducing computation of a differentiable architecture search in which the method may include forming an output node having a channel dimension that is one-fourth of a channel dimension of a normal cell for a first layer of the cells in a neural network architecture by averaging channel outputs of intermediate nodes of the normal cell; and preprocessing the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell using a 1×1 convolution to form channels of input nodes for a second layer of the cells in the neural network architecture in which the second layer may be immediately subsequent to the first layer. In one embodiment, forming the output node having a single channel for the normal cell for the first layer of the cells in the neural network architecture may include: forming s groups of channel outputs of the intermediate nodes in which each group may include a total number of channel outputs of the intermediate nodes divided by a splitting parameter s; forming an average channel output for each group of channel outputs by averaging each group of channel outputs; and forming the output node by concatenating the average channel output for each group of channels with channel outputs of the intermediate nodes of the normal cell. In one embodiment, the method may further include changing a number of output channels of the first layer of the cells in the neural network architecture with respect to a number of input channels of the first layer. In another embodiment, changing the number of output channels of the first layer of the cells in the neural network architecture may include increasing the number of output channels of the first layer of the cells in the neural network architecture with respect to the number of input channels of the first layer. In still another embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell may include forming the output node by averaging channel outputs of intermediate nodes of the normal cell or by selecting a maximum output from intermediate nodes of the normal cell. In yet another embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell may further include forming the output node by averaging channel outputs of intermediate nodes of the normal cell or by performing a weighted average of the channel outputs of intermediate nodes of the normal cell. In one embodiment, the weighted average may be performed on channel outputs of intermediate nodes, and the method may further include batch normalizing the output node of the first layer of the cells in the neural network architecture. Another embodiment may further include generating a first predetermined number of intrinsic feature maps for the first layer of the cells in the neural network architecture in which the first predetermined number may be less than a second predetermined number that may be equal to a total number of output nodes for the first layer; and using one or more linear transformation operators to generate a third predetermined number of correlated or redundant output nodes for the first layer in which the first predetermined number plus the third predetermined number may equal the second predetermined number.
An example embodiment provides a method for reducing computation of a differentiable architecture search in which the method may include: forming an output node having a channel dimension that is one-fourth of a channel dimension of a normal cell for a first layer of the cells in a neural network architecture by selecting a maximum channel output from intermediate nodes of the normal cell; and preprocessing the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell using a 1×1 convolution to form channels of input nodes for a second layer of the cells in the neural network architecture in which the second layer may be immediately subsequent to the first layer. In one embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell may include: forming s groups of channel outputs of the intermediate nodes in which each group includes a total number of channel outputs of the intermediate nodes divided by a splitting parameter s; selecting a maximum channel output for each group of channel outputs; and forming the output node by concatenating the maximum channel output for each group of channels with channel outputs of the intermediate nodes of the normal cell. In another embodiment, the method may further include changing a number of output channels of the first layer of the architecture with respect to a number of input channels of the first layer. In one embodiment, changing the number of output channels of the first layer of the cells in neural network architecture may include increasing the number of output channels of the first layer of the cells in the neural network architecture with respect to the number of input channels of the first layer. In another embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell may include forming the output node by selecting a maximum output from intermediate nodes of the normal cell or by averaging channel outputs of intermediate nodes of the normal cell. In still another embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell may further include forming the output node by selecting a maximum output from intermediate nodes of the normal cell or by performing a weighted average of channel outputs of intermediate nodes of the normal cell. In yet another embodiment, a weighted average is performed on channel outputs of intermediate nodes, and the method may further include batch normalizing the output node of the first layer of the cells in the neural network architecture. In one embodiment, the method may further include generating a first predetermined number of intrinsic feature maps for the first layer of the cells in the neural network architecture in which the first predetermined number may be less than a second predetermined number that may be equal to a total number of output nodes for the first layer; and using one or more linear transformation operators to generate a third predetermined number of correlated or redundant output nodes for the first layer in which the first predetermined number plus the third predetermined number may equal the second predetermined number.
An example embodiment provides a method for reducing computation of a differentiable architecture search that may include: forming an output node having a channel dimension that is one-fourth of a channel dimension of a normal cell for a first layer of a neural network architecture by performing a weighted average of channel outputs of intermediate nodes of the normal cell; and preprocessing the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell using a 1×1 convolution to form channels of input nodes for a second layer of the cells in the neural network architecture in which the second layer may be immediately subsequent to the first layer. In one embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell may include: forming s groups of channel outputs of the intermediate nodes in which each group includes a total number of channel outputs of the intermediate nodes divided by a splitting parameter s; forming a weighted-average channel output for each group of channel outputs by weight averaging each group of channel outputs; and forming the output node by concatenating the weighted-average channel output for each group of channels with channel outputs of the intermediate nodes of the normal cell. In one embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell further may include forming the output node by performing a weighted average of channel outputs of intermediate nodes of the normal cell or by averaging channel outputs of intermediate nodes of the normal cell. In another embodiment, forming the output node having the channel dimension that is one-fourth of the channel dimension of a normal cell may further include forming the output node by performing a weighted average of channel outputs of intermediate nodes of the normal cell or by selecting a maximum output from intermediate nodes of the normal cell.
In the following section, the aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments illustrated in the figures, in which:
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail to not obscure the subject matter disclosed herein.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. Similarly, a hyphenated term (e.g., “two-dimensional,” “pre-determined,” “pixel-specific,” etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., “two dimensional,” “predetermined,” “pixel specific,” etc.), and a capitalized entry (e.g., “Counter Clock,” “Row Select,” “PIXOUT,” etc.) may be interchangeably used with a corresponding non-capitalized version (e.g., “counter clock,” “row select,” “pixout,” etc.). Such occasional interchangeable uses shall not be considered inconsistent with each other.
Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element or layer is referred to as being on, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the term “module” refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein in connection with a module. For example, software may be embodied as a software package, code and/or instruction set or instructions, and the term “hardware,” as used in any implementation described herein, may include, for example, singly or in any combination, an assembly, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, but not limited to, an integrated circuit (IC), system-on-a-chip (SoC), an assembly, and so forth.
The subject matter disclosed herein provides a method for reducing the number of computations and the number of parameters involved with a DARTS search by using an average or alternatively using a maximum of the four intermediate nodes to produce an output node of a normal cell instead of a concatenation of the four intermediate nodes. Channel-wise averaging or maximum pooling reduces the number of channels by four.
For example, a base line number for an example neural network system may include 3.42 M parameters with 532.5 M flop computations. Using the DARTS shrinkage techniques disclosed herein may reduce the number of parameters to 2.4 M for the example neural network system, and may reduce the number of computations to 373 M flop, which is about a 30% reduction for both the number of parameters and the number of computations with only about a 0.15% reduction in accuracy.
One embodiment of the subject matter disclosed herein provides different DARTS shrinkage types that primarily differ based on how the output of a DARTS normal cell is generated. A hyper-parameter s in which in which s=1 to 4 may be used for generating the output node c_{k}. The channels output from the intermediate nodes 0-4 of a DARTS normal cell for a given layer of a neural network architecture may be split, or grouped, into 1 to 4 sets depending on the selected hyper-parameter s so that each group has C/s channels. An average of the outputs of each grouped channels (i.e., average pooling) is determined. Alternatively, a maximize value in each group may be selected (i.e., max pooling). As another alternative, an adaptive averaging (ada pooling), which uses a weighted averaging, is determined. The output channels may then be concatenated (C/s)×4 so that the output channel becomes 4C→(C/s)×4. Different layers of a neural network architecture may have different split configurations.
Table 1 shows results for two example DARTS shrinkage architecture types (shrink_type 0 and shrink_type 1) for an example 19-layer neural network architecture. The shrink_type 0 architecture is the example baseline neural network system described earlier and uses a hyper-parameter s=1, whereas the shrink_type 1 architecture uses a hyper-parameter s=4. It should be noted that a shrinkage type architecture may use a hyper-parameter s of a single value, or may use multiple hyper-parameters s of different values.
As the location of a DARTS normal cell in a neural network architecture increases (i.e., becomes deeper), the number of output channels of may progressively increase.
Table 2 shows some example details associated with ten (10) example shrinkage architecture (arch) types 0-9 that use average pooling with no batch normalization (BN). PDARTS refers to progressive DARTS. A shrink_type 3 architecture, for example, provided the best accuracy of 97.49% with about a 10% reduction in flops as compared to the baseline example neural network system (shrink_type 0 architecture) that included 3.42 M parameters with 532.5 M flop computations. Shrink-types 5, 6 and 8 provided comparable accuracies with about a 22% reduction in flops.
Tables 3-6 show some example details of shrinkage architecture types 3, 5, 6 and 8. The box outline in each of Tables 3-6 highlight different input and output channel numbers for different layers of the example neural network architecture. Only the outputs of the first six layer of shrink_type 3 architecture were shrunk. Shrink-types 5, 6 and 8 architectures had differing amounts of layers having outputs that were shrunk (i.e., different hyper-parameters s) indicated by the box outlines.
Average pooling may be used on the split channel outputs (i.e., average pooling) from the intermediate nodes 0-4 to form the output node c_{k}. For average pooling, c_{k}=(node1+node2+node3+node4)/4. Alternatively, maximum pooling may be used to form the output node c_{k} from the split channels. For maximum pooling, c_{k}=max(node1, node2, node3, node4). As yet another alternative is adaptive averaging (ada pooling), which uses a weighted averaging, to form the output node c_{k} from the split channels. For adaptive pooling, c_{k}=(node1*w1+node2*w2+node3*w3+node4*w4)/4.
After pooling, a batch normalization (BN) may optionally be added. Batch normalization may not change the results for average pooling or maximum pooling, but may provide a benefit for adaptive pooling. Table 7 shows example results for four example shrinkage architecture types for the three different pooling techniques with and without batch normalization. It should be noted that using adaptive pooling with batch normalization for shrink_type 3 architecture results in a greater accuracy than the baseline example neural network architecture.
To further reduce the number of computations associated with a DARTs normal cell, one or more ghost modules may be used to generate correlated and redundant feature maps from intrinsic feature maps by using, for example, linear transformation operators.
Table 8 shows example results for four example shrinkage architecture types with and without Ghost modules for the three different pooling techniques and with and without batch normalization.
Embodiments of the subject matter and the operations described in this specification may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer-program instructions, encoded on computer-storage medium for execution by, or to control the operation of data-processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. A computer-storage medium can be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial-access memory array or device, or a combination thereof. Moreover, while a computer-storage medium is not a propagated signal, a computer-storage medium may be a source or destination of computer-program instructions encoded in an artificially-generated propagated signal. The computer-storage medium can also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Additionally, the operations described in this specification may be implemented as operations performed by a data-processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.
While this specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather be construed as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
Thus, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.
As will be recognized by those skilled in the art, the innovative concepts described herein may be modified and varied over a wide range of applications. Accordingly, the scope of claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the following claims.
This application claims the priority benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63/225,435, filed on Jul. 23, 2021, the disclosure of which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63225435 | Jul 2021 | US |
