This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-010989, filed Jan. 27, 2022, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a side erase measuring method and a refresh process method.
In magnetic disk devices, when data are written to a disk, such data may be erased because of an influence of flux leaked from a head or the like (adjacent track interference: ATI), which is referred to as side erase. Different ATIs are caused based on head characteristics, track per inch (TPI) setting values, and write current setting values. In order to prevent the side erase, magnetic disk devices have a function to rewrite data of a certain track when the number of write of data to peripheral tracks of the certain track reaches a predetermined number (which may be referred to as refresh function or ATI refresh function). A trigger used to start the refresh function may be a track profile indicative of influential degree of side erase.
However, depending on methods of acquiring track profile, the refresh function may not perform well, and rewrite is not performed timely.
The embodiments of the present application will present a side erase measuring method and a refresh process method, which are to improve the reliability of data.
In general, according to one embodiment, a side erase measuring method used in a disk-shaped magnetic disk including a plurality of tracks which are areas defined concentrically from a center part in a radial direction and a plurality of sectors defined in a circumferential direction, the method include selecting one center track from the tracks and a plurality of peripheral tracks continuous from tracks adjacent to the center track concentrically outward and inward in the radial direction, and a plurality of target sectors, selecting a bit error rate (BER) measuring sector to measure a BER from the target sectors in the peripheral tracks such that sectors differ between adjacent peripheral tracks, counting a center track write number which is a write number per write of data to all the target sectors of the center track, and measuring BER in the BER measuring sector per a predetermined number of the center track write number.
Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that, the drawings are only an example and do not limit the scope of the invention.
The magnetic disk device 1 includes a head disk assembly (HDA) 100, which will be described below, driver IC20, head amplifier IC30 which is a head amplifier integrated circuit, volatile memory 70, buffer memory (buffer) 80, non-volatile memory 90, and system controller 130 which is a single-chip integrated circuit. Furthermore, the magnetic disk device 1 is connected to a host system 2.
The host system 2 is, for example, a personal computer that outputs data read/write commands to the magnetic disk device 1. The host system 2 may also include programs for BER measurement and may control the magnetic disk device 1 in BER measurement.
The HDA100 includes a magnetic disk (hereinafter referred to as disk) 10, spindle motor (hereinafter referred to as SPM) 12, arm 13 which mounts a head 15, and voice coil motor (hereinafter referred to as VCM) 14.
The disk 10 is mounted on the spindle motor 12, and is rotated by drive of the spindle motor 12. The arm 13 and the VCM 14 structure an actuator. By drive of the VCM 14, the head mounted on the arm 13 is moved to a target position on the disk 10. The number of the disk 10 and the head 15 may be two or more.
The disk 10 is a disk-shaped rotatable disk storage medium, and in the area where data can be written, a user data area 10a which is available for the user, and a system area 10b where information necessary for system management is written are allocated. In the following description, a direction orthogonal to the radial direction of the disk 10 will be referred to as circumferential direction.
The spindle 12 is a prop of the disk 10 and is installed in the casing of the magnetic disk or the like. The rotation of the spindle 12 causes the disk 10 to rotate.
The disk 10 includes a plurality of tracks TR set concentrically around the spindle 12, and a plurality of sector regions SCT in the circumferential direction. Data are written to the tracks TR, and the head 15 writes data in each sector area SCT of the track TR, or reads the written data therein. The intersection of track TR and sector area SCT will be referred to as target data sector TGT.
A track TR(TRN) indicates a track TR with a track number TRN. For example, track TR with track number 0 will be indicated as track TR(0). Similarly, TR(TRN+1), TR(TRN−1) adjacent to TR(TRN) will be referred to as adjacent tracks of TR(TRN).
Referring back to
The VCM 14 is a voice coil motor for moving the arm 13.
The head 15 includes a slider as the main body thereof, and a write head 15W and a read head 15R mounted on the slider. The write head 15W writes data to the disk 10. The read head 15R reads data recorded on the data track of the disk 10.
The driver IC 20 controls the SPM 12 and the VCM 14 in accordance with the system controller 130.
The head amplifier IC 30 includes a read amplifier and a write driver. The read amplifier amplifies read signals read from the disk 10 and outputs the amplified signals to the system controller 130. The write driver outputs write current corresponding to the signals output from the R/W channel 40 to the head 15.
The volatile memory 70 is a semiconductor memory which loses data stored therein when the power supply is cut off. The volatile memory 70 stores data and other data necessary for processing of the magnetic disk device 1. The volatile memory 70 is, for example, a dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM).
The buffer memory 80 is a semiconductor memory which temporarily records data or the like transmitted and received between the magnetic disk device 1 and the host system 2. Note that, the buffer memory 80 may be configured integrally with the volatile memory 70. The buffer memory 80 is, for example, a DRAM, static random access memory (SRAM), SDRAM ferroelectric random access memory (FeRAM), or magnetoresistive random access memory (MRAM).
The nonvolatile memory 90 is a semiconductor memory which records stored data even when the power supply is cut off. The nonvolatile memory 90 is, for example, a NOR or NAND flash read only memory (FROM).
The system controller 130 may be realized using, for example, a large-scale integrated circuit (LSI) which will be referred to as system-on-a-chip (SoC) in which a plurality of elements are integrated into a single chip. The system controller 130 includes a read/write (R/W) channel 40, hard disk controller (HDC) 50, and microprocessor (MPU) 60. The system controller 130 is electrically connected to, for example, the driver IC 20, head amplifier IC 30, volatile memory 70, buffer memory 80, nonvolatile memory 90, and host system 2.
The R/W channel 40 performs signal processing of read data transferred from the disk 10 to the host system 2 and write data transferred from the host system 2 in response to instructions from the MPU 60, which will be described later. The R/W channel 40 includes a circuit to measure signal quality of the read data or a function to perform the same. The R/W channel 40 is electrically connected to the head amplifier IC 30, HDC50, MPU 60.
The HDC50 serves as the interface between the magnetic disk device 1 and the host system 2, and receives commands from the host system 2 such as data write commands to the disk 10 and data read commands from the disk 10. The HDC50 controls internal components of the magnetic disk device 1 and transfers data between the host system 2 and the R/W channel 40. The HDC50 is electrically connected to, for example, the R/W channel 40, MPU 60, volatile memory 70, buffer memory 80, and nonvolatile memory 90.
The MPU60 is a main controller which controls each component of the magnetic disk device 1. The MPU60 controls the VCM14 via the driver IC 20, and executes servo control for positioning the head 15. The MPU60 controls the write operation of data to the disk 10 and selects the destination for storing the write data. Furthermore, the MPU60 controls the read operation of data from the disk 10, and controls the processing of read data. The MPU60 is connected to each part of the magnetic disk device 1. The MPU60 is electrically connected to, for example, the driver IC 20, R/W channel 40, and HDC50.
The MPU 60 includes a read/write controller 61, counter 62, and refresh processor 63. The MPU 60 executes the processing of, for example, the read/write controller 61, counter 62, and refresh processor 63, using programs such as firmware. Note that, the MPU 60 may include each of such components as hardware such as circuitry.
The read/write controller 61 controls data read processing and data write processing according to commands from the host system 2. The read/write controller 61 controls the VCM 14 via the driver IC 20, and positions the head 15 at a target position of the disk 10 to read or write data.
The counter 62 is used to count the number N(TRN) indicating how many times data have been written to track TR(TRN) (hereinafter referred to as count number or write number) for each track TR(TRN). The counter 62 counts the number of write counts N(TRN) per track TR and per sector SCT, and in that case, the write counts will be indicated as N(TRN, SCTN), where SCTN indicates the sector number. Furthermore, the counter 62 may count the number N_A(TRN) of adjacent write counts when data are written to tracks TR(TRN+1) and TR(TRN−1) adjacent to the track TR(TRN).
The refresh processor 63 executes refresh processing (or may be simply referred to as refresh). The refresh processing is a process for reducing the effects of side erase caused by adjacent track interference in the disk 10. For example, in the refresh process, data written to a specific recording area on the disk 10 are read once and the read data are rewritten to the specific recording area. The data written to the disk 10 may sometimes be altered when data are written to adjacent tracks thereof, for example, and such altered data cannot be read (and this phenomenon is generally referred to as side erase). The effect of side erase can be reduced by the refresh process. The refresh processor 63 executes the refreshing process of data of the adjacent tracks or peripheral tracks including the adjacent tracks based on the number of write counts N(TRN) counted by the counter 62 and a preset threshold (which will be referred to as refresh threshold).
Since the side erase may affect tracks distant from the written (data-written) track (referred to as write track), there is a track profile weight table which weights the degree of erase influence on the peripheral tracks. The refresh threshold is determined based on the track profile weight table, and the determination method will be described later.
The HDC 50 receives a data write command (write request) to a track TR(TRN) of track number TRN from the host 2 (Step S101). The HDC 50 sends the write request together with the data to the read/write controller 61, and also orders the counter 62 to count the write number N(TRN) which indicates the write counts to the track TR (Step S102).
The counter 62 compares N(TRN) with the threshold value TH_W, and if N(TRN)>TH_W (Yes in Step S103), orders the refresh processor 63 to perform refresh processing (step S104). In step S104, data of the adjacent tracks TR(TRN-1) and TR(TRN+1) or the data of the peripheral tracks including the adjacent tracks are refreshed. Upon completion of the execution of step S104, the counter 62 clears N(TRN) (step S105). In step S103, the write number N(TRN) of the tracks TR(TRN) is equal to or less than the threshold value TH_W, a next write request is awaited (No in Step S103).
The threshold TH_W in step S103 is determined from, for example, the track profile which indicates the degree of influence of side erase obtained by separate evaluation. In the present embodiment, side erase is measured considering the effect of data write to adjacent tracks.
Track TR(0) will be referred to as center track, and tracks on both sides of track TR(0) will be referred to as peripheral tracks. In the side erase measurement of the present embodiment, the effect of side erase on the peripheral tracks when data are repeatedly written (overwritten) to track TR(0) is measured. In
To perform the BER measurement, for example, known data may be written in advance in the BER measurement area, and the host system 2 reads the data from the BER measurement area and compares the read data with the known data.
In the peripheral tracks where BER is measured, one or more writes are performed in the area other than the area of BER measurement before consecutive writes are performed to track TR(0) as the center tracks, or after the specific number of consecutive writes is made to track TR(0). The sector to be written one or more times in the peripheral tracks will be referred to as write sector. As in
Then, the continuous writes to track TR(0) is performed, and for each specific number of continuous writes, BER is measured with respect to the BER measurement area. This is repeated until the specific number of writes is reached, and dependence of write number of BER is obtained.
A central track TR and peripheral tracks TR of the disk 10 to be subjected to BER measurement is selected (Step S200).
BER measuring sector is allocated with respect to the evaluation target sector SCT selected in step S201 (Step S202). Specifically, as in
Known data are put in the BER measuring sectors of the peripheral tracks (Step S203). The known data in step S203 are the data for BER measurement. In step S203, the known data may be put in all the evaluation target sectors SCT in the peripheral tracks.
Data are once written to the write sectors of the peripheral tracks (Step S204). Specifically, as in
Data are written once to sector areas SCT1, SCT2, and SCT3 of the central track TR(0) (Step S205). The counter 62 increases the number N of writes to the central track TR(0) by one (Step S206).
BER measurement is performed with respect to the BER measurement areas shown in
BER measurement is performed with respect to all peripheral tracks TR(TRN) (Step S208). BER with respect to track TR(TRN) will be BER1(TRN, N(0)) when the influence of adjacent tracks is considered, and BER2(TRN, N(0)) when the influence of adjacent tracks is not considered, and the above two will be collectively referred to as BER(TRN, N(0)).
Specifically, for example, in
Furthermore, from a result of the BER measurement with respect to the sector area SCT3, BER2(TRN, N(0)) when the influence of adjacent tracks is not considered is obtained. Through the above procedure, BER(TRN, N(0)) of the peripheral tracks in the case where data are written once to the sector areas SCT1, SCT2, and SCT3 of the central track TR(0) is obtained (Step S208).
BER(TRN, N(0)) is compared to BER threshold TH_B(TRN) preset with respect to track TR(TRN), (Step S209). If the BER(TRN, N(0)) exceeds TH_B(TRN) (Yes in Step S209), N(0) at that time is set as write number threshold with respect to the track TR(TRN), and is stored in a memory or the like (Step S210). Specifically, in step S209, if BER1(TRN, N(0))>TH_B(TRN), then in step S210, the write number threshold TH_W1(TRN) is set to N(0), and stored in a volatile memory 70 or the like.
Also, in step S209, if BER2(TRN, N(0))>TH_B(TRN), then in step S210, the write number threshold TH_W2(TRN) is set to N(0), and stored in a volatile memory 70 or the like. The write number threshold TH_W1(TRN) is a write number threshold when the influence of adjacent writes is considered, and the write number threshold TH_W2(TRN) is a write number threshold when the influence of adjacent writes is not considered. Note that, TH_B(TRN) may be different from both BER1(TRN, N(0)) and BER2(TRN, N(0)). Furthermore, TH_B(TRN) may be a value for each TRN, or it may be a value for all TRNs.
After performing steps S207 to S211 with respect to all tracks TR(TRN), whether or not all write number thresholds TH_W1(TRN) and TH_W2 (TRN) are acquired with respect to all tracks TR(TRN), and if not, the processes from step S205 and thereafter are repeated (No in Step S212). If they have been obtained (Yes in Step S212), minimum values are extracted from each of the write number thresholds TH_W1(TRN) and TH_W2(TRN) acquired with respect to all peripheral tracks, and the extracted values are determined as the write number thresholds TH_W1 and TH_W2 (Step S213).
Characteristics B1, B2, B3, B4, and B5 indicate examples of the BERs of track TR of the peripheral tracks TRN=−2, −1, +1, +2, and +8, respectively, where the BERs are measured after the write number N(0) to the center track TR(0) is set to 1000, 2000, 4000, 7000, and 10000 times, respectively. Each indicates BER characteristics of cases with adjacent writes obtained from sector areas SCT1 and SCT2 and without adjacent writes obtained from sector area SCT3. As indicated by each of BER characteristics B1, B2, B3, B4, and B5, a linear dependence is shown between the logarithm of the number of writes and the BER. Based on the obtained data of the above dependence, for example, the maximum number which does not exceed the allowable BER threshold (TH_B(TRN) of step S209 of
For example, data D1 indicates that the write number threshold TH_W1 of TR(−2) is 3607 and TH_W2(−2) thereof is 1137. D6 in
By applying the thresholds obtained by the above procedure to the flowchart of
In the present embodiment, explained is an example where adjacent write number N_A(TRN) is counted, when writes are made to track TR(TRN), using the write number thresholds TH_W1(TRN) and TH_W2(TRN) obtained from the side erase measuring method of the first embodiment. A counter 62 in this example includes an adjacent write counter that counts the adjacent write number N_A(TRN) for each track.
The track profile weights are obtained for a case with adjacent writes (TPW1) and without adjacent writes (TPW2). TPW1 and TPW2 (collectively denoted as TPW) are each acquired using the write number thresholds TH_W1(TRN) and TH_W2(TRN) per track as in
TPW1(TRN)=TH_W1/TH_W1(TRN)
TPW2(TRN)=TH_W2/TH_W2(TRN)
TPW indicates the weight for the number of writes by side erase, and the track profile weight table is stored in a non-volatile memory 90, for example, in advance, and an adjacent write number N_A(TRN) of data with respect to peripheral tracks is used for count.
HDC 50 receives a write command (write request) of data to track TR(TRN) of track number TRN from a host 2 (Step S151). MPU 60 counts write number N(n) of peripheral tracks TR(n) of the track TR(TRN) in steps S153 to S156, where n indicates TRN-n1 to TRN-n2 (note that n1 and n2 are integers equal to or greater than 1), which are inward and outward peripheral track number with respect to track TR(TRN) where the track TR(TRN) is set as the center track.
The counter 62 counts the number of adjacent writes N_A(n) (Step S153). In step S153, the counter 62 obtains weight TPW(n) of a target peripheral track TR(n) from the track profile weight table and counts as follows such that it is increased by TPW.
N_A(n)=N_A(n)+TPW(n)
N_A(n)=N_A(n)+TPW1(n) (when track weight TPW1 is used)
N_A(n)=N_A(n)+TPW2(n) (when track weight TPW2 is used)
The refresh processor 63 compares a preset threshold TH_WA(n) with N_A(n) (Step S154). TH_WA(n) may be a threshold set for each track TR(n) or a constant threshold regardless of n.
If N_A(n)>TH_WA(n), data of track TR(n) are refreshed (Yes in Step S154, Step S155). If N_A(n)<TH_WA(n), the process is performed from step S153 with respect to the next track TR(n) (No in Step S154). In step S155, after the data in track TR(n) are refreshed, the adjacent write count N_A(n) is cleared to 0 or the like (Step S156).
The above procedure enables refresh processing by a counting process in which the influence of side erase with respect to the peripheral tracks is considered using a track profile weight table.
In the present embodiment, a method of determining a threshold TH_W used in the first embodiment based on adjacent write number is shown. In addition to the write number N(TRN) of data to track TR(TRN), adjacent write number N_A(TRN) of data with respect to adjacent tracks TR(TRN+1) and (TRN−1) of the track TR(TRN) is counted.
The counter 62 of the present embodiment includes a write counter which counts the number of writes N(TRN) per track and an adjacent write counter which counts the number of adjacent writes N_A(TRN) per track.
Steps S301 to S305 are similar to steps S101 to S105 of
In step S321, if a write request to tracks TR(TRN−1) and TR(TRN+1) which are adjacent tracks to the track TR(TRN) from the host 2 (YES in this step) is received, the HDC 50 counts the adjacent write number N_A(TRN) of track TR(TRN) (Step S322). For example, if TRN=0, the counter 62 counts the adjacent write number N_A(TRN) using the track profile weight table of
If written to adjacent track TR(TRN−1):
N_A(0)=NA(0)+TPW(1).
If written to adjacent track TR(TRN+1):
N_A(0)=NA(0)+TPW(−1).
That is, in step S322, if a track (in this case, TR(TRN+1) or TR(TRN−1)) is written, the track profile weight table is used to count the number of adjacent write number N_A(TRN) of TR(TRN) which is an adjacent track.
The number of adjacent write N_A(TRN) is compared with a preset threshold TH_WA, and if N_A(TRN)>TH_WA (Yes in Step S323), the threshold TH_W=TH_W1 (Step S324), and if N_A(TRN) is equal to or less than TH_WA (No in Step S323), the value TH_W=TH_W2 (Step S325). TH_W1 and TH_W2 are write number thresholds as the minimum value acquired in step S213 of
N(TRN) is compared with TH_W, and if N(TRN)>TH_W (Yes in Step S326), data of adjacent tracks TR(TRN−1) and TR(TRN+1) of track TR(TRN) are refreshed (Step S327), and the adjacent write number N_A(TRN) is cleared to 0 or the like (Step S328). Furthermore, the threshold TH_W set in steps S324 or S325 is also used for comparison of write number N(TRN) of track TR(TRN) to TH_W in step S303.
The present embodiment enables the refresh process using threshold obtained with respect to the write number N(TRN) in consideration of adjacent write number N_A of adjacent tracks.
(Variation)
In this variation, an example of assigning BER measuring sectors to five sector areas is shown.
In the first embodiment, an example where three sector areas of
According to at least one of the aforementioned embodiments, a side erase measuring method and a refresh process method, which are to improve the reliability of data can be achieved.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2022-010989 | Jan 2022 | JP | national |