Claims
- 1. A sigma-delta digital to analog converter (DAC), comprising:
a digital sigma-delta modulator to receive a digital input signal and produce a quantized digital signal therefrom; a decimation filter to receive the quantized digital signal and produce a decimated digital signal therefrom; and a multi-bit digital to converter (DAC) to receive the decimated digital signal and produce an analog output signal therefrom, the analog output signal being representative of the digital input signal.
- 2. The sigma-delta DAC of claim 1, wherein:
the digital sigma-delta modulator comprises a 2-level quantizer; and the quantized digital signal comprises a single-bit digital signal.
- 3. The sigma-delta DAC of claim 1, wherein:
the digital sigma-delta modulator comprises a p-level quantizer, where p is an integer greater than 2; and the quantized digital signal comprises a multi-bit digital signal.
- 4. The sigma-delta DAC of claim 1, wherein the decimation filter comprises:
a multi-tap finite impulse response (FIR) filter that filters the quantized digital signal to produce a filtered signal including a sequence of sample values, each sample value comprising a plurality of bits; and a decimator to produce the decimated digital signal based on the sequence of sample values of the filtered signal.
- 5. The sigma-delta DAC of claim 4, wherein:
the decimator discards one of every two sample values in the sequence of sample values of the filtered signal to produce the decimated digital signal, the decimated digital signal having a sample frequency that is one half of a sample frequency of the filtered signal.
- 6. The sigma-delta DAC of claim 5, wherein:
the multi-tap FIR filter comprises a 3-tap digital FIR filter.
- 7. The sigma-delta DAC of claim 1, wherein:
the multi-bit DAC includes k elements to be driven by a k-bit digital signal and produce k analog values therefrom; the k-bit digital signal is representative of the decimated digital signal; and a sum of the analog values from the k elements is representative of the digital input signal.
- 8. The sigma-delta DAC of claim 7, wherein each of the k elements is a current source that produces a respective one of the k analog values, each of the k analog values being a current.
- 9. The sigma-delta DAC of claim 7, wherein each of the k elements is a capacitor that produces a respective one of the k analog values, each of the k analog values being a charge.
- 10. The sigma-delta DAC of claim 7, wherein each of the k elements is a resistor that produces a respective one of the k analog values, each of the k analog values being a current.
- 11. The sigma-delta DAC of claim 7, wherein the muti-bit DAC (212) is calibrated.
- 12. The sigma-delta DAC of claim 7, wherein the k-bit digital signal is the decimated digital signal.
- 13. The sigma-delta DAC of claim 12, wherein:
the decimated digital signal is a binary signal; and wherein the k elements of the multi-bit DAC are binary weighted elements.
- 14. The sigma-delta DAC of claim 7, wherein the multi-bit DAC includes:
a coder to receive the decimated digital signal and produce the k-bit digital signal therefrom.
- 15. The sigma-delta DAC of claim 14, wherein:
the decimated digital signal is an n-bit signal, and the coder receives the n-bit decimated digital signal and produces the k-bit digital signal therefrom, where k does not equal n.
- 16. The sigma-delta DAC of claim 15, wherein:
the n-bit decimated digital signal is a binary signal, and the coder is a binary to thermometer coder that converts the n-bit binary decimated digital signal to the k-bit digital signal, the k-bit digital signal being a thermometer coded signal.
- 17. The sigma-delta DAC of claim 7, wherein the multi-bit DAC includes:
a mismatch shaping network to receive the decimated digital signal and produce the k-bit digital signal therefrom, the k-bit digital signal being a shuffled signal.
- 18. The sigma-delta DAC of claim 7, wherein the multi-bit DAC includes:
a coder to receive the decimated digital signal and produces a coded signal therefrom; and a mismatch shaping network to receive the coded signal and produce the k-bit digital signal therefrom, the k-bit digital signal being a shuffled signal.
- 19. The sigma-delta DAC of claim 18, wherein each of the k elements are substantially equally weighted.
- 20. The sigma-delta DAC of claim 1, wherein the multi-bit DAC includes:
an N-tap delay line including N multi-bit delay elements; and N multi-bit sub-DACs, where N is greater than one, wherein a first of the N multi-bit delay elements receives a multi-bit digital signal representative of the decimated digital signal and produces a delayed multi-bit output signal therefrom, and each of the other N multi-bit delay elements receives a delayed multi-bit output signal from an immediately preceding one of the N multi-bit delay elements and produces a respective delayed multi-bit output signal therefrom, wherein each multi-bit sub-DAC is driven by a respective one of the delayed multi-bit output signals produced by a corresponding one the N multi-bit delay elements and produces an analog output therefrom, and wherein a sum of the analog outputs from the N multi-bit sub-DACs is representative of the digital input signal.
- 21. The sigma-delta DAC of claim 20, wherein:
each multi-bit sub-DAC includes k elements to be driven by the respective one of the delayed multi-bit output signals and produce k analog values therefrom; and a sum of the analog values from the k elements corresponds to an analog output from one of the N multi-bit sub-DACs.
- 22. The sigma-delta DAC of claim 21, wherein each of the k elements is a current source that produces one of the k analog values, each of the k analog values being a current.
- 23. The sigma-delta DAC of claim 21, wherein each of the k elements is a capacitor that produces one of the k analog values, each of the k analog values being a charge.
- 24. The sigma-delta DAC of claim 21, wherein each of the k elements is a resistor that produces one of the k analog values, each of the k analog values being a current.
- 25. The sigma-delta DAC of claim 21, wherein each k-bit sub-DAC is calibrated.
- 26. The sigma-delta DAC of claim 20, wherein the multi-bit digital signal is decimated digital signal.
- 27. The sigma-delta DAC of claim 26, wherein:
the decimated digital signal is a binary signal; and each multi-bit sub-DAC are binary weighted elements.
- 28. The sigma-delta DAC of claim 20, wherein the multi-bit DAC further includes:
a coder to receive the decimated digital signal and produce the multi-bit digital signal therefrom.
- 29. The sigma-delta DAC of claim 28, wherein:
the decimated digital signal is an n-bit signal, and the coder receives the n-bit decimated digital signal and produces the multi-bit digital signal therefrom, the multi-bit digital signal being a k-bit digital signal, where k does not equal n.
- 30. The sigma-delta DAC of claim 29, wherein:
the n-bit decimated digital signal is a binary signal, and the coder is a binary-to-thermometer coder that converts the n-bit binary decimated digital signal to the k-bit digital signal, the k-bit digital signal being a thermometer coded signal.
- 31. The sigma-delta DAC of claim 30, wherein each multi-bit sub-DAC includes k elements, each of the k elements being substantially equally weighted.
- 32. The sigma-delta DAC of claim 20, wherein the multi-bit DAC further includes:
a mismatch shaping network to receive the decimated digital signal and produce the multi-bit digital signal therefrom, the multi-bit digital signal being a k-bit shuffled digital signal.
- 33. The sigma-delta DAC of claim 32, wherein each multi-bit sub-DAC includes k elements, each of the k elements being substantially equally weighted.
- 34. The sigma-delta DAC of claim 20, wherein the multi-bit DAC further includes:
a coder to receive the decimated digital signal and produces a coded signal therefrom; and a mismatch shaping network to receive the coded signal and produce a k-bit shuffled digital signal therefrom, wherein the k-bit shuffled digital signal is the multi-bit digital signal received by the first of the N multi-bit delay elements.
- 35. The sigma-delta DAC of claim 32, wherein each multi-bit sub-DAC includes k elements, each of the k elements being substantially equally weighted.
- 36. The sigma-delta DAC of claim 20, wherein each multi-bit sub-DAC includes:
a coder to receive a respective one of the delayed multi-bit output signals and produce a respective coded signal therefrom; and k elements to be driven by the coded signal and produce k analog values therefrom, wherein a sum of the analog values from the k elements corresponds to an analog output from one of the N k-bit sub-DACs.
- 37. The sigma-delta DAC of claim 36, wherein:
each delayed multi-bit output signal is an n-bit signal, and the coder of each multi-bit sub-DAC receives a respective n-bit delayed multi-bit output signal and produces a k-bit digital signal therefrom, wherein the k-bit digital signal is the coded signal produced by the coder.
- 38. The sigma-delta DAC of claim 37, wherein:
each coder is a binary-to-thermometer coder that converts a respective n-bit delayed muti-bit output signal to the k-bit digital signal, the k-bit digital signal being a thermometer coded signal.
- 39. The sigma-delta DAC of claim 20, wherein each multi-bit sub-DAC further includes:
a mismatch shaping network to receive a respective one of the delayed multi-bit output signals and produce a respective k-bit shuffled signal therefrom; and k elements to be driven by the k-bit shuffled signal to produce k analog values therefrom, wherein a sum of the analog values from the k elements corresponds to an analog output from one of the N multi-bit sub-DACs.
- 40. The sigma-delta DAC of claim 20, wherein each multi-bit sub-DAC further includes:
a coder to receive a respective one of the delayed multi-bit output signals and produce a respective coded signal therefrom; and a mismatch shaping network to receive the coded signals and produce a respective k-bit shuffled signal therefrom; and k elements to be driven by the k-bit shuffled signal to produce k analog values therefrom, wherein a sum of the analog values from the k elements corresponds to an analog output from one of the N multi-bit sub-DACs.
- 41. The sigma-delta DAC of claim 40, wherein each of the k elements are substantially equally weighted.
- 42. A method for converting a digital signal to an analog signal, comprising:
(a) producing a quantized digital signal based on a digital input signal; (b) producing a decimated digital signal based on the quantized digital signal (c) producing an analog output signal based on the decimated digital signal, the analog output signal being representative of the digital input signal.
- 43. The method of claim 42, wherein step (a) comprises producing a single-bit quantized digital signal.
- 44. The method of claim 42, wherein step (a) comprises producing a multi-bit quantized digital signal.
- 45. The method of claim 42, wherein step (b) comprises:
(b.1) filtering the quantized digital signal to produce a filtered signal including a sequence of sample values, each sample value comprising a plurality of bits; and (b.2) produce the decimated digital signal based on the sequence of sample values of the filtered signal.
- 46. The method of claim 45, wherein step (b.2) comprises discarding one of every two sample values in the sequence of sample values of the filtered signal to produce the decimated digital signal, the decimated digital signal having a sample frequency that is one half of a sample frequency of the filtered signal.
- 47. The method of claim 42, wherein step (c) comprises:
(c.1) driving k elements with a k-bit digital signal to produce k analog values therefrom, the k-bit digital signal being representative of the decimated digital signal; and (c.2) summing the analog values from the k elements to produce the analog output signal.
- 48. The method of claim 47, wherein the k-bit digital signal is the decimated digital signal, and wherein step (c.1) comprises driving the k elements with the decimated digital signal.
- 49. The method of claim 47, wherein the decimated digital signal is a binary signal, and wherein step (c.1) comprises driving k binary weighted elements.
- 50. The method of claim 47, further comprising, prior to step (c.1), the step of coding the decimated digital signal to produce the k-bit digital signal therefrom.
- 51. The method of claim 50, wherein the decimated digital signal is an n-bit signal, and wherein the step of coding comprises producing the k-bit digital signal based on the n-bit decimated digital signal, where k does not equal n.
- 52. A sigma-delta digital to analog converter (DAC), comprising:
quantizing means for producing a quantized digital signal based on a digital input signal; decimating means for producing a decimated digital signal based on the quantized digital signal; outputting means for producing an analog output signal based on the decimated digital signal, the analog output signal being representative of the digital input signal.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The application claims priority to U.S. Provisional Patent Application No. 60/231,825, entitled “A Multi-Bit Sigma-delta Digital to Analog Converter For Use in an Analog Front End in a DOCSIS Compatible Cable Modem,” filed Sep. 11, 2000, and U.S. Provisional Patent Application No. 60/232,157, entitled “Multi-Bit Sigma-delta Digital to Analog Converter,” filed Sep. 11, 2000, both of which are assigned to the assignee of the present invention, and both of which are incorporated herein by reference in their entirety.
Continuations (1)
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Number |
Date |
Country |
Parent |
09949814 |
Sep 2001 |
US |
Child |
10379593 |
Mar 2003 |
US |