Sigma-delta modulation with minimized noise and fractional-N phase-locked loop including the same

Abstract

A sigma-delta modulator (SDM) includes a delay circuit and an operation circuit. The delay circuit generates multiple clock signals with different delays. The operation circuit includes a plurality of operation stages that operate with timing according to all of the clock signals for high-order sigma-delta modulation. Thus, noise may be dispersed for minimizing noise coupling. The SDM is used to particular advantage within a fractional-N phase-locked loop.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent when described in detailed exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional fractional-N phase-locked loop (PLL);

FIG. 2 is a timing diagram illustrating noise coupling in the PLL of FIG. 1, according to the prior art;

FIG. 3 is a block diagram of a fourth-order sigma-delta modulator (SDM) of an interpolative architecture;

FIG. 4 is a block diagram of a fourth-order sigma-delta modulator (SDM) with reduced noise, according to an example embodiment of the present invention;

FIG. 5 is a block diagram of a fractional-N PLL including the SDM of FIG. 4, according to an example embodiment of the present invention;

FIG. 6 is a timing diagram illustrating reduced noise in the PLL of FIG. 5; and

FIG. 7 is a graph comparing respective in-band noise of the PLL in FIG. 1 and the PLL in FIG. 5.

Claims

1. A sigma-delta modulator (SDM) comprising: a delay circuit that generates a plurality of clock signals, each clock signal having a respective unique delay from a reference clock signal; andan operation circuit including a plurality of operation stages that operate with timing according to all of the clock signals for high-order sigma-delta modulation.

2. The SDM of claim 1, wherein the operation circuit includes a plurality of first-order sigma-delta modulators coupled in series, and wherein each of the first-order sigma-delta modulators includes a respective accumulator timed with a respective unique one of the clock signals.

3. The SDM of claim 2, wherein the respective clock signal for a first-order sigma-delta modulator disposed more toward an output of the SDM has less delay.

4. The SDM of claim 3, wherein the respective clock signal for a last first-order sigma-delta modulator is the reference clock signal.

5. The SDM of claim 2, further comprising: a latch coupled to a last first-order sigma-delta modulator, wherein the latch operates according to one of the clock signals having a maximum delay.

6. The SDM of claim 4, further comprising: a quantizer that quantizes an output of the latch to generate a quantized output that is fed-back to each of the first-order sigma-delta modulators.

7. The SDM of claim 2, wherein the first-order sigma-delta modulators are each configured with an interpolative architecture.

8. The SDM of claim 1, wherein a maximum delay of the respective delays is smaller than a period of the reference clock signal.

9. A method of performing high-order sigma-delta modulation, comprising: generating a plurality of clock signals, each clock signal having a respective unique delay from a reference clock signal; andoperating a plurality of operation stages that together perform high-order sigma-delta modulation with timing according to all of the clock signals.

10. The method of claim 9, wherein the operation circuit includes a plurality of first-order sigma-delta modulators coupled in series, and wherein each of the first-order sigma-delta modulators includes a respective accumulator timed with a respective unique one of the clock signals.

11. The method of claim 10, wherein the respective clock signal for a first-order sigma-delta modulator disposed more toward an output of the SDM has less delay, and wherein the respective clock signal for a last first-order sigma-delta modulator is the reference clock signal.

12. The method of claim 10, further comprising: latching an output of a last first-order sigma-delta modulator with timing according to one of the clock signals having a maximum delay; andquantizing the latched output to generate a quantized output that is fed-back to each of the first-order sigma-delta modulators.

13. A fractional-N phase-locked loop (PLL) comprising: a phase-frequency detector (PFD) that determines a phase difference between a reference frequency signal and a division frequency signal obtained by frequency division of an output frequency signal of the PLL by a division ratio;a voltage-controlled oscillator (VCO) that generates the output frequency signal depending on said phase difference; anda sigma-delta modulator (SDM) for generating the division ratio from a fractional input, the SDM including a plurality of operation stages that operate with timing according to a plurality of clock signals having different delays for high-order sigma-delta modulation.

14. The fractional-N PLL of claim 13, wherein the SDM further includes: a delay circuit that generates the plurality of clock signals, each clock signal having a respective unique delay from a reference clock signal.

15. The fractional-N PLL of claim 14, wherein the division frequency signal is the reference clock signal.

16. The fractional-N PLL of claim 15, wherein the operation stages include a plurality of first-order sigma-delta modulators coupled in series, and wherein each of the first-order sigma-delta modulators includes a respective accumulator timed with a respective unique one of the clock signals.

17. The fractional-N PLL of claim 16, wherein the respective clock signal for a first-order sigma-delta modulator disposed more toward an output of the SDM has less delay, and wherein the respective clock signal for a last first-order sigma-delta modulator is the reference clock signal.

18. The fractional-N PLL of claim 16, wherein the SDM further includes: a latch coupled to a last first-order sigma-delta modulator, wherein the latch operates according to one of the clock signals having a maximum delay; anda quantizer that quantizes an output of the latch to generate a quantized output that is fed-back to each of the first-order sigma-delta modulators.

19. The fractional-N PLL of claim 16, wherein the first-order sigma-delta modulators are each configured with an interpolative architecture.

20. The fractional-N PLL of claim 14, wherein a maximum delay of the respective delays is smaller than a period of the reference clock signal.