Sigma-delta modulator having reduced delay from input to output

Abstract

Described herein is a fourth-order sigma-delta modulator which utilizes two second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators having a 1/2 sample period delay from input to output. A second-order sigma-delta modulator, including such integrators, exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator, which includes two such second-order sigma-delta modulators, exhibits a delay of two sample periods from input to output. The present sigma-delta modulator can be fabricated using switched capacitor circuitry to form an A/D convertor, and in another embodiment can be used as a digital noise shaper for a D/C convertor circuit. The 1/2 unit delay is implemented without requiring two D-flip flops in series, which results in a design and manufacturing advantage.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to high resolution analog-to-digital and digital-to-analog converters, and in particular, to oversampled, noise shaping analog-to-digital and digital-to-analog converters.

2. Brief Description of the Related Technology and Prior Art

The use of sigma-delta modulators in analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits is increasing. It is well known in the art that so-called higher order sigma-delta modulators have an inherently higher signal-to-noise ratio than lower ordered sigma-delta modulators. For many practical applications, fourth-order sigma-delta modulators have become the higher-order modulator of choice because they strike an appropriate balance between analog circuit complexity and accompanying digital filtering complexity. Various fourth-order sigma-delta modulators for A/D circuits are described in the following applications assigned to the common assignee of the present invention: application Ser. No. 08/112,610, filed Aug. 26, 1993, entitled "Fourth-Order Cascaded Sigma-Delta Modulator;" application Ser. No. 08/147,062, filed Nov. 3, 1993, entitled "Fourth-Order Cascaded Sigma-Delta Modulator;" and application Ser. No. 08/171,091, filed Dec. 21, 1993, entitled "Fourth-Order Cascaded Sigma-Delta Modulator." Another fourth-order sigma-delta modulator is described by Karema, et al, in U.S. Pat. No. 5,061,928. The aforementioned applications describe sigma-delta modulators created by connecting two, second-order sigma-delta modulators, each such modulator being characterized as having two associated unit delays from input to output. In each of the above applications, a unique post-quantization network combines the output of the two, second-order sigma-delta modulators in a manner such that a single modulated multi-bit data stream, with fourth-order shaping, results. The modulators in all of the examples given above are characterized as having four unit delays from input to final output.

A need has developed for a fourth-order sigma-delta modulator with fewer than four unit delays from input to output in order to overcome disadvantages associated with those fourth-order modulators having four unit delays from input to output. Prior art fourth-order sigma-delta modulators implemented as A/D converters suffer from increased operational amplifier and post-quantization network complexity. Additionally, when such sigmadelta modulators are used in the feedback loop of such circuits as echo cancelers, stability may be difficult to obtain due to the amount of delay from input to output through the sigma-delta modulator.

The sigma-delta modulator of FIG. 1 is an example of a fourth-order sigma-delta modulator which is formed by connecting two, second-order sigma-delta modulators. This is similar to the fourth-order modulator described in U.S. Pat. No. 5,061,928 by Karema, et al. This modulator is characterized as a cascade of two second-order modulators. These second-order modulators are characterized as including two integrators each of which can be characterized as having the following transfer function:

H(z)=z.sup.-1 /(1-z.sup.-1)

As can be seen in the above equation, there is a single unit delay in such an integrator due to the z.sup.-1 term in the numerator. Additionally, such second-order modulators are also characterized as having a quantizer, which typically is used to quantize only the sign of the signal presented at its input. This is commonly modeled as a summing node where one input is the input to the quantizer (Q) and the other input is a noise source (E) which represents the quantization noise of the quantizer. Such a model is shown in FIG. 1 as Q.sub.1 and Q.sub.2. The overall transfer function of such a second-order modulator is typically given by the following equation:

y(z)=z.sup.-2 x(z)+E(z)(1-z.sup.-1).sup.2 where y(z) is the output of the modulator, x(z) is the sampled input to the modulator, and E(z) is the quantization noise of the quantizer within the modulator.

When two such second-order modulators are connected together as shown in FIG. 1, the transfer function at output y1(z) can be characterized by the following equation:

y.sub.1 (z)=z.sup.-2 x(z)+E.sub.1 (z)(1-z.sup.-1).sup.2 where x(z) is the sampled input to the modulator and E.sub.1 (z) is the quantization noise of quantizer Q.sub.1. Output y.sub.2 (z) can be characterized by the following equation: y.sub.2 (z)=z.sup.-2 E.sub.1 (z)+KE.sub.2 (z)(1-z.sup.-1).sup.2 where E.sub.1 (z) is the quantization noise due to quantizer Q.sub.1, K is a constant that is frequently used as a scaling factor for the connection between the first and second modulator, and E.sub.2 (z) is the quantization noise due to the quantizer Q.sub.1.

The two modulator outputs, y.sub.1 (z) and y.sub.2 (z) are typically combined using a post-quantization network which results in a final modulator output y.sub.out (z). An appropriate post-quantization network for use with the circuit of FIG. 1 is shown in FIG. 2. Such a circuit along with the two, second-order sigma-delta modulators shown in FIG. 1 will result in an overall fourth-order sigma-delta modulator which may be characterized by the following equation:

y.sub.out (z)=z.sup.-4 x(z)+KE.sub.2 (z)(1-z.sup.-1).sup.4 Essentially, the post-quantization circuit of FIG. 2 removes the quantization noise E.sub.1 (z) due to quantizer Q.sub.1. It also results in an overall fourth-order high pass filtering function on the quantization noise E.sub.2 (z) due to quantizer Q.sub.2. As can be seen in the above equation, such a modulator has an overall constant group delay of four sample periods due to the z.sup.-4 term in front of the x(z) term.

In application Ser. No. 08/147,062, described previously, a fourth-order sigma-delta modulator is formed by connecting two, second-order sigma-delta modulators together such that only the input of the first quantizer is fed to the second, second-order sigma-delta modulator. The output of each quantizer for each second-order sigma-delta modulator is then fed to a post-quantization network which removes the quantization noise of the first, second-order sigma-delta modulator and shapes the quantization noise of the second, second-order sigma-delta modulator with a fourth-order high pass filter function. Such a sigma delta modulator is shown in FIGS. 3 and 4 and can be characterized by the same equation that characterizes the operation of the fourth-order sigma-delta modulator described by Karema, et al. That is, the output of the fourth-order sigma-delta modulator described in the aforementioned application also has a constant group delay of four sample periods.

It is an object of the present invention to provide a fourth-order sigma-delta modulator which has high resolution, but with an overall constant group delay of two sample periods. This is to be accomplished by connecting together two, second-order sigma-delta modulators, each being characterized as having an overall constant group delay of one sample period. An example of a prior art second-order modulator having unit delays less than one is described in the IEEE Journal of Solid State Circuits, Vol. 25, no. 4, Aug. 1990, pp. 979-986, in the article entitled "The Implementation of Digital Echo Cancellation in Codecs," by Friedman, et al. Friedman describes a second-order modulator characterized as having integrators with 1/2 unit delays from input to output. Furthermore, the second-order sigma-delta modulator of Friedman is characterized as requiring two flip-flops to perform delay functions in the feedback of the modulator to obtain the desired transfer function. Such a second-order sigma-delta modulator is shown in FIG. 5.

It is, therefore, a further object of the present invention to describe a second-order sigma-delta modulator which does not require two flip-flops in the feedback of the sigma-delta modulator, thus reducing the manufacturing cost of such a sigma-delta modulator.

It is a further object of the present invention to utilize two such second-order sigma-delta modulators, which are to be connected together, to form a portion of a fourth-order sigma-delta modulator.

It is still a further object of the present invention to connect two such second-order modulators to a post-quantization network to form an overall fourth-order sigma-delta modulator with a total of two unit sample delays.

It is yet another object of the present invention to provide a sigmadelta modulator which can be fabricated using switched capacitor circuitry in such a fashion as to form an A/D converter.

It is still another object of the present invention to provide a sigmadelta modulator which can be used as a digital noise shaper for a D/A converter.

SUMMARY OF THE INVENTION

The fourth-order sigma-delta modulator of the present invention utilizes two, second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators with a 1/2 sample period delay from input to output. A second-order sigma-delta modulator including such integrators exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator which includes two such second-order sigma-delta modulators exhibits a delay of two sample periods from input to output.

In a preferred embodiment, a fourth-order analog-to-digital converter circuit is described by combining two such second-order sigma-delta modulators which include the characteristic that all capacitors which are connected to the output of each op amp within the sigma-delta modulator would be charged on the same clock phase. Because of this characteristic, glitches between clock phases are avoided and performance of the analog-todigital converter is improved.

In another embodiment, the two second-order sigma-delta modulators, and a portion of the post-quantization network, are constructed as a digital circuit that can be used as a digital noise shaper for a D/A converter. The resultant outputs of the post-quantization network may then be input into a plurality of D/A converters whose outputs are summed to form a single analog output.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a fourth-order sigma-delta modulator of the prior art;

FIG. 2 is a block diagram of a post-quantization circuit of the prior art;

FIG. 3 is a block diagram of a fourth-order sigma-delta system of the prior art;

FIG. 4 is a block diagram of a post-quantization circuit of the prior art;

FIG. 5 is a block diagram of a second-order sigma-delta modulator of the prior art;

FIG. 6 is a block diagram of a second-order sigma-delta modulator of the present invention;

FIG. 7 is an embodiment of two integrators, each having one-half unit delay;

FIG. 8 is an embodiment of two integrators, each having one unit delay;

FIG. 9 is a timing diagram of the timing signals, .PHI..sub.1 and .PHI..sub.2, used with the switching capacitors of the present invention;

FIG. 10 is a block diagram of a fourth-order sigma-delta modulator of the present invention;

FIG. 11 is a block diagram of a post-quantization network of the present invention;

FIG. 12 is a block diagram of a second-order sigma-delta modulator of the present invention;

FIG. 13 is a block diagram of a fourth-order sigma-delta modulator of the present invention;

FIG. 14 is an embodiment of a fourth-order sigma-delta modulator of the present invention, which utilizes summing integrators;

FIG. 15 is a timing diagram showing the relationship between the switch capacitor timing signals, .PHI..sub.1 and .PHI..sub.2, and the outputs y1a(z), y1b(z), y2a(z), and y2b(z), and of FIG. 14 of the present invention;

FIG. 16 shows an alternative embodiment of an integration stage of a sigma-delta modulator of the present invention;

FIG. 17 illustrates an additional embodiment of an integration stage of a sigma-delta/modulator of the present invention;

FIG. 18 is a timing diagram showing the timing of the switches in the sigma-delta embodiment illustrated in FIG. 19;

FIG. 19 is an embodiment of an integration stage of a sigma-delta modulator of the present invention;

FIG. 20 is a graphic illustration of a plot of simulated signal noise plus distortion ratio levels (SNDR), with an oversampling ratio of 64, of a sigma-delta modulator of the present invention; and

FIG. 21 is a post-quantization network for a D/A modulator of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 6 is a functional block diagram of a second-order sigma-delta modulator 5 of the present invention. Integrators 12 and 14, each having a 1/2 unit delay with the following transfer function, are utilized:

H.sub.1 (z)=z.sup.-1/2 /(1-z.sup.-1) A more common form of integrator is characterized by the following transfer function: H.sub.2 (z)=z.sup.-1 /(1-z.sup.-1)

FIG. 7 schematically depicts a single-ended implementation of two integrators in series with half unit delays in each integrator. FIG. 8 is a single-ended implementation of two integrators in series with unit delays in each integrator. In FIGS. 7 and 8, .PHI..sub.1 and .PHI..sub.2 are two-phase non-overlapping clocks and are characterized such that neither clock is at a logic `1` during the same instant in time. An example of such clocks is shown in FIG. 9. When .PHI..sub.1 is at a logic `1` any switch which is denoted as being controlled by .PHI..sub.1 is closed. Such a switch is open at all other times. Likewise, when .PHI..sub.2 is at a logic `1` any switch is denoted as being controlled by .PHI..sub.2 is closed. Such a switch is open at all other times.

In FIG. 8, charge is added to capacitor C.sub.2 while .PHI..sub.2 is at a logic `1`. Once .PHI..sub.2 becomes a logic `0` and .PHI..sub.1 becomes a logic `1`, the op amp 16a must charge capacitor C.sub.3 from 0 volts to the voltage that the output of op amp 16a had achieved during the time .PHI..sub.2 was a logic `1`. Since practical implementations of op amps have a finite output impedance, gain, and bandwidth, the output of op amp 16a will glitch at the beginning of the time during which .PHI..sub.1 is a logic `1`. This is undesirable and may lead to reduced performance if such a structure is used in a sigma-delta modulator which performs an analog-to-digital conversion.

In FIG. 7, capacitor 24 and capacitor 22 are charging on the same clock phase. Because of this, op amp output node 28 does not glitch between clock phases. Such a structure may have the added benefit of increased performance when used in a sigma-delta modulator which is configured as an A/D converter circuit.

For reasons previously stated, it is desirable to have a second-order sigma-delta modulator circuit with only one unit delay. Such a modulator, as shown in FIG. 6, would have the desired transfer function given by the following equation:

y(z)=z.sup.-1 x(z)+E(z)(1-z.sup.-1).sup.2 Equation A

In Equation A, E(z) represents the quantization noise of a quantizer Q.sub.1 modelled as a summing node 30 in FIG. 6, where y(z) represents the output signal 6 of modulator 5 and x(z) represents a sampled analog input signal 7.

Referring to FIG. 6, y(z) can be represented by the following equation

y(z)=E(z)+C(z) Equation 1

Solving the block diagram given in FIG. 6 for C(z) yields the following equation:

C(z)={z.sup.-1 x(z)-y(z)[z.sup.-(Q+1) +2z.sup.-(P+1/2) -2z.sup.-(P+3/2) ]/(1-z.sup.-1).sup.2 } Equation 2

Now, after substituting C(z) in Equation 2 into Equation 1 and solving algebraically, the following equation results:

y(z)(1-z.sup.-1).sup.2 =E(1-z.sup.-1).sup.2 +z.sup.-1 x(z)-y(z)[z.sup.-(Q+1) +2z.sup.-(P+1/2) -2z.sup.-(P+3/2) ]

The above equation can be algebraically rearranged into the following equation:

y(z)[1-2z.sup.-1 +z.sup.-2 +z.sup.-(Q+1) +2z.sup.-(P+1/2) -2z.sup.-(P+3/2) ]=z.sup.-1 x(z)+E(z)(1-z.sup.-1).sup.2

The right hand side of the equation above is identical to the right hand side of Equation A, supra. Algebraically, this is true only if the following identity is true:

1-2z.sup.-1 +z.sup.-2 +z.sup.-(Q+1) +2z.sup.(P+1/2) -2z.sup.-(P+3/2) =1

Rearranging the above equation yields:

-2z.sup.-1 +z.sup.-2 +z.sup.-(Q+1) +2z.sup.-(P+1/2) -2z.sup.-(P+3/2) =0

With Q=1 and P=1/2, the above equation is correctly resolved. Thus, the desired equation, y(z)=z.sup.-1 x(z)+E(z)(1-z.sup.-1).sup.2, is the transfer function for the block diagram shown in FIG. 6 when Q=1 and P=1/2. In other words, in order to satisfy the desired transfer function, there would be a delay of 1/2 of a sample period from the output of the quantizer Q.sub.1 to the input of the gain of 2 block 8. Also, there would be a full sample period delay from the output of the quantizer Q.sub.1 to the input of summing node 10.

FIG. 10 illustrates the functional block diagram implementation of the current invention illustrated by a fourth-order sigma-delta modulator 9 formed by connecting together two, second-order sigma-delta modulators 11 and 13, each including 1/2 unit delay integrators associated therewith. The output signal 15, y.sub.1 (z), in FIG. 10 is represented by the following equation:

y.sub.1 (z)=z.sup.-1 x(z)+E.sub.1 (z)(1-z.sup.-1).sup.2 The equation for output signal 17, y.sub.2 (z), can be represented by the following equation: y.sub.2 (z)=(1/ C)z.sup.-1 y.sub.1 (z)-(1/C)z.sup.-1 E.sub.1 (z)

The term E.sub.1 (z) is removed in equations for y.sub.1 (z) and y.sub.2 (z) so the following desired fourth-order output equation of the fourth-order modulator, as shown in FIG. 10, is achieved.

y.sub.out (z)=z.sup.-2 x(z)+CE.sub.2 (z)(1-z.sup.-1).sup.4 To accomplish this, the following steps occur: Firstly, the y.sub.2 (z) equation is multiplied by C, C representing a constant, which yields y.sub.3 (z) as follows: y.sub.3 (z)=z.sup.-1 y1(z)-z.sup.-1 E.sub.1 (z)+CE.sub.2 (z)(1-z.sup.-1).sup.2

Secondly, the term z.sup.-1 y.sub.1 (z) is subtracted from y.sub.3 (z) yielding the equation y.sub.4 (z) as follows:

y.sub.4 (z)=-z.sup.-1 E.sub.1 (z)+CE.sub.2 (z)(1-z.sup.-1).sup.2 Next, y.sub.4 (z) is multiplied by the term (1-z.sup.-1).sup.2 yielding the equation y.sub.5 (z) as follows: y.sub.5 (z)=-z.sup.-1 (1-z.sup.-1).sup.2 E.sub.1 (z)+C(1-z.sup.-1).sup.4 E.sub.2 (z) Equation y.sub.1 (z) is then multiplied by the term z.sup.-1 which yields equation y.sub.6, as follows: y.sub.6 (z)=z.sup.-2 x(z)+z.sup.-1 E.sub.1 (z)(1-z.sup.-1).sup.2

Finally, equation y.sub.5 (z) is added to equation y.sub.6 (z) yielding the desired equation for y.sub.out (z), as follows:

y.sub.out (z)=z.sup.-2 x(z)+CE.sub.2 (z)(1-z.sup.-1).sup.4

FIG. 11 illustrates the post-quantization network 23 which corresponds to the aforementioned equations that results in the above equation for y.sub.out (z), 21. Output signals 15 and 17, y.sub.1 (z) and y.sub.2 (z) from FIG. 10 are connected to y.sub.1 (z) and y.sub.2 (z), respectively, in FIG. 11.

Thus, in an A/D converter application, the output signal 21, y.sub.out (z), in FIG. 11 is available as an input signal to additional circuitry, such as a decimator filter.

FIG. 12 illustrates how scaling is employed in the design of the second-order modulator 25 to prevent the integrators 36 and 38 from clipping, while not affecting the transfer function of the second-order sigma-delta modulator 25. The scaling is accomplished by using constants K.sub.1 and K.sub.2. Thus, the integrator in FIG. 12, is shown within the dashed area 36, which includes summing node 10, 1/2 unit delay integrator block 12 and a scaling factor 1/K.sub.1. Likewise, the other integrator in FIG. 12, shown within the dashed area 38, includes summing node 18, 1/2 unit delay integrator block 14, and constants K.sub.1, 1/K.sub.2 and 2. Since 1/K.sub.1 in integrator 36 is compensated by factor K.sub.1 in integrator 38, no net change occurs in the transfer function due to scaling factor 1/K.sub.1. The quantizer Q.sub.1, denoted by summing node 19, with noise E.sub.1 (z) as an input, is typically a comparator which quantizes only the sign of the signal input to it. Thus, the term 1/K.sub.2 can be of arbitrary size and will not affect the transfer function of the second-order sigma-delta modulator 25.

When two second-order sigma delta modulator sections 29 and 31, as shown in FIG. 13, are connected together to form a fourth-order modulator, the term 1/K.sub.2 acts as the 1/C scaling factor shown in FIG. 10. The resulting fourth-order modulator 27 is shown in FIG. 13. The post-quantization network which combines outputs y.sub.1 (z) and y.sub.2 (z) for sigma-delta modulator 27 shown in FIG. 13 is identical to the post-quantization correction network 23 shown in FIG. 11, with the constant C in FIG. 11 being replaced by the constant K.sub.2.

FIG. 14 depicts an embodiment of the analog portion of the fourth-order sigma-delta A/D converter of the present invention. The implementation shown is a single ended configuration. If output signal CMP.sub.1 is a logic `1` and output signal CMP.sub.1 * is a logic `0`, then negative reference voltage DNEG is selected as an input to the summing integrator 40 and positive reference voltage DPOS is selected as an input to the summing integrator 41. If output signal CMP.sub.1 is a logic `0` and output signal CMP.sub.1 * is a logic `1` then reference voltage DPOS is selected as an input to the summing integrator 40 and reference voltage DNEG is selected as an input to the summing integrator 41.

If output signal CMP.sub.2 is a logic `1` and output signal CMP.sub.2 * is a logic `0` then reference voltage DNEG is selected as an input to the summing integrator 42 and reference voltage DPOS is selected as an input to the summing integrator 43. Likewise if CMP.sub.2 is a logic `0` and CMP.sub.2 * is a logic `1` then reference voltage DPOS is selected as an input to the summing integrator 42 and reference voltage DNEG is selected as an input to the summing integrator 43.

FIG. 15 is a timing diagram illustrating the timing relationships between the following signals which are shown in FIG. 14: .PHI..sub.1, .PHI..sub.2, the output y.sub.1 a(z) of integrator 40, the output y.sub.1 b(z) of integrator 41, the output y.sub.2 a(z) of integrator 42, and the output y.sub.2 b(z) of integrator 43.

The transfer function of summing integrator 40 in FIG. 14 can be represented by the following equation:

y.sub.1 a(z)=[(C.sub.1 /C.sub.3)x(z)-z.sup.-1 (C.sub.2 /C.sub.3)y.sub.1 (z)]z.sup.-1/2 /(1-z.sup.-1)

Since the output of y.sub.1 (z) is sampled on .PHI..sub.2, there is a 1/2 sample period delay in the feed-forward path of the integrator which is represented by the z.sup.-1/2 term in the above equation. The logic value of CMP.sub.1 and CMP.sub.1 * determine whether DPOS or DNEG is connected to the input A of integrator 40 in FIG. 14. Since CMP.sub.1 (which corresponds to y.sub.1 (z)) connects reference voltage DNEG to the input A of integrator 40, an inherent negation is performed on y.sub.1 (z) as it is fed into input A of integrator 40. Thus the summing integrator 40 acts to effectively calculate the scaled difference between the input signal y.sub.1 (z) and the output signal y.sub.1 (z). Also, since the actual value of y.sub.1 (z), which is used in the subtraction process and whose output is sampled during the .PHI..sub.2 clock phase is actually the output y.sub.1 (z) which was calculated at the previous .PHI..sub.2 clock phase, an inherent unit delay exists in the feedback path from y.sub.1 (z) to the input A of integrator 40. This is represented by the z.sup.-1 term before the y.sub.1 (z) term in the above equation. Since an inherent delay exists in the feedback path from y.sub.1 (z) to the input A of integrator 40, no explicit latch is required to perform this function.

The output y.sub.1 (z), which is essentially y.sub.1 b(z) that has been sampled during the .PHI..sub.2, can be represented by the following equation:

y.sub.1 (z)=[(C.sub.4 /C.sub.6)y.sub.1 a(z)-(C.sub.5 /C.sub.6)z.sup.-1/2 y.sub.1 (z)]z-1/2/(1-z.sup.-1)

There is an extra one-half sample delay in front of the y.sub.1 (z) term in the above equation which is represented by the z.sup.-1/2 term. This is because the actual value of y.sub.1 (z) which is used is the value of y.sub.1 (z) which existed during the .PHI..sub.1 cycle prior to the .PHI..sub.2 cycle during which the output y.sub.1 b(z) is sampled.

Referring to the block diagram in FIG. 12, it can be seen that the desired equation for y.sub.1 d.sub.1 (z) is as follows:

y.sub.1 d.sub.1 (z)=(1/K.sub.1)[x(z)-z.sup.-1 y.sub.2 d.sub.1 (z)]z.sup.-1/2 (1-z.sup.-1)

One can see that the above equation is of the same form as the equation for y.sub.1 a(z) given previously. In the above equation, the term 1/K.sub.1 is realized by the capacitor ratio C.sub.1 /C.sub.3 as well as the ratio C.sub.2 /C.sub.3 in FIG. 14.

Likewise, referring to FIG. 12, the desired equation for y.sub.2 d.sub.1 (z) can be represented by the following equation:

y.sub.2 d.sub.1 (z)=[(K.sub.1 /K.sub.2)y.sub.1 d(z)-(2/K.sub.2)z.sup.-1/2 y.sub.2 d.sub.1 (z)]z.sup.-1/2 /(1-z.sup.-1) This equation is of the same form given for the equation for y.sub.1 (z), given previously. In this case, the ratio K.sub.1 /K.sub.2 is realized by the capacitor ratio C.sub.4 /C.sub.6 in FIG. 14. Likewise, the term 2/K.sub.2 would be realized by the capacitor ratio C.sub.5 /C.sub.6. As explained previously in this disclosure, any effective scaling immediately before the quantizer will have no effect on the overall transfer function since a 1 bit quantizer only quantizes the sign of the signal at its input. Thus, the second-order sigma-delta modulator shown in FIG. 14, which includes integrator 40, integrator 41, and comparator 47, can be represented by the following equation: y.sub.1 (z)=z.sup.-1 x(z)+E.sub.1 (z)(1-z.sup.-1).sup.2 In the above equation, y.sub.1 (z) is the output of comparator 47, x(z) is the sampled analog input to the sigma-delta modulator and E.sub.1 (z) is the quantization noise due to comparator 47.

Using similar arguments as have been used in the foregoing discussion, appropriate equations for the second, second-order modulator shown in FIG. 14 which includes integrator 42, integrator 43, and comparator 49, can be developed. Thus, it can be seen that the two sigma-delta modulators which are shown in FIG. 14 are an appropriate practical embodiment of the two sigma-delta modulators shown in block diagram form in FIG. 10.

A preferred method of implementing the analog portion of the architecture is to utilize fully differential design techniques. Examples of differential differencing integrators, which may replace the summing integrators 40-43 shown in FIG. 14, are shown in FIGS. 16 and 17. The timing shown in FIGS. 16 and 17 is preferred where the differential differencing integrators shown therein replace summing integrators 40 and 42 in FIG. 14. When the integrators of FIGS. 16 and 17 are substituted for integrators 41 and 43 in FIG. 14, the clocks .PHI..sub.1 and .PHI..sub.2 shown within hashed area A of FIGS. 16 and 17 are reversed (i.e., .PHI..sub.1 clocks become .PHI..sub.2 and vice versa).

Other integrators have been described in the literature, including correlated-double-sampled and chopper stabilized integrators. These techniques may also be used to implement the aforementioned integrators. Three-phase clocking may also be employed which would allow both the input signal and the DPOS/DNEG signals to be double-sampled.

To reduce signal dependent charge injection and its accompanying harmonic distortion, clock phases .PHI..sub.1 and .PHI..sub.2 can be implemented as four clocks, as shown in FIG. 18. This technique is described by Kuang-Lu Lee and Robert G. Meyer, IEEE JSSC, December 1985, Vol. SC-20, No. 6, pp. 1103-1113, entitled, Low-Distortion Switched Capacitor Filter Design Techniques, incorporated herein for all purposes.

As shown in FIG. 19, utilizing the four clock technique of FIG. 18, switches controlled by S.sub.3 open slightly before switches controlled by S.sub.1 and switches controlled by S.sub.4 open slightly before switches controlled by S.sub.2. When switches controlled by S.sub.3 open, charge is injected onto capacitors C.sub.1 A and C.sub.1 B. Since switches controlled by S.sub.3 previously connected one plate of C.sub.1 A and one plate of C.sub.1 B to a reference point, the charge that is injected due to switches controlled by S.sub.1 opening is not input signal dependent. When switches controlled by S.sub.1 open, capacitors C.sub.1 A and C.sub.1 B already have one plate floating. Thus, the action of switches controlled by S.sub.1 cannot inject charge onto C.sub.1 A or C.sub.1 B. Likewise, since before opening, switches controlled by S.sub.4 were previously connected to a virtual ground node, no input signal dependent charge is injected onto capacitors C.sub.1 A, C.sub.1 B, C.sub.3 A, or C.sub.3 B. When switches controlled by S.sub.2 open, capacitors C.sub.1 A and C.sub.1 B already have one plate floating. Thus, the action of opening switches controlled by S.sub.2 cannot inject charge onto capacitors C.sub.1 A and C.sub.1 B.

FIG. 20 graphically illustrates the plot of simulated signal to noise plus distortion ratio levels (SNDR) for K.sub.1 =4, K.sub.2 =8, K.sub.3 =4, and K.sub.4 =8 with an oversampling ratio of 64. Zero dB is defined as a full-scale input voltage which is one-half the D/A converter reference voltage, which for a differential implementation of FIGS. 16 and 17 would be the voltage defined by DPOS-DNEG.

In another embodiment, the invention disclosed herein may be used as a digital noise shaper for a D/A converter implementation. In that case, the two second-order sigma-delta modulators which are connected together in FIG. 10 would be implemented as digital circuitry comprised of appropriate adders, subtractors, accumulators, multipliers, and quantizers. The post-quantizer circuitry shown in FIG. 11 would be modified as shown in FIG. 21. Digital signal y.sub.6 (z) would be converted to an analog signal by D/A converter 32. Likewise, digital signal y.sub.5 (z) would be converted to an analog signal by D/A converter 34. The resultant signals, y.sub.6 a(z) and y.sub.5 a(z), respectively would then be summed together by an analog summing node 72. There are numerous methods by which two analog signals may be summed together which are well known by those skilled in the art. Likewise, there are numerous methods which are known by those skilled in the art by which a digital signal may be converted to an analog signal. Any such method would be appropriate for D/A converters 32 and 34 in FIG. 21.

If the quantizer Q.sub.1 in the second-order sigma-delta modulator 11 shown in FIG. 10 quantizes only the sign of the signal input to it, signal y.sub.1 (z), and thus signal y.sub.6 (z), of FIG. 21 would be represented by a 1-bit digital signal. A D/A converter which converts a 1-bit digital signal to an analog signal would result in an analog signal with only two output voltage, or current levels, possible. Such a D/A converter would be inherently linear and thus would contribute no distortion terms to the final analog signal, y.sub.out (2). If the quantizer Q.sub.2 in the second-order sigma-delta modulator 13 shown in FIG. 10 likewise quantizes only the sign of the signal input to it, then signal y.sub.2 (z) would also be represented by a 1-bit digital signal. After being processed according to the aforementioned equations as illustrated in the block diagram shown in FIG. 21, it is clear that signal y.sub.5 (z) would be represented by a plurality of bits for any value of C greater than one. Thus, the D/A converter 34 would convert a signal represented by a plurality of bits to an analog signal would have a plurality of possible output voltages, or currents, which correspond to any possible code represented by y.sub.5 (z).

As stated previously herein, signal y.sub.5 (z) can be represented by the following equation:

y.sub.5 (z)=-z.sup.-1 (1-z.sup.-1).sup.2 E.sub.1 (z)+C(1-z.sup.-1).sup.4 E.sub.2 (z)

As shown in the above equation, y.sub.5 (z) contains no terms which represent the input signal, x(z). Thus, the D/A converter 34 in FIG. 21 will add no terms which would cause harmonic distortion in the final output signal y.sub.out if there are any nonidealities in the D/A converter 34. If D/A converter 34 is nonideal, signal y.sub.5 a(z) may be represented by the following equation:

y.sub.5 a(z)=R[-z.sup.-1 (1-z.sup.-1).sup.2 E.sub.1 (z)+C(1-z.sup.-1).sup.4 E.sub.2 (z)]

In the above equation, R is a term which represents any nonidealities, or nonlinearities, in D/A converter 34 in FIG. 21. If D/A converter 32 in FIG. 21 is ideal, then the following equation would represent y.sub.6 a(z):

y.sub.6 a(z)=z.sup.-2 x(z)+z.sup.-1 E.sub.1 (z)(1-z.sup.-1).sup.2

The final output signal, y.sub.out (z) would then be the sum of y.sub.5 a(z) and y.sub.6 a(z) and would be represented by the following equation:

y.sub.out (z)=z.sup.-2 x(z)+E.sub.1 (z)z.sup.-1 (1-z.sup.-1).sup.2 (1-R)+RCE.sub.2 (z)(1-z.sup.-1).sup.4

It can be seen by the above equation that if D/A converter 34 of FIG. 21 is not perfect, then the quantization noise of the first, second-order sigma-delta modulator would not be perfectly canceled and thus, some quantization noise E.sub.1 (z) would be present in the final output, y.sub.out (z). Also, the quantization noise E.sub.2 (z) would be modified slightly. Thus, it can be seen that while additional noise may be introduced due to nonidealities, additional harmonic distortion will not be produced.

The foregoing disclosure and description of the invention are illustrative and explanatory of the preferred embodiments, and changes in the individual components, elements or connections may be made without departing from the spirit of the invention and the scope of the following claims.

Claims

1. A post-quantization network for a fourth-order sigma-delta modulator for an A/D converter, comprising;

a first digital input, output from a first second-order sigma-delta modulator;

a second digital input, output from a second second-order sigma-delta modulator; and

a digital output;

wherein said first digital input is connected to an input of a delay block and said second input in multiplied by a constant;

wherein an output of said delay block is connected to a first input of a first summing node and to a first input of a second summing node;

wherein said multiplied second input is connected to a second input of said first summing node;

wherein an output of said differentiator is provided to a second input of said second summing node; and

wherein said digital output is provided by an output of said second summing node.

2. A fourth-order sigma delta modulator for an A/D converter, comprising:

an analog input signal;

a first digital output signal;

a first summing node, including a first output of said first summing node connected to said analog input signal;

a second input of said first summing node connected to a first unit delay feedback block, and an output of said first summing node connected to an input of a first integrator, wherein said first integrator includes a one-half unit delay associated therewith;

a second summing node, including a first input of said one-half unit delay first integrator, a second input of said second summing node connected to an output of a first one-half unit delay feedback block, and an output of said second summing node connected to an input of a second integrator, wherein said second integrator includes a one-half unit delay associated therewith;

a first quantizer, including a first quantizer input connected to an output of said one-half unit delay second integrator, and a first quantizer output connected to: an input of said first one-half unit delay feedback block, to an input of said first unit delay feedback block and to said first digital output signal;

a second digital output signal;

a third summing node, including a first input of said third summing node connected to said first quantizer input;

a second input of said third summing node connected to a second unit delay feedback block, and an output of said third summing node connected to an input of a third integrator, wherein said third integrator includes a one-half unit delay associated therewith;

a fourth summing node, including a first input of said fourth summing node connected to an output of said one-half unit delay third integrator, a second input of said fourth summing node connected to an output of a second one-half unit delay feedback block, and an output of said fourth summing node connected to an input of a fourth integrator, wherein said fourth integrator includes a one-half unit delay associated therewith;

a second quantizer, including a second quantizer input connected to an output of said one-half unit delay fourth integrator, and a second quantizer output connected to: an input of said second one-half unit delay feedback block, to an input of said second unit delay feedback block and to said second digital output signal;

a first post-quantization network input, output from said first quantizer output;

a second post-quantization network input, output from said second quantizer output; and

a post-quantization network digital output;

wherein said first network input is connected to an input of a network delay block and said second network input is multiplied by constant;

wherein an output of said network delay block is connected to a first input of a first network summing node and to a first input of a second network summing node;

wherein said multiplied second network input is connected to a second input of said first network summing node;

wherein an output of said second network summing node is provided to an input of a differentiator;

wherein an output of said differentiator is provided to a second input of said second network summing node; and

wherein said network digital output is connected to an output of said second summing network node.

3. A post-quantization network for a fourth-order sigma-delta modulator for a D/A converter, comprising:

a first digital input, output from a first second-order sigma-delta modulator;

a second digital input, output from a second second-order sigma delta modulator; and

an analog output;

wherein said first digital input is connected to an input of a delay block;

wherein said second digital input is multiplied by a constant and is then provided to a first input of a first summing node;

wherein an output of said delay block is provided to a second input of said first summing node and to an input of a first D/A converter;

wherein an output of said first summing node is connected to an input of a differentiator;

wherein an output of said differentiator is input to a second D/A converter;

wherein an output of said first differentiator is input to a second D/A converter;

wherein an output of said first D/A converter is provided to a first input of a second summing node and an output of said second D/A converter is provided to a second input of said second summing node; and

wherein said analog output is connected to an output of said second summing node.

4. The network of claim 3, wherein said first D/A converter is a one-bit D/A converter.

5. The network of claim 3, wherein said second D/A converter is a multi-bit D/A converter.

6. A fourth-order sigma-delta modulator system for a D/A converter, comprising:

a digital input signal;

an analog output signal;

a first summing node, including a first input connected to said digital input signal,

a second input of said first summing node connected to a first unit delay feedback block, and an output of said first summing node connected to an input of a first integrator, wherein said first integrator includes a one-half unit delay associated therewith;

a second summing node, including a first input of said second summing node connected to an output of said one-half unit delay first integrator, a second input of said second summing node connected to an output of a first one-half unit delay feedback block, and an output of said second summing node connected to an input of a second integrator, wherein said second integrator includes a one-half unit delay associated therewith;

a first quantizer, including a first quantizer input connected to an output of said one-half unit delay second integrator, and a first quantizer output connected to: an input of said first one-half unit delay feedback block, to an input of said first unit delay feedback block and to a first digital output signal;

a second digital output signal;

a third summing node, including a first input of said third summing node connected to said first quantizer input;

a second input of said third summing node connected to a second unit delay feedback block, and an output of said third summing node connected to an input of a third integrator, wherein said third integrator includes a one-half unit delay associated therewith;

a fourth summing node, including a first input of said fourth summing node connected to an output of said one-half unit delay third integrator, a second input of said fourth summing node connected to an output of a second one-half unit delay feedback block, and an output of said fourth summing node connected to an input of a fourth integrator, wherein said fourth integrator includes a one-half unit delay associated therewith;

a second quantizer, including a second quantizer input connected to an output of said one-half unit delay fourth integrator, and a second quantizer output connected to: an input of said second one-half unit delay feedback block, to an input of said second unit delay feedback block and to said second digital output signal;

a first post-quantization digital input, output from said first quantizer;

a second post-quantization digital input, output from said second quantizer;

wherein said first post-quantization digital input is connected to an input of a post-quantization delay block;

wherein said second post-quantization digital input is multiplied by a constant and is then provided to a first input of a first post-quantization summing node;

wherein an output of said post-quantization delay block is provided to a second input of said first post-quantization summing node and to an input of a first post-quantization D/A converter;

wherein an output of said first post-quantization summing node is connected to an input of a differentiator;

wherein an output of said differentiator is input to a second post-quantization D/A converter;

wherein an output of said post-quantization first D/A converter is provided to a first input of a second post-quantization summing node and an output of said second post-quantization D/A converter is provided to a second input of said second summing node; and

wherein said analog output signal is provided at an output of said second post-quantization summing node.

7. A fourth-order sigma-delta modulator system comprising:

a first second-order sigma-delta modulator having an input and an output;

a second second-order sigma-delta modulator having an input and an output;

a post-quantization network having a first network input connected to said output of said first modulator and a second network input connected to said output of said second modulator; and

wherein said first and second modulators each include a first and a second integration stage, wherein each said integration stage includes an integrator having a 1/2 unit delay associated therewith.

8. The fourth-order modulator system of claim 7, wherein said first modulator further comprises a first modulator quantizer, said first modulator quantizer being connected to an output of said second integration stage in said first modulator, and wherein an output of said first modulator quantizer is connected to said output of said first modulator.

9. The fourth-order modulator system of claim 8, wherein said second modulator further comprises a second modulator quantizer, said second modulator quantizer being connected to an output of said second integration stage in said second modulator, and wherein an output of said second modulator-quantizer is connected to said output of said second modulator.

10. The fourth-order modulation system of claim 9, wherein a feedback path having a 1/2 unit delay associated therewith connects between said second modulator output and an input to said second integration stage in said second modulator, wherein a second feedback path, having a unit delay associated therewith, connects between said second modulator output and an input to said first integration stage in said second modulator.

11. The fourth-order modulator system of claim 8, wherein a feedback path having a 1/2 unit delay associated therewith connects between said first modulator output and an input to said second integration stage in said first modulator, wherein a second feedback path, having a unit delay associated therewith, connects between said first modulator output and an input to said first integration stage in said first modulator.