SIGMA-DELTA MODULATOR

Abstract

A sigma-delta modulator includes a first adder, a filter, a quantizer and a digital-to-analog converter. The first adder receives an input signal and an analog signal and subtracts the analog signal from the input signal to output a processed signal. The filter receives the processed signal to output a filtered signal. The quantizer receives the filtered signal to generate an output signal. The quantizer works based on a first positive reference voltage and a first negative reference voltage. The digital-to-analog converter generates the analog signal according to the output signal and outputs the analog signal to the first adder. The digital-to-analog converter works based on a second positive reference voltage and a second negative reference voltage. A difference between the first positive reference voltage and the first negative reference voltage is smaller than a difference between the second positive reference voltage and the second negative reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (PriorArt) is a block diagram showing a conventional sigma-delta modulator.

FIG. 2 is a block diagram showing a sigma-delta modulator according to a preferred embodiment of the invention.

FIG. 3 is a circuit diagram showing that a quantizer 230 is a three-bit quantizer.

FIG. 4 is a circuit diagram showing a filter 220 when a sigma-delta modulator 200 is a five-order feed-forward sigma-delta modulator.

FIG. 5 is a circuit diagram showing an example of an adder 210 and the low-pass filter 220.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 is a block diagram showing a sigma-delta modulator 200 according to a preferred embodiment of the invention. Referring to FIG. 2, the sigma-delta modulator 200 is applied to the case of a large-swing signal, such as an audio signal, which may include an adder 210, a filter 220, a quantizer 230 and a digital-to-analog converter (D/A converter) 240. The adder 210 receives an input signal X2 and an analog signal A21 and generates a processed signal S21. The filter 220 receives and filters the processed signal S21 to generate and output a filtered signal S22. The quantizer 230 receives the filtered signal S22 to generate an output signal Y2. The quantizer 230 operates in accordance with a first positive reference voltage V1ref+ and a first negative reference voltage V1ref−.

The digital-to-analog converter 240 generates the analog signal A21 according to the output signal Y2 and transfers the analog signal A21 to the adder 210 and operates on a second positive reference voltage V2ref+ and a second negative reference voltage V2ref−. The difference Di1 between the first positive reference voltage V1ref+ and the first negative reference voltage V1ref− is K times the difference Di2 between the second positive reference voltage V2ref+ and the second negative reference voltage V2ref−, where K<1.

FIG. 3 is a circuit diagram showing a three-bit quantizer 230, for example. As shown in FIG. 3, the filtered signal S22 received by the quantizer 230 of this embodiment is represented by the signals Vin+ and Vin−, and the serial resistors divide the voltage between the first positive reference voltage V1ref+ and the first negative reference voltage V1ref− into multiple sets of divided voltages. Comparators compare values of the signals Vin+ and Vin− with the divided voltages generated by the serial resistors and produce thermal codes which then entered a thermal-code-to-binary unit 231 to generate a 3-bit output signal Y2. The output signal Y2 uses the signals y0, y1 and y2 to represent each bit.

The filter 220 of this embodiment, such as a low-pass filter, a band-pass filter or a high-pass filter, includes one integrator or multiple integrators, and one gain amplifier or multiple gain amplifiers. Each integrator may be, for example, a discrete-time integrator so that an Nth-order discrete integration circuit can be formed, where N is a positive integer. FIG. 4 is a circuit diagram showing the filter 220 when the sigma-delta modulator 200 is a fifth-order feed-forward sigma-delta modulator. Referring to FIG. 4, the filter 220 includes gain amplifiers f1, f2, h1, h2, h3, h4 and h5, integrators 221(a), 221(b), 221(c), 221(d) and 221(e), and adders 212(a), 212(b) and 212(c).

The gain amplifier hi receives the integration signal outputted from the integrator 221 (a), amplifies the integration signal according to its default weighting coefficient to generate an amplified integration signal, and then inputs the amplified integration signal to the adder 212(c). The gain amplifier h2 receives the integration signal outputted from the integrator 221(b), amplifies the integration signal according to its default weighting coefficient to generate an amplified integration signal, and then inputs the amplified integration signal to the adder 212(c). The gain amplifier h3 receives the integration signal outputted from the integrator 221 (c), amplifies the integration signal according to its default weighting coefficient to generate an amplified integration signal, and then inputs the amplified integration signal to the adder 212(c). The gain amplifier h4 receives the integration signal outputted from the integrator 221 (d), amplifies the integration signal according to its default weighting coefficient to generate an amplified integration signal, and then inputs the amplified integration signal to the adder 212(c). The gain amplifier h5 receives the integration signal of the integrator 221 (e), amplifies the integration signal according to its default weighting coefficient to generate an amplified integration signal, and then inputs the amplified integration signal to the adder 212(c). The adder 212(c) summates the amplified integration signals to generate the filtered signal S22.

When the quantizer 230 retains the output signal Y2 at the same digital code, the large current supplied under the same positive/negative reference voltage in the prior art are prevented and thus reduces the power-consumption since the difference Di1 between the first positive reference voltage V1ref+ and the first negative reference voltage V1ref− is smaller than the difference Di2 between the second positive reference voltage V2ref+ and the second negative reference voltage V2ref−. The gain amplifier of the filter 220 amplifies the integration signals by K times to match with the conditions that the difference Di1 is K times of the difference Di2, where K<1.

Compared with the prior art method, the quantizer 230 uses a reference voltage different from that of the digital-to-analog converter 240. Hence, the amplitude of the filtered signal S22 outputted from the adder 222(c) has to be reduced in correspondence with the range from the first positive reference voltage V1ref+ to the first negative reference voltage V1ref− of the quantizer 230, and the gains of the gain amplifiers h1 to h5 should be configured such that the amplitude of the filtered signal S22 also falls within this range. That is, the gains of the gain amplifiers h1 to h5 have to be reduced in correspondence with the first positive reference voltage V1ref+ and the first negative reference voltage V1ref− of the quantizer. In this embodiment, the first positive reference voltage V1ref+ and the first negative reference voltage V1ref− may be configured to be symmetrically relative to a common mode voltage, and the second positive reference voltage V2ref+ and the second negative reference voltage V2ref− may be configured to be symmetrically relative to another common mode voltage.

FIG. 5 is a circuit diagram showing an example of the adder 210 and the low-pass filter 220. Referring to FIG. 5, the circuit includes capacitors C1, C_S1, C_S2, C_S3, C_S4 and C_S5 and switches CK1, CK1d, CK2 and CK2d. The input signals are V_IN1+ to V_IN5+ and V_IN1− to V_IN5−, the potentials of the input signals are respectively stored in the capacitors C_S1 to C_S5 when the switches CK1, CK1d, CK2 and CK2d are turned on. Subsequently, the capacitor C1 receives a sum of potentials of other capacitors, and finishes the filtering process in conjunction with the switches. Similar to the above-mentioned condition, the signal has to be amplified K times in correspondence with the smaller reference voltage of the quantizer 230, where K<1. In this circuit, capacitances of the capacitors C_S1, C_S2, C_S3, C_S4 and C_S5 are reduced in order to reduce the signal gain. Thus, the area is reduced and the power consumption is also lowered so that the circuit are designed more easily and the cost of the circuit can be reduced.

In the sigma-delta modulator according to the embodiment of the invention, the quantizer utilizes the independent and lower reference voltage so that the weighting gain in the filter is also correspondingly reduced to hold the same output of the digital code. The output swing of the adder can be decreased greatly without influencing the operation of the modulator so that the power-consumption can be reduced. In addition, conditions that require large-current consumption man, also be reduced under the requirement of high slew rates.

While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

1. A sigma-delta modulator, comprising: a filter for receiving a processed signal and generating a filtered signal;a quantizer for receiving the filtered signal to generate an output signal, wherein the quantizer operates in accordance with a first voltage difference; anda digital-to-analog converter for generating an analog signal according to the output signal, wherein the digital-to-analog converter operates in accordance with a second voltage difference;wherein, the first voltage difference is K times of the second voltage difference, and K is smaller than 1.

2. The modulator according to claim 1, further comprising: an adder for receiving an input signal and the analog signal, and generating the processed signal.

3. The modulator according to claim 1, wherein the first voltage difference is a difference between a first positive reference voltage and a first negative reference voltage.

4. The modulator according to claim 3, wherein the first positive reference voltage and the first negative reference voltage are symmetrical relative to a common mode voltage.

5. The modulator according to claim 1, wherein the second voltage difference is a difference between a second positive reference voltage and a second negative reference voltage.

6. The modulator according to claim 5, wherein the second positive reference voltage and the second negative reference voltage are symmetrical relative to a common mode voltage.

7. The modulator according to claim 1, wherein the filter comprises: at least one integrator for outputting at least one integration signal;at least one gain amplifier for amplifying the integration signal to generate at least one amplified integration signal; anda second adder for receiving and summating the amplified integration signal and outputting the filtered signal.

8. The modulator according to claim 7, wherein the integrator is a discrete-time integrator.

9. The modulator according to claim 7, wherein the gain amplifier amplifies the integration signal by K times.

10. The modulator according to claim 1, wherein the filter is a low-pass filter.

11. The modulator according to claim 1, wherein the filter is a band-pass filter.

12. The modulator according to claim 1, wherein the filter is a high-pass filter.

13. The modulator according to claim 1 being applied to a large-swing signal.

14. The modulator according to claim 13, wherein the large-swing signal is an audio signal.

15. The modulator according to claim 1, wherein the filter comprises an Nth-order discrete-time integration circuit, and N is a positive integer.