Claims
- 1. A signal acquisition circuit for a radar system, comprising:
- (a) a phase lock loop to which an input signal is applied;
- (b) a variable frequency oscillator in the phase lock loop, said oscillator having a signal output;
- (c) means for locking the frequency of said variable frequency oscillator;
- (d) comparison means arranged to determine the magnitude of a part of the input signal within the bandwidth of the phase lock loop and in phase coherence with the variable frequency oscillator, and to provide an output signal indicative of said magnitude;
- (e) means for varying the bandwidth of the phase lock loop in accordance with the output signal from the comparison means until the bandwidth stabilizes and the output signal of the comparison means is brought to a first predetermined value;
- (f) first detection means arranged to produce an output signal dependent on whether the output signal from the comparison means is above or below a second predetermined value when said bandwidth stabilizes; and
- (g) a confirm trigger circuit and a reject trigger circuit connected to receive the output signal from the first detection means, the confirm trigger circuit being arranged to produce a confirm target signal if the phase lock loop stabilizes at a relatively narrow bandwidth, and the reject trigger circuit being arranged to produce a reject signal if the phase lock loop stabilizes at a relatively broad bandwidth.
- 2. A signal acquisition circuit as claimed in claim 1, wherein the comparison means comprises a quadrature phase sensitive detector to which said input signal and said signal output from the variable frequency oscillator are applied, the output of the quadrature phase sensitive detector providing the output signal indicative of said magnitude.
- 3. A signal acquisition circuit as claimed in claim 1, wherein the means for varying the bandwidth of the phase lock loop comprises a first subtraction circuit arranged to subtract the output signal of the comparison means from a first d.c. reference signal and provide an output signal, and a first integrator connected to receive the output signal from the first subtraction circuit, and to control a variable gain circuit in the phase lock loop whereby to vary the bandwidth of the phase lock loop.
- 4. A signal acquisition circuit as claimed in claim 3, wherein said first detection means comprises a second subtraction circuit arranged to subtract an output signal of said first integrator from a second d.c. reference signal and provide an output signal, and a second integrator connected to receive the output signal of the second subtraction circuit and provide the output signal of said first detection means.
- 5. A signal acquisition circuit as claimed in claim 3, including means for monitoring and storing a quantity representative of the average level of the input signal, second detection means arranged to produce an output signal when the instantaneous level of the input signal exceeds a first predetermined monitored average level, and means responsive to an output signal from said second detection means to alter the first predetermined value of the output signal of the comparison means at which the bandwidth of the phase lock loop stabilizes.
- 6. A signal acquisition circuit as claimed in claim 5, wherein the second detection means is arranged to produce an output signal when the instantaneous level of the input signal is within a range 6 dB to 17 dB above the predetermined average level.
- 7. A signal acquisition circuit as claimed in claim 6, including means for adjusting the values of the first and second d.c. reference signals, and means for adjusting a time constant of the second integrator when an instantaneous level of the input signal exceeds a stored average level of the input signal.
Parent Case Info
This application is a continuation-in-part of earlier filed co-pending application Ser. No. 673,297 filed Apr. 2, 1976 for RADAR SYSTEMS, now abandoned.
US Referenced Citations (8)
Non-Patent Literature Citations (1)
Entry |
RCA COS/MOS Integrated Circuits, Spec. Sheet for CD4046 Phase-Locked Loop, pp. 150-153, 1977. |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
673297 |
Apr 1976 |
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