BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal amplifier, and more particularly, to a signal amplifier capable of generating a zero for compensating signal attenuation to increase high frequency gain.
2. Description of the Prior Art
In general, the signal amplifier has the phenomenon of signal attenuation due to the effect of low pass channel and the parasitic capacitance inside the amplifier. In order to compensate signal attenuation, the common method is to add a zero in the signal path to increase the signal gain for compensation. In the prior art, the common method of inserting a zero is using capacitive degeneration or inductive load, etc.
For example, please refer to FIG. 1A and FIG. 1B. FIG. 1A is a schematic diagram of a conventional differential signal amplifier 10 and FIG. 1B is a schematic diagram of small signal equivalent circuit of a part of the differential signal amplifier 10 in FIG. 1A. As shown in FIG. 1A and FIG. 1B, a resistor Rs and a capacitor Cs are added between the sources of transistors M1 and M2 in the conventional differential signal amplifier 10 to form the structure of source capacitive degradation to generate a zero Z1=1/RsCs.
On the other hand, please refer to FIG. 2, which is a schematic diagram of a conventional single-ended signal amplifier 20. As shown in FIG. 2, a load resistor Rd is coupled to an inductor in series in the conventional single-ended signal amplifier 20 and forms inductive load to generate a zero Z2=Rd/Ld.
The above structures of the signal amplifier 10 and the single-ended signal amplifier 20, and the method of generating zeros are known by those skilled in the art. However, utilizing only capacitive degeneration or inductive load to add zeros is lack of flexibility in application. Thus, there is a need to provide other method of adding zeros.
SUMMARY OF THE INVENTION
A signal amplifier is provided, capable of generating a zero for compensating signal attenuation to increase high frequency gain.
A signal amplifier is disclosed. The signal amplifier comprises a first transistor, comprising a first terminal, a second terminal and a control terminal, a resistor, comprising one terminal coupled to the first terminal of the first transistor, and another terminal coupled to the control terminal of the first transistor, and a capacitor, comprising one terminal coupled to the control terminal of the first transistor, and another terminal coupled to a specific voltage.
A signal amplifier is further disclosed. The signal amplifier comprises a first transistor, comprising a first terminal, a second terminal and a control terminal, a resistor, comprising one terminal coupled to the control terminal of the first transistor, and another terminal coupled to the specific voltage, and a capacitor, comprising one terminal coupled to the second terminal of the first transistor, and another terminal coupled to the control terminal of the first transistor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a schematic diagram of a conventional differential signal amplifier.
FIG. 1B is a schematic diagram of small signal equivalent circuit of a part of the differential signal amplifier in FIG. 1A.
FIG. 2 is a schematic diagram of a conventional single-ended signal amplifier.
FIG. 3A is a schematic diagram of a single-ended signal amplifier according to an embodiment of the present invention.
FIG. 3B is a schematic diagram of small signal equivalent circuit of lower half of the single-ended signal amplifier in FIG. 3A.
FIG. 4, FIG. 5, and FIG. 6 are the schematic diagrams of other single-ended signal amplifier according to an embodiment of the present invention.
DETAILED DESCRIPTION
Please refer to FIG. 3A, which is a schematic diagram of a single-ended signal amplifier 30 according to an embodiment of the present invention. The single-ended signal amplifier 30 includes a transistor M3, a transistor M4, a resistor Rp, and a capacitor Cp. The detail structure and connection are as shown in FIG. 3. A terminal of the resistor Rp is coupled to a drain (i.e. a first terminal) of the transistor M3 and another terminal of the resistor Rp is coupled to a gate (i.e. a control terminal) of the transistor M3. A terminal of the capacitor Cp is coupled to the gate of the transistor M3 and another terminal of the capacitor Cp is coupled to a ground voltage VSS1 (i.e. a specific voltage). A drain of the transistor M4 is coupled to the drain of the transistor M3 and outputs an output voltage Vout, a gate of the transistor M4 is utilized for receiving an input voltage Vin, and a source (i.e. a second terminal) of the transistor M4 is coupled to a system voltage VCC1. A source of the transistor M3 is coupled to a ground voltage VSS2. The transistors M3 and M4 are an N-type metal oxide semiconductor (MOS) transistor and a P-type MOS transistor, respectively.
On the other hand, please refer to FIG. 3B, which is a schematic diagram of a small signal equivalent circuit of a lower half of the signal amplifier 30 in FIG. 3A, wherein a resistor r is the output equivalent resistance of the transistor M3 and a capacitor c is the parasitic capacitance of the drain of the transistor M3. As shown in FIG. 3A and FIG. 3B, a current I flowing from the drain of the transistor M4 to the drain of the transistor M3 is:
I=(Vout−v)/Rp+gm*v+Vout/r+s*c*Vout
Substituting the impedance as Vout/I and substituting a voltage v as the division voltage of voltage Vout into the above equation can get:
From the above equation, the single-ended signal amplifier 30 gets a zero Z3=1/RpCp. As a result, based on the original basic structure of the single-ended signal amplifier with the transistors M3, M4 connected in series, the present invention adds the resistor Rp between the drain and the source of the transistor M3 and adds the capacitor Cp between the gate of the transistor M3 and a ground voltage VSS1 to generate the zero Z3=1/RpCp for compensating signal attenuation and increasing high frequency gain.
Noticeably, the main spirit of the present invention is adding the resistor Rp between the drain and the source of the transistor M3 and adding the capacitor Cp between the gate of the transistor M3 and a ground voltage VSS1 to generate the zero Z3=1/RpCp for compensating signal attenuation and increasing high frequency gain. Those skilled in the art can make modifications or alterations accordingly. For example, the ground voltage or the system voltage for the specific voltage can be provided by a voltage source or a current source. Besides, the resistor Rp can be implemented by parasitic resistance, poly-silicon, metal, MOS or any type of resistance, and the capacitor Cp also can be implemented by the parasitic capacitance, poly-silicon, metal, MOS or any type of capacitance. Moreover, in the above single-ended signal amplifier 30, the transistor M3 and M4 are the N-type MOS transistor and P-type MOS transistor, respectively, the resistor Rp is coupled between the drain and the gate of the transistor M3, and the capacitor Cp is coupled between the gate of the transistor M3 and the ground voltage VSS1. In other embodiment, the transistors can be implemented by other type of arrangement, and the capacitor and the resistor can also be coupled in other manner.
In detail, please refer to FIG. 4, FIG. 5, and FIG. 6, which are schematic diagrams of single-ended signal amplifiers 40, 50, and 60 according to embodiments of the present invention. As shown in FIG. 4, the single-ended signal amplifier 40 includes a transistor M5, a transistor M6, a resistor Rp1, and a capacitor Cp1. The detail structure and connection are shown in FIG. 4. A terminal of the resistor Rp1 is coupled to a drain (i.e. a first terminal) of the transistor M5 and another terminal of the resistor Rp1 is coupled to a gate (i.e. a control terminal) of the transistor M5. A terminal of the capacitor Cp1 is coupled to the gate of the transistor M5 and another terminal of the capacitor Cp1 is coupled to a system voltage VCC1 (i.e. a specific voltage). A drain of the transistor M6 is coupled to the drain of the transistor M5 and outputs an output voltage Vout, a gate of the transistor M6 is utilized for receiving an input voltage Vin, and a source (i.e. a second terminal) of the transistor M6 is coupled to a ground voltage VSS1. A source of the transistor M5 is coupled to a system voltage VCC2. The transistors M5 and M6 are a P-type MOS transistor and an N-type MOS transistor, respectively. In other words, the single-ended signal amplifier 40 and the single-ended signal amplifier 30 are partially similar, and the main differences are that the transistors M5 and M6 are P-type MOS transistor and N-type MOS transistor, respectively, and the capacitor Cp1 is coupled between the gate of the transistor M5 and the system voltage VCC1 in the single-ended signal amplifier 40. In such a situation, by method similar to the above method for the single-ended signal amplifier 30, it can derive that the single-ended signal amplifier 40 has a zero Z4=1/Rp1Cp1. As a result, the embodiment can also generate the zero Z4=1/Rp1Cp1 for compensating signal attenuation and increasing high frequency gain.
As shown in FIG. 5, the single-ended signal amplifier 50 includes a transistor M7, a transistor M8, a resistor Rp2, and a capacitor Cp2. The detail structure and connection are shown in FIG. 5. A terminal of the resistor Rp2 is coupled to a gate of the transistor M7 and another terminal of the resistor Rp2 is coupled to a ground voltage VSS1 (i.e. a specific voltage). A terminal of the capacitor Cp2 is coupled to the source (i.e. a second terminal) of the transistor M7 and another terminal of the capacitor Cp2 is coupled to the gate (i.e. a control terminal) of the transistor M7. A drain of the transistor M8 is coupled to the source of the transistor M7 and outputs an output voltage Vout, a gate of the transistor M8 is utilized for receiving an input voltage Vin, and a source of the transistor M8 is coupled to a system voltage VCC1. A drain of the transistor M7 is coupled to a ground voltage VSS2. Both the transistors M7 and M8 are P-type MOS transistors. In other words, the single-ended signal amplifier 50 and the single-ended signal amplifier 30 are partially similar and the main differences are that both the transistors M7 and M8 are P-type MOS transistors, the resistor Rp2 is coupled between the gate of the transistor M7 and the ground voltage VSS1, and the capacitor Cp2 is coupled between the source and the gate of the transistor M7 in the single-ended signal amplifier 50. In such a situation, by method similar to the above method for the single-ended signal amplifier 30, it can also derive that the single-ended signal amplifier 50 has a zero Z5=1/Rp2Cp2. As a result, the embodiment can also generate the zero Z5=1/Rp2Cp2 for compensating signal attenuation and increasing high frequency gain.
As shown in FIG. 6, the single-ended signal amplifier 60 includes a transistor M9, a transistor M10, a resistor Rp3, and a capacitor Cp3. The detail structure and connection are shown in FIG. 6. A terminal of the resistor Rp3 is coupled to a gate of the transistor M9 and another terminal of the resistor Rp3 is coupled to a system voltage VCC1 (i.e. a specific voltage). A terminal of the capacitor Cp3 is coupled to the source (i.e. a second terminal) of the transistor M9 and another terminal of the capacitor Cp3 is coupled to the gate (i.e. a control terminal) of the transistor M9. A drain of the transistor M10 is coupled to the source of the transistor M9 and outputs an output voltage Vout, a gate of the transistor M10 is utilized for receiving an input voltage Vin, and a source of the transistor M10 is coupled to a ground voltage VSS1. A drain of the transistor M9 is coupled to a system voltage VCC2. Both the transistors M9 and M10 are N-type MOS transistors. In other words, the single-ended signal amplifier 60 and the single-ended signal amplifier 50 are partially similar and the main differences are that both the transistors M9 and M10 are N-type MOS transistors and the resistor Rp3 is coupled between the gate of the transistor M9 and the ground voltage VSS1 in the single-ended signal amplifier 60. In such a situation, by a method similar to the above method for the single-ended signal amplifier 30, it can also be derived that the single-ended signal amplifier 60 has a zero Z6=1/Rp3Cp3. As a result, the embodiment can also generate the zero Z6=1/Rp3Cp3 for compensating signal attenuation and increasing high frequency gain.
Besides, the resistors and the capacitors are added in the above single-ended signal amplifiers to generate zeros in above embodiments, but resistors and capacitors can also be added in similar locations in differential signal amplifiers to generate zeros in other embodiments. Additionally, the transistors are implemented by MOS transistors in the above embodiment, but the transistors can also be implemented by any type of transistor in other embodiment. As the transistors are implemented by bipolar junction transistors (BJTs), the first terminal, the second terminal, and the control terminal can be a collector, an emitter, and a base. All of these are known by those skilled in the art, and will not be narrated hereinafter.
In the prior art, only utilizing capacitive degeneration or inductive load to add zeros is lack of flexibility in application. In comparison, the embodiments can add the resistor and the capacitor between the drain and the gate of transistor and between and the gate of the transistor and a specific voltage to generate a zero for compensating signal attenuation and increasing high frequency gain.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20140028399
