Claims
- 1. A method for balancing signals across a voltage island domain in an IC design comprising the steps of:
balancing signals at heirarchial levels above the voltage domains; and balancing signals at other levels in the design as a function of varying operating conditions across the voltage domains in the IC.
- 2. The method of claim 1 wherein the varying voltage operating conditions are worst case and best case conditions.
- 3. The method of claim 2 also comprising the step of calculating the average latency for paths in the voltage domains.
- 4. The method of claim 3 wherein the average latency is the mid-point between the worst case and best case conditions.
- 5. The method of claim 3 also comprising the step of iteratively increasing the delay in the paths of the voltage domains to match a target delay.
- 6. The method of claim 5 wherein the target delay is determined by examining the average latency of each voltage domain and choosing the slowest latency.
- 7. The method of claim 5 wherein the best case and worst case conditions are determined during each iteration and the average latency is recalculated based on the conditions.
- 8. The method of claim 1 wherein the balancing occurs through the use of programmable delay elements.
- 9. The method of claim 1 wherein voltage jitter is also considered in the design.
- 10. The method of claim 1 where in the signals are clock signals.
- 11. A method for balancing signals across an IC design having multiple voltage domains comprising the steps of:
balancing signals at heirarchial levels above the voltage domains; determining the average latency inside each voltage domain; balancing signals at the other levels in the design by incrementing progammable elements with the goal of having each voltage domain; and balancing signals at the other levels in the design by incrementing progammable elements with the goal of having each voltage domain.
- 12. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for balancing signals across voltage domains in an integrated circuit design, the method comprising the steps of:
balancing signals at heirarchial levels above the voltage domains; and balancing signals at other levels in the design as a function of varying operating conditions across the voltage domains in the IC.
- 13. The method steps of claim 12 wherein the varying voltage operating conditions are worst case and best case conditions.
- 14. The method steps of claim 13 also comprising the step of calculating the average latency for paths in the voltage domains.
- 15. The method steps of claim 14 wherein the average latency is the mid-point between the worst case and best case conditions.
- 16. The method steps of claim 14 also comprising the step of iteratively increasing the delay in the paths of the voltage domains to match a target delay.
- 17. The method steps of claim 16 wherein the target delay is determined by examining the average latency of each voltage domain and choosing the slowest latency.
- 18. The method steps of claim 16 wherein the best case and worst case conditions are determined during each iteration and the average latency is recalculated based on the conditions.
- 19. The method steps of claim 12 wherein the balancing occurs through the use of programmable delay elements.
- 20. The method steps of claim 12 wherein voltage jitter is also considered in the design.
- 21. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for balancing signals across voltage domains in an integrated circuit design, the method comprising the steps of:
balancing signals at hierarchical levels above the voltage domains; determining the average latency inside each voltage domain; and balancing signals at the other levels in the design by incrementing programmable delay elements with the goal of having each voltage domain.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to another U.S. Patent Application, IBM Docket Number BUR920020136US1, entitled “Programmable Delay Method for Hierarchical Signal Balancing,” which is filed concurrently with this application by the same assignee and is incorporatated herein by reference.