Claims
- 1. A circuit for modifying, within a predetermined frequency band, the dynamic range of an input signal having an input dynamic range with a predetermined upper limit, comprising a main signal circuit responsive to said input signal to transmit, at least within the predetermined frequency band, a main signal component from an input terminal to an output terminal, the main signal circuit including combining means, delay means coupled to the main circuit for delaying a second signal component derived from the main circuit, and a further circuit including means for forming within the predetermined frequency band the difference signal between a third signal component derived from the main circuit and the delayed version of the second signal component derived from the main circuit, the delay of the delayed second signal component delaying the second signal component relative to the third signal component, and the output of said further circuit coupled to said combining means so as to combine with the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, and means for restricting the said difference signal to a predetermined amplitude which is not greater than about one-tenth the amplitude of the main component existing at the predetermined upper limit of the input dynamic range.
- 2. A circuit according to claim 1, comprising a frequency selective filter operative on the difference signal.
- 3. A circuit according to claim 1, for operating on a television signal component, wherein the delay of the delayed version of the signal is equal to a small fraction of a line period of the television signal.
- 4. A system for modifying the dynamic range of a colour television signal, comprising a colour decoder for decoding the television signal into a plurality of baseband components, a plurality of circuits, each in accordance with claim 1, for modifying the dynamic range of the respective baseband components, and a colour encoder responsive to the outputs of the said plurality of circuits.
- 5. A system for reducing noise introduced into a television signal by a standards converter which converts the signal from first standards to second standards, comprising a first circuit according to claim 1 preceding the standards converter and wherein said combining means combine the difference signal of said first circuit in a sense such as to boost the main component of said first circuit, and a second circuit according to claim 1 following the standards converter and wherein said combining means combine the difference signal of said second circuit in a sense such as to buck the main component of said second circuit, the delay of the first circuit bearing a predetermined relationship to the first standards and the delay of the second circuit bearing the corresponding relationship to the second standards.
- 6. A circuit according to claim 1, wherein the further circuit comprises a plurality of channels including filter means defining different regions of the frequency band of the difference signal, the said restricting means comprising a plurality of individual restricting means in the said channels respectively, and wherein said combining means combine with the main component the restricted components provided by all the said channels.
- 7. A circuit according to clam 1, wherein the second and third signal components are derived from a single point in the main circuit.
- 8. A circuit according to claim 7, wherein said point is on the output side of said combining means, and said combining means combine the difference signal in a sense such as to boost the main component, whereby the circuit acts to compress the dynamic range.
- 9. A circuit according to claim 7, wherein said point is on the input side of said combining means, and said combining means combine the difference signal in a sense such as to buck the main component, whereby the circuit acts to expand the dynamic range.
- 10. A circuit according to claim 7, wherein said point is on the input side of said combining means, and said combining means combine the difference signal in a sense such as to boost the main component, whereby the circuit acts to compress the dynamic range.
- 11. A circuit according to claim 7, wherein said point is on the output side of said combining means, and said combining means combine the difference signal in a sense such as to buck the main component, whereby the circuit acts to expand the dynamic range.
- 12. A circuit according to claim 1, for operating on a television signal component, wherein the delay of the delayed version signal is substantially equal to one or more line periods of the television signal.
- 13. A circuit according to claim 12, for operating on a television signal including a chrominance subcarrier component, comprising means for effecting fine adjustment of the delay to match an offset of the subcarrier.
- 14. A circuit according to claim 1, for operating on a television signal component, wherein the delay of the delayed version signal is substantially equal to one or more field periods of the television signal.
- 15. A circuit according to claim 14, comprising means for effecting time adjustment of the field delay.
- 16. A system for modifying the dynamic range of a television signal, comprising a plurality of circuits each in accordance with claim 1, including filter means preceding the input terminals of said circuits and selecting different parts of the television signal frequency band, the delay of each said circuit bearing a predetermined relationship to the line and field periods of the television signal.
- 17. A system according to claim 16, wherein one delay is substantially equal to one or more line periods and another delay is substantially equal to one or more field periods.
- 18. A circuit according to claim 1, wherein the restricting means includes a filter on the output of which a limiting means is directly operative as an element of said filter, the variation of impedance of said limiting means consequent upon limiting action thereof affecting the characteristics of the filter so as to narrow the pass-band of the filter on the appearance of signal components exceeding the predetermined amplitude, thereby to effect the said restriction of the difference signal.
- 19. A circuit according to claim 18, wherein the limiting means is a diode limiter.
- 20. A circuit according to claim 19, comprising means responsive to a signal derived from a point in said modifying circuit to provide a bias signal to the diode limiter of such sense as to reduce the limiting level thereof as the signal level at said point in the circuit increases.
- 21. A circuit according to claim 1, wherein the restricting means is a diode limiter.
- 22. A circuit according to claim 21, comprising means responsive to a signal derived from a point in said modifying circuit to provide a bias signal to the diode limiter of such sense as to reduce the limiting level thereof as the signal level of said point in the circuit increases.
- 23. A circuit according to claim 22, comprising means for limiting the bias signal to a level such that the limiting level of the diode limiter is not reduced below zero.
- 24. A circuit according to claim 1, wherein the third signal component is derived from a first point in the main circuit and the second signal component is derived from a second different point in the main circuit.
- 25. A circuit according to claim 24, wherein the said points in the main circuit are on opposite sides of said combining means, the further circuit being coupled to the first and second points by way of direct and delay circuit paths, respectively, of which the delay path includes the delay means.
- 26. A circuit according to claim 25, wherein the first and second points are respectively on the input side and output side of said combining means and wherein said combining means combine the difference signal in a sense such as to boost the main component, whereby the circuit acts to compress the dynamic rage.
- 27. A circuit according to claim 25, wherein the first and second points are respectively on the output side and input side of said combining means and wherein said combining means combine the difference signal in a sense such as to buck the main component, whereby the circuit acts to expand the dynamic range.
- 28. A circuit according to claim 25 wherein the first and second points are respectively on the output side and input side of said combining means and wherein said combining means combine the difference signal in a sense such as to boost the main component, whereby the circuit acts to compress the dynamic range.
- 29. A circuit according to claim 25, wherein the first and second points are respectively on the input side and output side of said combining means and wherein said combining means combine the difference signal in a sense such as to buck the main component, whereby the circuit acts to expand the dynamic range.
- 30. A circuit according to claim 25, wherein the direct and delay circuit paths include frequency selective filters having the same characteristics.
- 31. A circuit according to claim 25, wherein the direct and delay circuit paths include frequency selective filters having different characteristics.
- 32. A circuit according to claim 25, for use with a periodic signal with a period nominally equal to the delay of the delay path, comprising means for comparing the phases of signal components from the delay and direct paths and operative automatically to adjust the delay of the delay path so as to tend to reduce any phase error between said components to zero.
- 33. A circuit according to claim 25, wherein one of the delay and direct paths includes gain adjusting means to settable that a steady signal component whose period equals the delay of the delay means contributes no component to the difference signal.
- 34. A circuit according to claim 33, wherein the gain adjusting means comprise means for deriving time averaged signals from the delay and direct paths, means for differencing the time averaged signals to derive an error signal, and means for automatically adjusting the gain of one of the delay and direct paths in response to the error signal so as to tend to reduce the error signal to zero.
- 35. A circuit according to claim 33, wherein the gain adjusting means adjust the gain of the delay path.
- 36. A circuit according to claim 25, wherein the delay path includes a plurality of delay means arranged to provide a corresponding plurality of signals delayed by a succession of delay times whose values form an arithmetic progression, the further circuit includes means for forming the difference signals between the signal provided by the direct path and each of the plurality of signals provided by the different delays of the delay path and a plurality of means for restricting the amplitudes of the respective difference signals to said predetermined amplitude, and said combining means combine all the difference signals with the main component.
- 37. A circuit according to claim 36, wherein the delay path includes a plurality of delay means in series, each having the same delay, and wherein the said plurality of signals are derived from the outputs of the delay means.
- 38. A circuit according to claim 36, for operating on a television signal component, wherein the delay path includes a first plurality of delay means providing signals delayed by multiples of a television line period and a second plurality of delay means providing signals delayed by multiples of a television field period.
- 39. A circuit for modifying the dynamic range of an input signal having an input dynamic range with a predetermined upper limit, comprising a main signal circuit responsive to said input signal to transmit a main signal component from an input terminal to an output terminal, the main signal circuit including combining means, and a plurality of further circuits, each including means for delaying a signal derived from a point in the main circuit, means for forming the difference signal between a signal derived from a point in the main circuit and its corresponding delayed signal derived from a point in the main circuit, and an output coupled to said combining means in the main circuit so as to combine with the main component the said difference signal, which difference signal modifies the main component when said difference signal exits, and each further circuit including means for restricting the said difference signal thereof to a predetermined amplitude which is not greater than about one-tenth the amplitude of the main component existing at the predetermined upper limit of the input dynamic range.
- 40. A dynamic range modifying circuit according to claim 39, wherein the main signal circuit is connected to the input terminal through at least one delay means, and wherein said dynamic range modifying circuit includes at least one additional further circuit including means for forming the difference signal between a signal derived from a point in the main signal circuit and a signal derived from the input to said at least one delay means, and means for amplitude restricting this difference signal, said combining means combining all the restricted difference signals, including that from said at least one additional circuit, with the main component so as to buck the main component signal when the combined, restricted difference signals exist.
- 41. A noise reduction system comprising a circuit for modifying the dynamic range of an input signal having an input dynamic range having a predetermined upper limit, the circuit comprising a main signal circuit responsive to said input signal to transmit, at least within the predetermined frequency band, a main signal component from an input terminal to an output terminal the main signal circuit including combining means, delay means coupled to the main circuit for delaying a second signal component from the main circuit, and a further circuit including means for forming within the predetermined frequency band the difference signal between a third signal component derived from the main circuit and the delayed version of the second signal component derived from the main circuit, the delay of the delayed second signal component delaying the second signal component relative to the third signal component, and the further circuit having an output coupled to said combining means in the main circuit so as to combine with the main component the said difference signal which difference signal modifies the main component when said difference signal exists, means for restricting the said difference signal to a predetermined amplitude which is not greater than about one-tenth the amplitude of the main component existing at the predetermined upper limit of the input dynamic range, and switching means operable to place the dynamic range modifying circuit selectively in a compressor configuration in which said combining means combine said difference signal in a sense such as to boost said main component and an expander configuration in which said combining means combine said difference signal in a sense such as to buck said main component.
- 42. A system according to claim 41, wherein the difference signal is formed between a signal at a first terminal and a delayed version of a signal at a second terminal, and wherein the switching means connect the first and second terminals to points in the main circuit respectively preceding and following said combining means in the compressor configuration of the circuit and to points in the main circuit respectively following and preceding said combining means in the expander configuration of the circuit.
- 43. A system according to claim 41, wherein the difference signal is formed between a signal at a first terminal and a delayed version of a signal at a second terminal, and wherein the switching means comnect the first and second terminals to points in the main circuit respectively following and preceeding said combining means in the compressor configuration of the circuit and to points in the main circuit respectively preceding and following said combining means in the expander configuration of the circuit.
- 44. A system according to claim 41, wherein the difference signal is formed between a signal derived from a terminal connected to the main signal and a delayed version of the same signal, and wherein the switching means connect the terminal to a point in the main circuit preceding said combining means in the compressor configuration of the circuit and to a point in the main circuit following said combining means in the expander configuration of the circuit.
- 45. A system according to claim 41, wherein the difference signal is formed between a signal derived from a terminal connected to the main circuit and a delayed version of the same signal, and wherein the switching means connect the terminal to a point in the main circuit which follows said combining means in the compressor configuration of the circuit and to a point in the main circuit which precedes said combining means in the expander configuration of the circuit.
- 46. A noise reduction system for reducing noise in signals within an input dynamic range having a predetermined upper limit and comprising a compressor circuit responsive to an input signal and feeding an information channel and an expander circuit fed by the information channel, the compressor circuit comprising a first main signal circuit responsive to said input signal to transmit at least within a predetermined frequency band a main, first signal component from an input terminal to an output terminal said first main signal circuit including first combining means, delay means coupled to the first main circuit for delaying a second signal component derived from the first main circuit, and a first further circuit including means for forming within the predetermined frequency band a first difference signal between a third signal component derived from the first main circuit and the delayed version of the second signal component derived from the first main circuit and an output coupled to said first combining means in the first main circuit so as to combine with the main, first component the first difference signal, in a sense such that the first difference signal boosts the main, first component when said difference signal exists, and first means for restricting the first difference signal to a predetermined amplitude which is not greater than about one-tenth the amplitude of the first main component existing at the predetermined upper limit of the input dynamic range, and the expander circuit comprising a second main signal circuit responsive to a signal from said output terminal of said compressor circuit to transmit at least within the predetermined frequency band a main, fourth signal component from an input terminal to an output terminal said second main signal circuit including second combining means, delay means coupled to the second main circuit for delaying a fifth signal component derived from the second main circuit, and a second further circuit including means for forming within the predetermined frequency band a second difference signal between a sixth signal component derived from the second main circuit and the delayed version of the fifth signal component derived from the second main circuit, and an output coupled to said second combining means in the second main circuit so as to combine with the main, fourth component the second difference signal, in a sense such that the second difference signal bucks the second main component when said second difference signal exists, and second means for restricting the second difference signal to a predetermined amplitude which is not greater than about one-tenth the amplitude of the second main component existing at the predetermined upper limit of the input dynamic range.
- 47. A system according to claim 46, wherein each difference signal is formed between a signal derived from a first point in the corresponding main circuit and a delayed version of a signal derived from a different point in the corresponding main circuit, and wherein the first point and different point respectively precede and follow said first combining means in the compressor circuit and respectively follow and precede said second combining means in the expander circuit.
- 48. A system according to claim 46, wherein each difference signal is formed between a signal derived from a first point in the corresponding main circuit and a delayed version of a signal derived from a different point in the corresponding main circuit, and wherein the first point and different point respectively follow and precede said first combining means in the compressor circuit and respectively precede and follow said second combining means in the expander circuit.
- 49. A system according to claim 46, wherein each difference signal is formed between a signal derived from a point in the corresponding main path and a delayed version of the same signal, and wherein the said point precedes said first combining means in the compressor circuit and follows said second combining means in the expander circuit.
- 50. A system according to claim 46, wherein each difference signal is formed between a signal derived from a point in the corresponding main circuit and a delayed version of the same signal, and wherein the said point follows said first combining means in the compressor circuit and precedes said second combining means in the expander circuit.
- 51. A circuit for modifying, within a predetermined frequency band, the dynamic range of an input signal having an input dynamic range with a predetermined upper limit, comprising a main signal circuit responsive to said input signal to transmit, at least within the predetermined frequency band, a main signal component from an input terminal to an output terminal, said main signal circuit including combining means, and a further circuit including an electron beam tube, means for scanning the screen of the tube with a beam, means for modulating the beam in accordance with an input signal derived from a point in the main circuit, said scanning following a raster whose field period establishes a predetermined delay, and a circuit for coupling from the screen of the tube a difference signal generated as the scanning beam rewrites over the signal written in the preceding raster, and the further circuit having an output coupled from said coupling circuit to said combining means in the main circuit so as to combine with the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, and means for restricting the said difference signal to a predetermined amplitude which is not greater than about one-tenth the amplitude of the main component existing at the predetermined upper limit of the input dynamic range.
- 52. A circuit according to claim 51, wherein the electron beam tube is a charge storage tube comprising a circuit for draining charge from the screen of the tube and means for illuminating the screen of the tube substantially constantly and uniformly.
- 53. A circuit according to claim 52, comprising means for combining with the difference signal, as derived from the screen of the tube, such a proportion of the input signal as cancels the component of the difference signal created by the drain of charge during the said delay.
- 54. A circuit for modifying, within a predetermined frequency band, the dynamic range of an input signal having an input dynamic range with a predetermined upper limit, comprising a main signal circuit responsive to said input signal to transmit, at least within the predetermined frequency band, a main signal component from an input terminal to an output terminal, and a further circuit including means for delaying a second signal component derived from the main circuit, and means for forming within the predetermined frequency band the difference signal between a third signal component derived from the main circuit and the delayed version of the second signal component derived from the main circuit, the delay of the delayed second signal component delaying the second signal component relative to the third signal component, variable impedance means connected in the main circuit as a series element of the main circuit, and the further circuit having an output coupled to the variable impedance means in the main circuit so as to vary said variable impedance means to superimpose on the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, and means for restricting the said difference signal to a predetermined amplitude which is not greater than about one-tenth the amplitude of the main component existing at the predetermined upper limit of the input dynamic range.
- 55. A circuit according to claim 54, wherein the main signal circuit includes first and second impedance means connected in series with each other, current drive means series connected between the first and second impedance means and having a control terminal connected to said input terminal, said output terminal being connected between the current drive means and one of the first and second impedance means, the first impedance means including the series combination of said variable impedance means and a fixed impedance means, the further circuit having an input connected to a point between the fixed and variable impedance means and including means operative to form the difference signal between a signal component derived from said point and a delayed version of the same signal component, and the variable impedance means having a control terminal connected to the output of the further circuit.
- 56. A circuit according to claim 55, wherein the output terminal is connected between the current drive means and the first impedance means, the current drive means inverts the input signal, and the restricted difference signal reduces the conduction of the variable impedance means.
- 57. A circuit according to claim 55, wherein the output terminal is connected between the current drive means and the second impedance means, the current drive means inverts the input signal, the restricted difference signal reduces the conduction of the variable impedance means, and the first impedance means introduces variable negative feedback to the current drive means.
- 58. A method of modifying, within a predetermined frequency band, the dynamic range of an input signal having an input dynamic range with a predetermined upper limit, comprising the steps of providing, at least within the predetermined frequency band, a main signal component derived from the input signal, forming within the predetermined frequency band a difference signal between a second signal component derived from the input signal and a delayed version of a third signal component derived from the input signal, the delay of the delayed third signal component delaying the third signal component relative to the second signal component, combining the said difference signal with the main component to modify the main component when said difference signal exists, and restricting the said difference signal to a predetermined amplitude which is not greater than about one-tenth the amplitude of the main component existing at the predetermined upper limit of the input dynamic range.
- 59. A circuit for modifying, within a predetermined frequency band, the dynamic range of an input signal having an input dynamic range with a predetermined upper limit, comprising a drive circuit and a load circuit therefor, said drive circuit being responsive to said input signal to establish one of a voltage across and a current through said load circuit, and means for deriving an output signal from said load circuit in dependence upon the other of said voltage thereacross and current therethrough, said load circuit including first, non-variable impedance means providing a main signal component of said output signal and second, variable impedance means connected in series with said first impedance means providing a second, non-linear signal component of said output signal, said load circuit combining said main and second components to produce said output signal, said variable impedance means comprising means for deriving two signals from at least one point in said load circuit, delay means for delaying one of said two signals relative to the other means for forming the difference signal between the delayed signal and said other signal, means for restricting said difference signal to provide said second component of said output signal, and said restricting means restricting said difference signal so that said second signal component of said output signal is restricted to a predetermined amplitude which is not greater than about one-tenth of the amplitude of said main component of said output signal existing at said predetermined upper limit of the input dynamic range. .Iadd. 60. A method for processing an input signal, comprising deriving a main signal component of said input signal,
- deriving a second signal component from a signal that includes at least said main signal component,
- deriving a third signal component from a signal that includes at least said main signal component,
- delaying said third signal component relative to said second signal component,
- deriving a difference signal between said second signal component and said delayed third signal component,
- restricting said difference signal to an amplitude less than the amplitude of said main signal component, and
- combining said difference signal with said main signal component to provide an output signal. .Iaddend..Iadd. 61. A circuit for processing an input signal, comprising main signal circuit means, receiving said input signal, for carrying signals including at least a main signal component of said input signal,
- means for deriving a second signal component from a signal carried by said main signal circuit means,
- means for deriving a third signal component from a signal carried by said main signal circuit means,
- means for delaying said third signal component relative to said second signal component,
- means for deriving a difference signal between said second signal component and said delayed third signal component,
- means for restricting said difference signal to an amplitude less than said main signal component, and
- said main signal circuit means including means for combining said restricted difference signal with said main signal component. .Iaddend. .Iadd. 62. A circuit according to claim 61 wherein said main signal circuit means further includes means for deriving an output signal from said combining means. .Iaddend..Iadd. 63. A circuit according to claim 61 wherein at least one of said second and third signal components is derived from said input signal. .Iaddend..Iadd. 64. A circuit according to claim 62 wherein at least one of said second and third signal components is derived from said output signal. .Iaddend..Iadd. 65. A circuit according to claim 62 wherein one of said second and third signal components is derived from said input signal and the other of said second and third signal components is derived from said output signal. .Iaddend. .Iadd. 66. A noise reduction system having a circuit for processing an input signal, comprising
- main signal circuit means, receiving said input signal, for carrying signals including at least a main signal component of said input signal,
- means for deriving a second signal component from a signal carried by said main signal circuit means,
- means for deriving a third signal component from a signal carried by said main signal circuit means,
- means for delaying said third signal component relative to said second signal component,
- means for deriving a difference signal between said second signal component and said delayed third signal component,
- means for restricting said difference signal to an amplitude less than said main signal component,
- said main signal circuit means including means for combining said restricted difference signal with said main signal component, and
- switching means operable to place the processing circuit selectively in a compressor configuration in which said combining means combine said restricted difference signal in a sense such as to boost said main signal component and in an expander configuration in which said combining means combine said restricted difference signal in a sense such as to buck said main signal component. .Iaddend. .Iadd. 67. A noise reduction system for reducing noise in signals having a compressor circuit responsive to an input signal and feeding an information channel and an expander circuit fed by the information channel, the compressor circuit comprising
- first main signal circuit means, receiving said input signal, for carrying signals including at least a main, first signal component of said input signal,
- means for deriving a second signal component from a signal carried by said first main signal circuit means,
- means for deriving a third signal component from a signal carried by said first main signal circuit means,
- means for delaying said third signal component relative to said second signal component,
- means for deriving a first difference signal between said second signal component and said delayed third signal component,
- means for restricting said first difference signal to an amplitude less than said main, first signal component,
- said first main signal circuit means including means for combining said restricted first difference signal with said main, first signal component in a sense such that the restricted first difference signal boosts said main, first signal component when said difference signal exists,
- means for deriving an output signal from said first main signal circuit means, and
- the expander circuit comprising
- second main signal circuit means, receiving a second input signal derived from said compressor circuit output signal, for carrying signals including at least a main signal component of said second input signal,
- means for deriving a fifth signal component from a signal carried by said second main signal circuit means,
- means for deriving a sixth signal component from a signal carried by said second main signal circuit means,
- means for delaying said sixth signal component relative to said fifth signal component,
- means for deriving a second difference signal between said fifth signal component and said delayed sixth signal component,
- means for restricting said second difference signal to an amplitude less than said main signal component of
- said second input signal, and said second main signal circuit means including means for combining said restricted second difference signal with said main signal component of said second input signal in a sense such that the restricted second difference signal bucks said main signal component of said second input signal when said difference signal exists.
- .Iaddend..Iadd. 68. A circuit according to claim 67 wherein said second main signal circuit means further includes means for deriving an output signal from said combining means. .Iaddend. .Iadd. 69. A method for processing a main component of a signal comprising
- deriving a second signal component from a signal that includes at least said main signal component,
- deriving a third signal component from a signal that includes at least said main signal component,
- delaying said third signal component relative to said second signal component,
- deriving a difference signal between the second signal component and said delayed third signal component,
- restricting said difference signal to an amplitude less than the amplitude of said main signal component, and
- combining said restricted difference signal with said main signal component. .Iaddend..Iadd. 70. A circuit for processing a main component of a signal comprising
- main signal circuit means for carrying signals including at least said main signal component,
- means for deriving a second signal component from a signal carried by said main signal circuit means,
- means for deriving a third signal component from a signal carried by said main signal circuit means,
- means for delaying said third signal component relative to said second signal component,
- means for deriving a difference signal between said second signal component and said delayed third signal component,
- means for restricting said difference signal to an amplitude less than said main signal component, and
- said main signal circuit means including means for combining said restricted difference signal with said main signal component. .Iaddend. .Iadd. 71. A circuit for modifying the dynamic range of an input signal, comprising a main signal circuit responsive to said input signal to transmit a main signal component from an input terminal to an output terminal, the main signal circuit including combining means, delay means coupled to the main circuit for delaying a second signal component derived from the main circuit, and a further circuit including means for forming the difference signal between a third signal component derived from the main circuit and the delayed version of the second signal component derived from the main circuit, the delay of the delayed second signal component delaying the second signal component relative to the third signal component, and the output of said further circuit coupled to said combining means so as to combine with the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, and means for restricting the said difference signal to an amplitude which is not greater than about one-tenth the amplitude of the main component. .Iaddend. .Iadd. 72. A circuit for modifying the dynamic range of an input signal having an input dynamic range, comprising a main signal circuit responsive to said input signal to transmit a main signal component from an input terminal to an output terminal, the main signal circuit including combining means, and a plurality of further circuits, each including means for delaying a signal derived from a point in the main circuit, means for forming the difference signal between a signal derived from a point in the main circuit and its corresponding delayed signal derived from a point in the main circuit, and an output coupled to said combining means in the main circuit so as to combine with the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, and each further circuit including means for restricting the said difference signal thereof to an amplitude which is not greater than about one-tenth the amplitude of the main component. .Iaddend. .Iadd. 73. A noise reduction system comprising a circuit for modifying the dynamic range of an input signal, the circuit comprising a main signal circuit responsive to said input signal to transmit a main signal component from an input terminal to an output terminal the main signal circuit including combining means, delay means coupled to the main circuit for delaying a second signal component from the main circuit, and a further circuit including means for forming the difference signal between a third signal component derived from the main circuit and the delayed version of the second signal component derived from the main circuit, the delay of the delayed second signal component delaying the second signal component relative to the third signal component, and the further circuit having an output coupled to said combining means in the main circuit so as to combine with the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, means for restricting the said difference signal to an amplitude which is not greater than about one-tenth the amplitude of the main component, and switching means operable to place the dynamic range modifying circuit selectively in a compressor configuration in which said combining means combine said restricted difference signal in a sense such as to boost said main component and an expander configuration in which said combining means combine said restricted difference signal in a sense such as to buck said main component. .Iaddend. .Iadd. 74. A noise reduction system for reducing noise in signals within an input dynamic range and comprising a compressor circuit responsive to an input signal and feeding an information channel and an expander circuit fed by the information channel, the compressor circuit comprising a first main signal circuit responsive to said input signal to transmit a main, first signal component from an input terminal to an output terminal said first main signal circuit including first combining means, delay means coupled to the first main circuit for delaying a second signal component derived from the first main circuit, and a first further circuit including means for forming first difference signal between a third signal component derived from the first main circuit and the delayed version of the second signal component derived from the first main circuit and an output coupled to said first combining means in the first main circuit so as to combine with the main, first component the first difference signal, in a sense such that the first difference signal boosts the main, first component when said difference signal exists, and first means for restricting the first difference signal to an amplitude which is not greater than about one-tenth the amplitude of the first main component, and the expander circuit comprising a second main signal circuit responsive to a signal from said output terminal of said compressor circuit to transmit a main, fourth signal component from an input terminal to an output terminal said second main signal circuit including second combining means, delay means coupled to the second main circuit for delaying a fifth signal component derived from the second main circuit, and a second further circuit including means for forming a second difference signal between a sixth signal component derived from the second main circuit and the delayed version of the fifth signal component derived from the second main circuit, and an output coupled to said second combining means in the second main circuit so as to combine with the main, fourth component the second difference signal, in a sense such that the second difference signal bucks the second main component when said second difference signal exists, and second means for restricting the second difference signal to an amplitude which is not greater than about one-tenth the amplitude of the second main component. .Iaddend..Iadd. 75. A circuit for modifying the dynamic range of an input signal having an input dynamic range comprising a main signal circuit responsive to said input signal to transmit a main signal component from an input terminal to an output terminal, said main signal circuit including combining means, and a further circuit including an electron beam tube, means for scanning the screen of the tube with a beam, means for modulating the beam in accordance with an input signal derived from a point in the main circuit, said scanning following a raster whose field period establishes a predetermined delay, and a circuit for coupling from the screen of the tube a difference signal generated as the scanning beam rewrites over the signal written in the preceding raster, and the further circuit having an output coupled from said coupling circuit to said combining means in the main circuit so as to combine with the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, and means for restricting the said difference signal to an amplitude which is not greater than about one-tenth the amplitude of the main component. .Iaddend. .Iadd. 76. A circuit for modifying the dynamic range of an input signal having an input dynamic range, comprising a main signal circuit responsive to said input signal to transmit a main signal component from an input terminal to an output terminal, and a further circuit including means for delaying a second signal component derived from the main circuit, and means for forming the difference signal between a third signal component derived from the main circuit and the delayed version of the second signal component derived from the main circuit, the delay of the delayed second signal component delaying the second signal component relative to the third signal component, variable impedance means connected in the main circuit as a series element of the main circuit, and the further circuit having an output coupled to the variable impedance means in the main circuit so as to vary said variable impedance means to superimpose on the main component the said difference signal, which difference signal modifies the main component when said difference signal exists, and means for restricting the said difference signal to an amplitude which is not greater than about one-tenth the amplitude of the
- main component. .Iaddend..Iadd. 77. A method of modifying the dynamic range of an input signal, comprising the steps of providing a main signal component derived from the input signal, forming a difference signal between a second signal component derived from the input signal and a delayed version of a third signal component derived from the input signal, the delay of the delayed third signal component delaying the third signal component relative to the second signal component, combining the said difference signal with the main component to modify the main component when said difference signal exists, and restricting the said difference signal to an amplitude which is not greater than about one-tenth the amplitude of the main component. .Iaddend..Iadd. 78. A circuit for modifying the dynamic range of an input signal, comprising a drive circuit and a load circuit therefor, said drive circuit being responsive to said input signal to establish one of a voltage across and a current through said load circuit, and means for deriving an output signal from said load circuit in dependence upon the other of said voltage thereacross and current therethrough, said load circuit including first, non-variable impedance means providing a main signal component of said output signal and second, variable impedance means connected in series with said first impedance means providing a second, non-linear signal component of said output signal, said load circuit combining said main and second components to produce said output signal, said variable impedance means comprising means for deriving two signals from at least one point in said load circuit, delay means for delaying one of said two signals relative to the other, means for forming the difference signal between the delayed signal and said other signal, means for restricting said difference signal to provide said second component of said output signal, and said restricting means restricting said difference signal so that said second signal component of said output signal is restricted to an amplitude which is not greater than about one-tenth of the amplitude of said main component of said output signal. .Iaddend.
Priority Claims (1)
| Number |
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| 15484/72 |
Apr 1972 |
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Parent Case Info
This application is a Continuation in Part of our application Ser. No. 346,689 filed Mar. 30, 1973, now abandoned.
This invention relates to signal encoding and decoding circuits the action of which are similar to those of the compressors and expanders described in British patent specifications Nos. 1,120,541 and 1,253,031, both in the name of Ray Milton Dolby, and to combined encoding/decoding circuits, i.e. noise reduction circuits. In such compressors and expanders a main signal component is transferred by a so-called main path from an input terminal to an output terminal, the main path having the characteristic at least of dynamic range linearity at any frequency within the band handled by the compressor or expander. The main path is preferably linear in all respects such that the main signal component is proportional on an instantaneous basis to the input signal. The main component is boosted in the case of a compressor or bucked in the case of an expander by one or more further components provided by so-called further paths, having one or more inputs connected to points in the main path and outputs connected to one or more combining means in the main path. The combining means combine the components in the sense appropriate to boosting or bucking, as the case may be.
Under low signal variation conditions, the further components significantly boost or buck the main component, to which end the further paths have suitable gain relative to the main path. However, the further paths have strong limiting characteristics. Each further path characteristic is generally linear up to a limiting threshold, which will usually be at least an order of magnitude (and preferably two orders of magnitude) below the nominal peak to peak signal level. The further components moreover do not under any conditions exceed a level which is greater than about one-tenth of the nominal peak to peak level of the main component. With large amplitude signals, the boosting or bucking action becomes insignificant with reference to the maximum signal amplitude, whereby a transfer characteristic which is linear with respect to dynamic range obtains.
The compressors (encoders) and expanders (decoders) based upon these principles are typically (though not necessarily) used together in complete noise reduction systems.
The main operative principle in the Applicant's signal processing devices is that a dynamically unmodified or main signal component is linearly combined with a dynamically modified component. The main signal component is derived from the input, and the modified component is produced by a dynamic modification circuit, the input of which is derived from one or more signals in the device, and ultimately from the input. The circuit realisations of this concept are many and varied, but the simplest for discussion purposes, as well as most straight forward in application, is the parallel path form, the paths are fed from conventional voltage inputs and produce conventional voltage outputs.
It is also possible to realise the invention in a series form, whereby the input signal may be applied as a current or a voltage to an impedance network, at least part of which is variable in response to one or more signals in the network. If a current is applied, the output signal is derived from the voltage across the network. If a voltage is applied, the output signal is derived from the current through the network. In practice, the same dynamic modification circuit is used as in the parallel path form; however, the input, output, and signal combining arrangements are such that the overall circuit can be thought of as a two-terminal impedance network or a series combination of two-terminal impedance networks. It is also possible to apply a current to a parallel combination of impedance networks, at least one of which is variable in response to one or more signals in the combination; the output signal is derived from the voltage across the combination or from the current through one or more of the impedance network branches.
Thus, the important feature of the invention is not so much the input, output, or combination methods, but that, in one way or another, a main or dynamically unmodified signal should be transferred from the input to the output, with subsequent signal accuracy and freedom from distortion; the dynamic modifications for noise reduction need take place only at low levels, which allows a boosting or bucking technique to be used, whether with voltages, currents or impedance components.
A problem which arises with any compressors or expanders is that the signal to be processed may include components which effectively block the compressing or expanding action. For instance, if the signal is a repetitive signal such as a video signal, the frequency spectrum contains substantial components at the picture and line repetition frequencies and harmonics thereof, e.g. 25 Hz and its harmonics and 15.625 KHz its harmonics in the case of a 625 line, 50 fields per second television signal. If such components are spread throughout any part of a band within which noise reduction is required, their presence may cause the output of the further path to limit, thereby blocking noise reduction action. For example, if noise reduction is attempted at low frequencies, large variation signal components are inevitably present at 25 Hz, 50 Hz, and so on and at 15.625 KHz, 31.250 KHz, and so on and the presence of these components will bring the limiting characteristics of the further paths into play and thereby prevent the significant boosting and bucking necessary to create the compressor and expander action.
The object of the present invention is to provide signal encoders and decoders capable of providing compressor and expander action in the presence of large variation signals which have a defined, and generally non-continuous, frequency spectrum. It will be convenient to refer to the encoders and decoders generically as circuits for modifying the dynamic range of a signal.
According to the present invention there is provided a circuit for modifying the dynamic range of a signal, comprising a main signal path arranged to transmit a main signal component with dynamic range linearity from an input terminal to an output terminal, and a further path including means for forming the difference signal between a signal derived from a point in the main path and a delayed version of a signal derived from a point in the main path, and an output connected to combining means in the main path so as to combine with the main component the said difference signal, which difference signal either boosts or bucks the main component appreciably under low signal variation conditions, and means for restricting the said difference signal to a predetermined amplitude which is not greater than about one-tenth of the level of the maximum amplitude of the main component.
In order to process a repetitive signal, the delay means introduces a delay period equal to the period of the fundamental repetition frequency, or an integral multiple of this frequency. Provided the gains via the two further path inputs are substantially equal, components at the fundamental repetition frequency and harmonics thereof (referred to together as the cancellation frequencies) will cancel out, i.e. will not appear in the said difference, and will accordingly not choke the encoder or decoder. As will be explained below, several different delays can be used, with delays which are different integral multiples of the aforesaid delay period.
In order to avoid the possibility of self oscillation, the present invention preferably employ the configuration described as Type 2 in British specification No. 1,253,031, in which the undelayed or direct further path input is connected, in the case of the encoder, to the output side of the combining means in the main path, and in the case of the decoder to the input side of these combining means. If the further path gain in this configuration is 0.684 below the aforementioned limiting threshold, the amount of compression or expansion varies from zero at the cancellation frequencies to a maximum of 14.5 dB at frequencies midway between adjacent cancellation frequencies.
For processing television signals, a suitable delay is one or more field periods, although this requires expensive delay means if adequate time-stability is to be achieved. Good results are also obtained using one or more line delays for both chrominance and luminance components in the case of NTSC signals (and two-line delays for chrominance and one-line delays for luminance in the case of PAL signals). It is furthermore possible to use closed loop control to maintain the delays at the correct values, as explained below.
The invention is not restricted to use of delays related to a repetition frequency. For example, the delays can be short compared with the periods of the major information components of a signal, which will thereby be excluded from the compressor or expander action. In a television system, such delays can range from a fraction of a microsecond to several microseconds, for example. The action of the invention will be confined to higher frequency components, such components typically including the major noise components required to be reduced by complementary compressor and expander action.
US Referenced Citations (2)
| Number |
Name |
Date |
Kind |
|
3117278 |
Johnson |
Jan 1964 |
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|
3875584 |
Fletcher et al. |
Apr 1975 |
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Continuation in Parts (1)
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Number |
Date |
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| Parent |
346689 |
Mar 1973 |
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Reissues (1)
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Number |
Date |
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| Parent |
477205 |
Jun 1974 |
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Patent Grant
RE30468
