Claims
- 1. A receiver comprising:
a) a phase adjustment circuit changing a phase of received signals; b) a transformation processor deriving frequency domain representations of phase-adjusted signals from the phase adjustment circuit; c) a derotator applying a rotation to an output of the transformation processor to counteract any adjustment applied by the phase adjustment circuit; and d) a channel estimator estimating channel characteristics based upon an output of the derotator.
- 2. The receiver of claim 1, wherein the transformation processor operates with a processor window having a window position, and wherein the phase adjustment circuit is configured to adjust phase by changing the window position of the transformation processor.
- 3. The receiver of claim 2, wherein the phase adjustment circuit further adjusts phase by changing a timing of received signal sampling to align sample timing to a determined feature of the received signal.
- 4. The receiver of claim 3, further comprising an input section configured to provide baseband signals to a resampler that provides I and Q components of the received signal for processing by the transformation processor, wherein the phase adjustment circuit controls sample timing of the resampler and window position for the transformation processor.
- 5. The receiver of claim 4, further comprising a cyclic component removal processor configured to receive the I and Q components from the resampler, and to provide to the transformation processor a portion of the I and Q components that does not include cyclic components.
- 6. The receiver of claim 1, wherein the phase adjustment circuit introduces phase changes by changing a timing of received signal sampling to align sample timing to a determined feature of the received signal.
- 7. The receiver of claim 6 wherein the phase adjustment circuit includes a resampler for forming digital samples of the received signal, and is configured to adjust a sample position of the resampler.
- 8. The receiver of claim 1, wherein the phase adjustment circuit introduces phase changes by changing a window position of timing of received signal sampling to align sample timing to a determined feature of the received signal.
- 9. The receiver of claim 1, wherein the receiver apparatus is configured to receive COFDM television signals.
- 10. A method of processing a received signal, comprising:
a) shifting a phase of the received signal to generate a phase shifted signal; b) Fourier transforming information from the phase shifted signal to generate phase shifted transformed signal information; c) derotating the phase shifted transformed signal information as compensation for phase shifting in step a) to generate derotated signal information; and d) applying the derotated signal information to a channel estimator.
- 11. The method of claim 10, wherein the act of a) shifting a phase of the received signal comprises adjusting sample timing of the received signal to effect alignment of samples to a signal feature.
- 12. The method of claim 10, wherein the act a) of shifting a phase of the received signal comprises changing a window position of a Fast Fourier Transform (“FFT”) processor.
- 13. The method of claim 12, wherein the act a) of shifting a phase of the received signal further comprises aligning sample timing of a resampler to cause the phase shifted signal to be aligned for cyclic information removal.
- 14. The method of claim 13, further comprising a step e) removing cyclic information from the aligned phase shifted signal to generate information from the phase shifted signal for the Fourier transformation of step b).
- 15. A communication signal receiving system, comprising:
a) a sampling block configured to derive samples of a received signal; b) a phase adjustment block configured to adjust a phase of the received signal by changing sample timing of the sampling block to align the sample timing; c) a cyclic section removal block configured to derive stripped signal information for further processing by removing cyclic sections from the derived samples; and d) a derotator block configured to compensate for phase adjustment imposed by the phase adjustment block by rotating phasing of the stripped signal information to provide derotated signal information.
- 16. The system of claim 15, further comprising a channel estimation block configured to derive channel estimates from the derotated signal information.
- 17. The system of claim 15, further comprising a Fast Fourier Transform (“FFT”) processor for providing the stripped signal information in frequency domain form to the derotator block.
- 18. The system of claim 17, wherein the phase adjustment block is configured to further adjust the phase of the received signal by changing a window position of the FFT processor.
- 19. The system of claim 18, further comprising a channel estimation block configured to derive channel estimates from the derotated signal information.
- 20. The system of claim 19, further comprising an equalizer, a demultiplexer, and a decoder.
- 21. The system of claim 15, wherein the sampling block is configured to derive I and Q component samples.
- 22. The system of claim 15, wherein the phase adjustment block is configured to align the sample timing with a feature of the received signal.
- 23. A method of processing a received signal, comprising:
a) shifting a phase of the received signal with a controller to align received signal samples; b) removing cyclic information from the received signal samples to produce cyclically stripped signal information; c) derotating the cyclically stripped signal information to compensate for any phase shifting in step a); and d) decoding signal information resulting from step c).
- 24. The method of claim 23, wherein the step d) comprises performing channel estimation.
- 25. The method of claim 24, wherein the step a) comprises adjusting sample timing of a resampler to align the samples with an actual start position of the received signal.
- 26. The method of claim 23, further comprising a step e) performing a Fourier transformation of the stripped signal information.
- 27. The method of claim 26, wherein the step c) comprises performing a complex multiplication.
- 28. The method of claim 27, wherein the step e) comprises employing a Fast Fourier Transform (“FFT”) processor, and the step a) further comprises adjusting a window position of the FFT processor.
- 29. The method of claim 23, further comprising mixing the received signal down to baseband before performing any of the steps a), b), c) or d).
- 30. A receiver comprising:
a) means for adjusting a phase of received signals to produce phase adjusted signals; b) means for deriving frequency domain (“FD”) representations of the phase-adjusted signals; c) means for derotating the FD representations of the phase adjusted signals to counteract phase adjustment applied to the received signals by means (a) to produce derotated signals; and d) means for estimating channel characteristics based upon the derotated signals.
- 31. The receiver of claim 30, wherein the means for deriving FD representations of the phase-adjusted signals comprises means for shifting a Fourier Transformation window position to adjust phase of the phase adjusted signals.
- 32. The receiver of claim 30, wherein the means for adjusting a phase of received signals comprises means for changing a timing of received signal sampling to align sample timing to a determined feature of the received signal.
Priority Claims (2)
Number |
Date |
Country |
Kind |
PCT/GB00/04001 |
Oct 2000 |
WO |
|
0017132.2 |
Jul 2000 |
GB |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the effective filing date under 35 USC §§ 120 and 363 to PCT International Application. No. PCT/GB00/04001, entitled “Television Receiver”, filed Oct. 18, 2000 designating the U.S. and published under PCT Article 21(2) in English as International Publication No. WO 02/05550 A1 entitled “Television Receiver,” of which this application is a continuation, which PCT application claims priority to Great Britain Patent Application No. 0017132.2, filed Jul. 12, 2000. This application claims priority under 35 USC 119(a) to Great Britain Patent Application No.: 0017132.2, filed Jul. 12, 2000.