Patent Application
20120313671
The present invention relates to a signal generation device and a signal generation method that generate a signal whose sampling frequency has been converted based on a sampled input signal.
In radio communications and the like, sampling frequency conversion is sometimes performed for converting a signal having been sampled at one sampling frequency, into a signal having been sampled at another sampling frequency. A conventional sampling-frequency conversion method is explained below. A case of performing sampling frequency conversion by using an oversampling polyphase filter is explained here.
The oversampling polyphase filter is a filter used for generating a signal whose sampling frequency has been increased M times, and in order to form a filter H having desired filter characteristics, M filter banks for which a tap coefficient is respectively set are used. By selecting a signal output from each filter bank periodically at an equal time interval and providing the selected signal as an output signal, a filtering process and the sampling frequency conversion can be performed.
For example, when M is 4, an input signal sampled at a predetermined sampling interval is input to each of M (four) sub-filters. The tap coefficients of the four sub-filters are obtained by extracting the tap coefficients of the desired filter H at an equal interval so that an origin of extraction is shifted for each filter. When the four sub-filters are represented as F1 to F4 and sets of the tap coefficients of F1 to F4 are H0={h(0,0), h(0,1), h(0,2), h(0,3), h(0,4)}, H1={h(1,0), h(1,1), h(1,2), h(1,3), h(1,4)}, H2={h(2,0), h(2,1), h(2,2), h(2,3), h(2,4)}, and H3={h(3,0), h(3,1), h(3,2), h(3,3), h(3,4)}, respectively, an impulse response of the filter H corresponding to 4-times oversampling becomes {h(0,0), h(1,0), h(2,0), h(3,0), h(0,1), h(1,1), . . . }. In this case, an FIR filter is assumed, and the tap coefficients of each filter bank are set based on the impulse response of the filter H corresponding to the 4-times oversampling.
As described above, by setting the tap coefficients of the filter banks corresponding to characteristics of the filter H and sequentially selecting the outputs from the four filter banks, which are F1, F2, F3, and F4, at an equal time interval within a sampling period of the input signal, it is possible to obtain an output signal whose sampling frequency has been converted into a four-times higher frequency.
Non Patent Literature 1: Nishimura, “Communication system design by digital signal processing”, CQ Publishing Co., Ltd., pp. 79-89 (June 2006)
However, according to the conventional sampling conversion method using a polyphase filter, there is a problem that, when an output signal is converted into an arbitrary sampling frequency, it is necessary to change the sampling frequency of an input signal as well as a frequency of an operation clock used for the sampling conversion.
Furthermore, to set the sampling frequency of the output signal to an arbitrary value when the operation clock frequency is fixed, it is necessary to use a plurality of polyphase filters for the oversampling and downsampling in combination. Therefore, there is a problem that the number of arithmetic operations is increased, and a memory size becomes large because the number of candidates of the tap coefficients of the polyphase filters is increased.
Further, in order to set the sampling frequency of the output signal to an arbitrary value when the operation clock frequency is fixed, it is necessary to use a plurality of filter banks corresponding to the sampling frequency of the output signal when the polyphase filters are constituted, and this causes a problem that the number of arithmetic operations is increased and a circuit size is enlarged.
The present invention has been achieved in view of the above problems, and an object of the present invention is to provide a signal generation device that can perform sampling frequency conversion at an arbitrary rate with a simple configuration, and a signal generation method.
In order to solve the above problem and in order to attain the above object, a signal generation device of the present invention, includes: a filtering unit that performs sampling frequency conversion with respect to an input signal of a predetermined sampling frequency, and generates a signal obtained after the sampling frequency conversion as an output signal; and a control unit that selects, based on a sampling-frequency setting value indicating a sampling frequency of the output signal, a combination of tap coefficients used by the filtering unit from a plurality of combinations of tap coefficients determined in advance. Additionally, the filtering unit generates the sampling frequency conversion based on a result of selection by the control unit.
According to the signal generation device and the signal generation method of the present invention, a frequency of a high-speed operation clock is fixed, a filter bank unit is provided, a filter control unit selects sets of the tap coefficients to be set for the filter bank unit, based on a ratio between the frequency of the high-speed operation clock and a sampling frequency of an output signal, and the output obtained after the filter bank unit performs filtering using the selected sets of the tap coefficients is handled as an output signal obtained after sampling conversion, so that it is possible to perform sampling frequency conversion at an arbitrary rate with a simple configuration.
Exemplary embodiments of a signal generation device and a signal generation method according to the present invention will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments.
As shown in
The configuration of the filter banks 2-0 to 2-(L-1) is identical to that of a general FIR (Finite Impulse Response) filter. The shift register 10 generates signals Xn, Xn−1, Xn−2, Xn−3, and Xn−4 that have been delayed from the input signal Xn by one sample relative to each other. The multiplier 11-0 multiplies Xn by a tap coefficient C0, the multiplier 11-1 multiplies Xn−1 by a tap coefficient C1, the multiplier 11-2 multiplies Xn−2 by a tap coefficient C2, the multiplier 11-3 multiplies Xn−3 by a tap coefficient C3, and the multiplier 11-4 multiplies Xn−4 by a tap coefficient C4. The adder 12 adds outputs from the multipliers 11-0 to 11-4 together, and then outputs them to the switching unit 4.
Generally, in frequency conversion using a conventional polyphase filter, the operation clock frequency is the same as a sampling frequency of an output signal (a converted sampling frequency obtained after sampling frequency conversion), and by switching the filter banks based on the operation clock (switching among the filter banks to be selected as the output signal), the output signal of the converted sampling frequency can be generated.
On the other hand, in the present embodiment, the sampling frequency fout of a plurality of output signals is handled while the high-speed operation clock frequency fclk is fixed, and therefore fclk and fout are not necessarily the same. Accordingly, in the present embodiment, the filter banks to be selected are changed according to the ratio fclk/fout. In this example, L is 16, and the sampling frequency can be converted into a maximum frequency of 16 times with respect to the input signal Xn. Therefore, it suffices that the high-speed operation clock frequency fclk is higher than the sampling frequency 16 times as high as that of the input signal, and in this example, the high-speed clock frequency fclk is the sampling frequency 16 times as high as the input signal. In addition, in this example, the sampling frequency of the input signal Xn is fixed.
Based on the above assumption, when the ratio fclk/fout is 4, the sampling frequency four times as high as that of the input signal is obtained after conversion. Thus, four filter banks are used for the sampling frequency conversion. In this example, four of the filter banks 2-0, 2-4, 2-8, 2-12 (H0, H4, H8, H12) are to be selected. For the filter banks 2-0 to 2-(L-1), it is assumed that sets of the tap coefficients H0 to HL−1, which are obtained by extracting the tap coefficients of a desired filter characteristic H that correspond to each filter bank, are set. In this example, because the number of taps is five, the number of the tap coefficients set for each filter bank is five (C0, C1, C2, C3, and C4).
Accordingly, the tap coefficients can be represented as H0={h(0,0), h(0,1), h(0,2), h(0,3), h(0,4)}, H1={h(1,0), h(1,1), h(1,2), h(1,3), h(1,4)}, H2={h(2,0), h(2,1), h(2,2), h(2,3), h(2,4)}, . . . , H4={h(4,0), h(4,1), h(4,2), h(4,3), h(4,4)}, . . . , H15={h(15,0), h(15,1), h(15,2), h(15,3), h(15,4)}. Furthermore, H0 to HL−1 are sets of tap coefficients that are extracted at an equal interval (an interval of L) from all the tap coefficients corresponding to the desired filter characteristic H so that an origin of the tap coefficients of each filter is shifted by one point from each other, and that are obtained by polyphase decomposition of the desired filter characteristic H.
As shown in
In the present embodiment, the sampling frequency fout of the output signal is set in the control-signal generation unit 3, the control-signal generation unit 3 generates a control signal transmitted to the switching unit 4 based on fout as described later, and the switching unit 4 switches among the filter banks to be selected based on the control signal. Processing of the control-signal generation unit 3 is explained below.
The control-signal generation unit 3 operates on a high-speed operation clock (the frequency fclk). A sampling-frequency setting (phase), which is a value determined by a ratio between the high-speed clock frequency and an output sampling frequency, is input to the control-signal generation unit 3. It is assumed that the output sampling frequency is input to the control-signal generation unit 3, so that the control-signal generation unit 3 can calculate the sampling frequency setting (phase). A sampling frequency setting (phase) ΔP is a value obtained by a calculation of the following expression (1). Note that ΔP does not necessarily need to be an integer.
ΔP=L/(fclk/fout) (1)
In this example, the ratio fclk/fout is 4, and the sampling frequency setting (phase) ΔP becomes 4 accordingly.
In the present embodiment, a phase of 0 to 2π is expressed as a value having been converted into a linear value of 0 to (L-1), and ΔP is expressed as a converted phase. Based on the input sampling frequency setting (phase), the phase generation unit 31 integrates the phase and outputs as an output phase a result (0 to (L-1)) obtained by applying modulo-L arithmetic to the integral.
Specifically, the phase generation unit 31 determines an output phase P(k) from the following expression (2) based on ΔP, for example. Note that an initial value S(0) is 0.
S(k)=F{S(k−1)+ΔP}
P(k)=modulo{S(k), L} (2)
Reference sign F(·) denotes a function used for rounding off fractions, and k denotes a sample number of the output signal. Accordingly, it suffices to calculate P(k) once for every 4 (=fclk/fout) pulses of a high-speed clock. Note that F(·) can be a function for rounding down the fractions for simplicity of the arithmetic operation.
The phase generation unit 31 outputs the output phase P(k) to the shift-register enable generation unit 32 and the filter control unit 33. Based on the output phase P(k), the filter control unit 33 selects the filter bank 2-j determined from j=P(k) every time P(k) is updated (that is, once for 4 (=fclk/fout) periods of the high-speed clock), and outputs to the switching unit 4 a control signal for instructing to output the signal Y. (m is the sample number) having the filtering processing of the selected filter bank 2-j performed thereon. The switching unit 4 performs switching of filter banks based on this control signal.
Based on the output phase P(k), the shift-register enable generation unit 32 generates a shift-register enable pulse for instructing updating of contents in the shift register 10 of the filter banks 2-0 to 2-(L-1). Based on the shift-register enable pulse, the filter banks 2-0 to 2-(L-1) update a value of the shift register 10 to another value derived from the next (next sample) input signal. A method of generating the shift-register enable pulse of the shift-register enable generation unit 32 can be any method as long as it is for generating a shift-register enable pulse once for every sampling period of an input signal. As an example, it is assumed that the output phase P(k) is compared to a predetermined threshold a in the unit of high-speed clock cycles, and when P(k) becomes equal to or larger than a, a pulse is generated at every high-speed clock unit.
Furthermore, a is L/2=8 in
In the case of the example in
As described above, in the present embodiment, S(k) is set to be an integer (by rounding off or rounding down the number), and then the filter bank to be selected is determined, thereby handling a case where the ratio between the high-speed operation clock frequency and the sampling frequency of the output signal is not an integral multiple. Therefore, even with a limited number of filter banks, it is possible to correspond to the sampling frequency of any output signal with a small error.
In the present embodiment, ΔP is used to determine the filter banks 2-0 to 2-(L-1) to be selected; however, other methods not using ΔP can be employed as long as selecting (switching) similar to that of the above method is performed based on the ratio between the high-speed operation clock frequency and the sampling frequency of the output signal.
When the filter banks 2-0 to 2-(L-1) and the switching unit 4 in the present embodiment are assumed as a single filtering unit, the control-signal generation unit 3 can be deemed to give this filtering unit an instruction of sets of the tap coefficients that are set for the filter banks 2-0 to 2-(L-1) selected as the output signal, when the filter banks 2-0 to 2-(L-1) are selected.
In the present embodiment, the filter banks 2-0 to 2-(L-1) to be selected are determined based on ΔP, which is the ratio between the high-speed operation clock frequency and the sampling frequency of the output signal; however, a method of determining the filter banks is not limited thereto and can be any method as long as it determines the filter banks 2-0 to 2-(L-1) based on the sampling frequency of the output signal.
As described above, in the present embodiment, the high-speed operation clock frequency is fixed, L filter banks 2-0 to 2-(L-1) corresponding to a maximum oversampling ratio L are provided, the phase generation unit 31 determines and gives an instruction for the filter banks 2-0 to 2-(L-1) to be selected, based on the ratio between the high-speed operation clock frequency and the sampling frequency of the output signal, and the switching unit 4 selects an output from the filter banks 2-0 to 2-(L-1) based on the instruction, and then outputs the selected one. Therefore, without combining a plurality of polyphase filters for upsampling and downsampling and with a simple configuration, sampling frequency conversion can be performed at any oversampling ratio not exceeding a maximum oversampling ratio while a high-speed operation clock frequency is fixed.
Differences from the first embodiment are explained below. The control-signal generation unit 5 is constituted by a phase generation unit 51, a shift-register enable generation unit 52, and a tap-coefficient generation unit (filter control unit) 53. In the present embodiment, it is assumed that an operation is performed at the high-speed clock fclk corresponding to a maximum oversampling ratio. In the second embodiment, the maximum oversampling ratio L (resolution) is explained as 16.
Similarly to the phase generation unit 31 according to the first embodiment, the sampling frequency setting (phase) ΔP, which is determined based on the ratio between the high-speed clock frequency and the output sampling frequency, is input to the phase generation unit 51 of the control-signal generation unit 5. The method of calculating ΔP is the same as that in the first embodiment. When L is 16 and the ratio fclk/fout is 4, ΔP is 4. The phase generation unit 51 determines the output phase P(k) similarly to the phase generation unit 31 in the first embodiment, and then outputs to the shift-register enable generation unit 52 and the tap-coefficient generation unit 53.
An operation of the shift-register enable generation unit 52 is identical to that of the shift-register enable generation unit 32 according to the first embodiment. The tap-coefficient generation unit 53 holds the sets of the tap coefficients H0 to H12 shown in the first embodiment. The tap-coefficient generation unit 53 selects the set Hj of the tap coefficients corresponding to j=P(k) based on the output phase P(k), and then outputs the selected set of the tap coefficients to the coefficient multiplication unit 13 of the filter bank 2. The coefficient multiplication unit 13 of the filter bank 2 sets the set of the tap coefficients output from the tap-coefficient generation unit 53 as the tap coefficients (C0 to C4). A signal having the filtering using the set of the tap coefficients Hj performed thereon is output from the filter bank 2, as the output signal Ym obtained after the sampling frequency conversion. Operations of the present embodiment except for those explained above are identical to those of the first embodiment.
As described above, in the present embodiment, one filter bank 2 is provided, the tap-coefficient generation unit 53 holds the sets of the tap coefficients Ho to H12, the set of the tap coefficients is selected based on P(k) calculated similarly to the first embodiment, and the coefficient multiplication unit 13 in the filter bank 2 sets the selected set of the tap coefficients. Therefore, the use of even one filter bank can achieve effects identical to those of the first embodiment, so that the configuration in the present embodiment can be simplified as compared to the first embodiment.
In the present embodiment, the sampling frequency setting (phase) ΔP is averaged and then input to the control-signal generation unit 3 according to the first embodiment or the control-signal generation unit 5 according to the second embodiment. While any configuration and method can be used for the configuration of the averaging processing unit 7 and for the averaging method thereof, in the present embodiment, an example of using an IIR (Infinite Impulse Response) filter is explained.
In the present embodiment, it is assumed that ΔP is input to the phase generation unit 51 and is averaged; however, when the sampling frequency of the output signal is input to the phase generation unit 51, the sampling frequency of the output signal is averaged.
As described above, in the present embodiment, by averaging the sampling frequency setting (phase) ΔP in advance, ΔP can be smoothly varied and the output sample signal can be also smoothly varied continuously. Therefore, the present embodiment can achieve effects identical to those in the first embodiment or the second embodiment, and when noise and the like are added on the sampling frequency setting (phase) or when the sampling frequency setting (phase) is changed at a midpoint, it is possible to smoothly vary the output signal.
As described above, the signal generation device and the signal generation method according to the present invention are suitable for a signal generation device that generates a signal whose sampling frequency has been converted based on a sampled input signal, and are particularly suitable for a case where a converted sampling frequency of a signal is not fixed.
1, 1a, 1b signal generation device
2, 2-0 to 2-(L-1) filter bank
3, 5 control-signal generation unit
4 switching unit
6 signal generation unit
7 averaging processing unit
10 shift register
11-0 to 11-4 multiplier
12 adder
13 coefficient multiplication unit
31, 51 phase generation unit
32, 52 shift-register enable generation unit
33 filter control unit
53 tap-coefficient generation unit
71, 73 multiplier
72 adder
74 delay unit
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-009070 | Jan 2010 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2011/050543 | 1/14/2011 | WO | 00 | 7/19/2012 |
