Claims
- 1. A circuit for enhancing a signal on a signal line, the signal line having a near end and a far end, the circuit comprising:
- a p-channel transistor having a source connected to a positive voltage supply, and a drain connected to the signal line far end;
- a first logic gate having an output connected to a gate of the p-channel transistor, and having a first input connected to the signal line far end;
- a first delay circuit having an input connected to the signal line far end, and having an output connected to a second input of the first logic gate;
- an n-channel transistor having a source connected to a negative voltage supply, and a drain connected to the signal line far end;
- a second logic gate having an output connected to a grate of the n-channel transistor, and having a first input connected to the signal line far end; and
- a second delay circuit having an input connected to the signal line far end, and having an output connected to a second input of the second logic gate;
- wherein the first logic gate operates to turn on the p-channel transistor when a voltage at the signal line far end rises above a first threshold voltage, for a time period determined by the first delay circuit;
- and wherein the second logic gate operates to turn on the n-channel transistor when a voltage at the signal line far end falls below a second threshold voltage, for a time period determined by the second delay circuit.
- 2. The circuit of claim 1, wherein the first logic gate comprises a NAND gate, and the second logic gate comprises a NOR gate.
- 3. The circuit of claim 2, wherein the first and second delay circuits each comprises an odd number of inverters in series.
- 4. The circuit of claim 3, wherein the first and second delay circuits each comprise three inverters in series.
- 5. The circuit of claim 3, wherein the first and second delay circuits each have the same number of inverter stages.
- 6. The circuit of claim 1, wherein the first input of the first logic gate has a threshold voltage which is lower than a threshold of the first input of the second logic gate.
- 7. The circuit of claim 1, further comprising:
- a second signal line having a first end adjacent the near end and a second end adjacent the far end;
- a second p-channel transistor having a source connected to the positive voltage supply, a drain connected to the second end, and a gate connected to the first logic gate output; and
- a second n-channel transistor having a source connected to the negative voltage supply, a drain connected to the second end, and a gate connected to the second logic gate output.
- 8. The circuit of claim 7, wherein the first logic gate comprises a NAND gate, and the second logic gate comprises a NOR gate.
- 9. The circuit of claim 8, wherein the first and second delay circuits each comprise an odd number of inverters in series.
- 10. The circuit of claim 9, wherein the first and second delay circuits each comprise three inverters in series.
- 11. The circuit of claim 9, wherein the first and second delay circuits each have the same number of inverter stages.
- 12. The circuit of claim 7, wherein the first input of the first logic gate has a threshold voltage which is lower than a threshold of the first input of the second logic gate.
Parent Case Info
This is a continuation of application Ser. No. 07/823,680, filed Jan. 21, 1991, now abandoned.
US Referenced Citations (9)
Continuations (1)
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Number |
Date |
Country |
Parent |
823680 |
Jan 1992 |
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