Signal line selection and polarity change of natural bit ordering in high-speed serial bit stream multiplexing and demultiplexing integrated circuits

Abstract

A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits. These circuits include an interface that may be ordered, have signal line polarities altered, or bit asserted states altered depending upon the particular implementation.

Description

BACKGROUND OF THE INVENTION

[0002] 1. Technical Field of the Invention

[0003] The present invention relates generally to communication systems; and more particularly to high-speed serial bit stream communications.

[0004] 2. Description of Related Art

[0005] The structure and operation of communication systems is generally well known. Communication systems support the transfer of information from one location to another location. Early examples of communication systems included the telegraph and the public switch telephone network (PSTN). When initially constructed, the PSTN was a circuit switched network that supported only analog voice communications. As the PSTN advanced in its structure and operation, it supported digital communications. The Internet is a more recently developed communication system that supports digital communications. As contrasted to the PSTN, the Internet is a packet switch network.

[0006] The Internet consists of a plurality of switch hubs and digital communication lines that interconnect the switch hubs. Many of the digital communication lines of the Internet are serviced via fiber optic cables (media). Fiber optic media supports high-speed communications and provides substantial bandwidth, as compared to copper media. At the switch hubs, switching equipment is used to switch data communications between digital communication lines. WANs, Internet service providers (ISPs), and various other networks access the Internet at these switch hubs. This structure is not unique to the Internet, however. Portions of the PSTN, wireless cellular network infrastructure, Wide Area Networks (WANs), and other communication systems also employ this same structure.

[0007] The switch hubs employ switches to route incoming traffic and outgoing traffic. A typical switch located at a switch hub includes a housing having a plurality of slots that are designed to receive Printed Circuit Boards (PCBs) upon which integrated circuits and various media connectors are mounted. The PCBs removably mount within the racks of the housing and typically communicate with one another via a back plane of the housing. Each PCB typically includes at least two media connectors that couple the PCB to a pair of optical cables and/or copper media. The optical and/or copper media serves to couple the PCB to other PCBs located in the same geographic area or to other PCBs located at another geographic area.

[0008] For example, a switch that services a building in a large city couples via fiber media to switches mounted in other buildings within the city and switches located in other cities and even in other countries. Typically, Application Specific Integrated Circuits (ASICs) mounted upon the PCBs of the housing. These ASICs perform switching operations for the data that is received on the coupled media and transmitted on the coupled media. The coupled media typically terminates in a receptacle and transceiver circuitry coupled thereto performs signal conversion operations. In most installations, the media, e.g., optical media, operates in a simplex fashion. In such case, one optical media carries incoming data (RX data) to the PCB while another optical media carries outgoing data (TX data) from the PCB. Thus, the transceiver circuitry typically includes incoming circuitry and outgoing circuitry, each of which couples to a media connector on a first side and communicatively couples to the ASIC on a second side. The ASIC may also couple to a back plane interface that allows the ASIC to communicate with other ASICs located in the enclosure via a back plane connection. The ASIC is designed and implemented to provide desired switching operations. The operation of such enclosures and the PCBs mounted therein is generally known.

[0009] The conversion of information from the optical media or copper media to a signal that may be received by the ASIC and vice versa requires satisfaction of a number of requirements. First, the coupled physical media has particular RX signal requirements and TX signal requirements. These requirements must be met at the boundary of the connector to the physical media. Further, the ASIC has its own unique RX and TX signal requirements. These requirements must be met at the ASIC interface. Thus, the transceiver circuit that resides between the physical media and the ASIC must satisfy all of these requirements.

[0010] Various standardized interfaces have been employed to couple the transceiver circuit to the ASIC. These standardized interfaces include the XAUI interface, the Xenpak interface, the GBIC interface, the XGMII interface, and the SFI-5 interface, among others. The SFI-5 interface, for example, includes 16 data lines, each of which supports a serial bit stream having a nominal bit rate of 2.5 Giga bits-per-second (GBPS). Line interfaces also have their own operational characteristics. Particular high-speed line interfaces are the OC-768 interface and the SEL-768 interface. Each of these interfaces provides a high-speed serial interface operating at a nominal bit rate of 40 GBPS.

[0011] Particular difficulties arise in converting data between the 40×1 GBPS line interface and the 16×2.5 GBPS communication ASIC interface. In particular, operation on the 40 GBPS side requires the ability to switch data at a very high bit rate, e.g., exceeding the bit rate possible with a CMOS integrated circuit formed of Silicon. While other materials, e.g., Indium-Phosphate and Silicon-Germanium provide higher switching rates than do Silicon based devices, they are very expensive and difficult to manufacture. Further, the functional requirements of interfacing the 40×1 GBPS line interface and the 16×2.5 GBPS communication ASIC interface are substantial. Thus, even if a device were manufactured that could perform such interfacing operations, the effective yield in an Indium-Phosphate or Silicon-Germanium process would be very low.

[0012] When multiple chips are assembled to provide an end-to-end solution in a high speed serial communications system such as the one described above, a decision has to be made as to the source for the clock that latches the data into the downstream circuit (i.e. the data receiving the data. One choice is to have the downstream circuit generate its own clock for latching the data. While this choice permits the upstream circuit to be simpler, there also can be problems associated with generating the clock on the chip that is receiving the data, such as jitter and phase alignment issues. Generating the clock at the upstream circuit may provide a cleaner clock that is more related to the data, but it also serves to render the upstream more complex.

[0013] Thus, there is a need in the art for low cost and high speed interface that couples a high-speed line side interface to a communication ASIC, and particularly one that provides for as much flexibility as possible in its configuration.

BRIEF SUMMARY OF THE INVENTION

[0014] An embodiment of a bit stream multiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream multiplexer may also includes a media interface that receives the single bit stream output at the line bit rate and couples the single bit stream output at the line bit rate to the high-speed bit stream media.

[0015] The first plurality of bit streams are received by the first transmit data multiplexing integrated circuit in a first input order such that a multiplexing hierarchy of the first transmit data multiplexing integrated circuit produces the second plurality of bit streams in a first output order such that a multiplexing hierarchy of the second transmit data multiplexing integrated circuit produces the single bit stream in the predetermined order.

[0016] An embodiment of the bit stream multiplexer of the invention also may include input and output ordering blocks. The input ordering block can present to the multiplexing hierarchy the first plurality of bit streams with their natural ordering, as a mirror image by reversing the most and least significant bit streams, by inverting the interpretation of the polarity of the differential signals, or by inverting the binary states of the outputs, all in response to different states of an input order select signal.

[0017] The output ordering block receives the first plurality of signals from the input ordering block and presents them to the multiplexing hierarchy such that the second plurality of bit streams is naturally ordered, or alternate orderings that include the first and fourth bit streams being swapped, the second and third bit streams being swapped or both to produce a mirror image of the natural ordering. The interpretation of the binary states of the polarities of none some or all of the differential bit stream signals can be inverted. All of these alternate orderings are realized through different states on the output order select input.

[0018] An embodiment of the bit stream demultiplexer of the invention couples a high-speed bit stream media to a communication Application Specific Integrate Circuit (ASIC), the bit stream demultiplexer includes a first receive data demultiplexing integrated circuit having an input that receives a single bit stream at a line bit rate, and an output for producing a first plurality of transmit bit streams at a first bit rate. A second receive data demultiplexing integrated circuit has an input that receives the first plurality of transmit bit streams at the first bit rate from the first receive data demultiplexing integrated circuit, and an output that produces a second plurality of transmit bit streams at a second bit rate. The first plurality has fewer bit streams than the second plurality. A media interface has an output that produces the single bit stream at the line bit rate and couples the high-speed bit stream media to the bit stream demultiplexer.

[0019] The first plurality of bit streams is produced by the first receive data demultiplexing integrated circuit in a first order that is the natural result of the predetermined order of the single bit stream and a demultiplexing hierarchy of the first receive data demultiplexing integrated circuit. The second receive data demultiplexing integrated circuit produces the second plurality of bit streams in a first output order that is the natural result of a multiplexing hierarchy of the second transmit data multiplexing integrated circuit and the natural order of the first plurality of bit streams.

[0020] An embodiment of the bit stream demultiplexer of the invention also can include input and output ordering blocks. The input ordering block can present to the demultiplexing hierarchy the first plurality of bit streams with their natural ordering, or in alternate orderings such as a mirror image by swapping the first and fourth bit streams as well as the second and third bit streams of the first plurality with respect to their natural ordering, or performing one or the other of the swaps without the other. The input ordering block can also invert the interpretation of the polarity of some, none or all the differential signals that comprise the bit streams of the first polarity such that a positive differential signal is considered a binary zero state instead of a one, and vice versa. All of these alternate orderings are realized through different states on the input order select input.

[0021] The output ordering block receives the second plurality of bit streams from the demultiplexing hierarchy and presents the bit streams to the second receive data demultiplexing integrated circuit naturally ordered, or with alternate orderings that include a mirror image of the natural ordering, or the interpretation of the binary states of the polarities having been reversed or both. All of these alternate orderings are realized through different states on the output order select input.

[0022] Other features and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0023] These and other features, aspects and advantages of the present invention will be more fully understood when considered with respect to the following detailed description, appended claims and accompanying drawings wherein:

[0024] FIG. 1 is a block diagram illustrating a Printed Circuit Board (PCB) that has mounted thereon a plurality of Bit Stream Interface Module (BSIMs) constructed according to the present invention;

[0025] FIG. 2A is a block diagram illustrating one embodiment of a BSIM constructed according to the present invention;

[0026] FIG. 2B is a block diagram illustrating an optical media interface that may be included wit the BSIM of FIG. 2A;

[0027] FIG. 3 is a block diagram illustrating another embodiment of a BSIM constructed according to the present invention;

[0028] FIG. 4A is a block diagram illustrating a TX data multiplexing integrated circuit constructed according to the present invention;

[0029] FIG. 4B is a block diagram illustrating an RX data demultiplexing integrated circuit constructed according to the present invention;

[0030] FIG. 5 is a block diagram illustrating the TX data multiplexing integrated circuits of FIG. 3 and the interfaces serviced thereby;

[0031] FIG. 6 is a block diagram illustrating the RX data demultiplexing integrated circuits of FIG. 3 and the interfaces serviced thereby;

[0032] FIG. 7 includes a table and a diagram that illustrate operating specifications for the TX interface between the TX data multiplexing integrated circuits of FIG. 3;

[0033] FIG. 8 includes a table and a diagram that illustrate operating specifications for the RX interface between the RX data demultiplexing integrated circuits of FIG. 3;

[0034] FIG. 9A is a block diagram illustrating the ordering of data blocks on the TX interface between the TX data multiplexing integrated circuits of FIG. 3;

[0035] FIG. 9B is a block diagram illustrating the ordering of data blocks on the RX interface between the RX data demultiplexing integrated circuits of FIG. 3;

[0036] FIG. 10 is a block diagram illustrating the jitter allocation for the TX link between TX data multiplexing integrated circuits of FIG. 3;

[0037] FIG. 11 is a block diagram illustrating the jitter allocation for the RX link between RX data multiplexing integrated circuits of FIG. 3;

[0038] FIG. 12 includes timing diagrams illustrating the set up and hold operations on the 4 bit wide×10 GBPS links between TX data multiplexing integrated circuits and between the RX data demultiplexing integrated circuits of FIG. 3;

[0039] FIG. 13 is a block diagram illustrating the pin-out of the TX data multiplexing integrated circuit of FIG. 3;

[0040] FIG. 14 is a block diagram illustrating the pin-out of the RX data demultiplexing integrated circuit of FIG. 3;

[0041] FIG. 15 is a block diagram illustrating a logical implementation for data recovery on the RX and TX links according to the present invention;

[0042] FIG. 16 is a block diagram illustrating a forward clock implementation for TX data multiplexing integrated circuits and RX data demultiplexing integrated circuits of the present invention;

[0043] FIG. 17 is a block diagram illustrating a reverse clock implementation for TX data multiplexing integrated circuits and RX data demultiplexing integrated circuits of the present invention;

[0044] FIG. 18A is a block diagram illustrating a first embodiment of one aspect of the first TX data multiplexing integrated circuit of FIG. 3;

[0045] FIG. 18B is a block diagram illustrating a second embodiment of one aspect of the first TX data multiplexing integrated circuit of FIG. 3;

[0046] FIG. 19A is a block diagram illustrating a first embodiment of one aspect of the RX data demultiplexing integrated circuit of FIG. 3;

[0047] FIG. 19B is a block diagram illustrating a second embodiment of one aspect of the RX data demultiplexing integrated circuit of FIG. 3;

[0048] FIG. 20 is a block diagram illustrating a multiple bit stream interface between the TX data multiplexing integrated circuit and the TX data multiplexing integrated circuit of FIG. 3;

[0049] FIG. 21 is a block diagram illustrating a multiple bit stream interface between the RX data demultiplexing integrated circuit and the RX data multiplexing integrated circuit of FIG. 3;

[0050] FIG. 22 illustrates the clock data relationship between a 40 GBPS bit stream and a 20 GHz self centered double data rate clock received by the 1:4 RX data demultiplexer circuit of FIG. 3.

[0051] FIG. 23 is a block diagram illustrating an embodiment of the 1:4 RX data demultiplexer circuit of FIG. 3 supporting a natural ordering of the input and output bit streams;

[0052] FIG. 24 is a block diagram illustrating an embodiment of the 4:16 RX data demultiplexer circuit of FIG. 3 supporting a natural ordering of the input and output bit streams;

[0053] FIG. 25 is a block diagram illustrating one embodiment of the 16 to 4 TX data multiplexer circuit of FIG. 3 supporting a natural ordering of the input and output bit streams; and

[0054] FIG. 26 is a block diagram illustrating one embodiment of the 4:1 TX data multiplexer circuit of FIG. 3 supporting a natural ordering of the input and output bit streams.

DETAILED DESCRIPTION OF THE INVENTION

[0055] FIG. 1 is a block diagram illustrating a Printed Circuit Board (PCB) that has mounted thereon a plurality of Bit Stream Interface Module (BSIMs) constructed according to the present invention. As shown in FIG. 1, the PCB 100 includes BSIMs 102A, 102B and 102C. The PCB 100 also includes mounted thereupon communication Application Specific Integrated Circuits (ASIC) 104A, 104B, and 104C. The PCB 100 is mounted within a housing that services switching requirements within a particular location or geographic area. Each of the BSIMs 102A, 102B, and 102C couples to a high-speed media such as an optical fiber via a respective media interface and supports the OC-768 or the SEC-768 standard at such media interface. On the second side of the BSIMs 102A through 102C, the SFI-5 interface standard is supported. Communication ASIC 104A through 104C may communicate with other PCB components located in the housing via back interfaces 106A through 106C.

[0056] The BSIMs 102A through 102C may be removably mounted upon the PCB 100. In such case, if one of the BSIMs 102A through 102C fails it may be removed and replaced without disrupting operation of other devices on the PCB 100. When the BSIMs 102-102C are removably mounted upon the PCB 100, they are received by a socket or connection coupled to the PCB 100. Further, in such embodiment, the BSIMs 102A-102C may be constructed on a separate PCB.

[0057] FIG. 2A is a block diagram illustrating one embodiment of a BSIM 102A constructed according to the present invention. The BSIM 102A of FIG. 2A includes a first combined TX/RX multiplexing/demultiplexing integrated circuit 202 and a second combined TX/RX multiplexing/demultiplexing integrated circuit 204. On the line side of the BSIM 102A, the first combined TX/RX multiplexing/demultiplexing integrated circuit 204 couples to a media, e.g., fiber optic cable or copper cable, via a media interface 206. The media interface 206 couples to the combined TX/RX multiplexing/demultiplexing integrated circuit 204 via a 40 GPS nominal bit rate, one bit transmit and one bit receive interface. The TX and RX line medias themselves each support one bit 40 Giga bits-per-second (GBPS) nominal bit rate communications, such as is defined by the OC-768 and/or SEC 768 specifications of the OIF.

[0058] The combined TX/RX multiplexing/demultiplexing integrated circuit 202 interfaces with a communication ASIC, e.g. 104A, via 16 TX bit lines and 16 RX bit lines, each operating at a nominal bit rate of 2.5 GBPS. Such interface supports a nominal total throughput of 40 GBPS (16*2.5 GBPS). The interface between the combined TX/RX multiplexing/demultiplexing integrated circuit 202 and the combined TX/RX multiplexing/demultiplexing integrated circuit 204 includes 4 TX bit lines and 4 RX bit lines, each operating at a nominal rate of 10 GBPS. This interface supports a nominal total throughput of 40 GBPS (4*10 GBPS). This interface may operate substantially or fully in accordance with an operating standard known as the Q40 operating standard. However, the teachings of the present invention are not limited to according to operation of the Q40 standard or is the description here intended to be a complete description of the Q40 standard itself.

[0059] FIG. 2B is a block diagram illustrating an optical media interface that may be included with the BSIM of FIG. 2A. As shown in FIG. 2B, media interface 206 couples to an optical media on a first side and couples to the combined TX/RX multiplexing/demultiplexing integrated circuit 204 on a second side. In the transmit path, the media interface 206 receives a single bit stream at a nominal bit rate of 40 GBPS from the combined TX/RX multiplexing/demultiplexing integrated circuit 204. The TX bit stream is amplified by limiting amplifier 252 to produce a bit stream output that is coupled to laser 254. The laser produces an optical signal that is coupled to TX optical media.

[0060] On the receive side, an RX optical media produces the RX bit stream at a nominal bit rate of 40 GBPS. The RX bit stream is received by a photo diode/pre-amplifier combination 258. The photo diode/pre-amplifier combination 258 produces an output that is received by a transimpedance amplifier 256. The output of the transimpedance amplifier 256 is a single bit stream at a nominal bit rate of 40 GBPS that is provided to the combined TX/RX multiplexing/demultiplexing integrated circuit 204 of FIG. 2A.

[0061] FIG. 3 is a block diagram illustrating another embodiment of a BSIM constructed according to the present invention. The embodiment of FIG. 3 differs from the embodiment of FIG. 2A in that separate TX and RX circuit components are employed. While the media interface 206 of FIG. 3 is shown to be a single device such as shown in FIG. 2B, in other embodiments, the media interface 206 may be formed in separate circuits corresponding to the separate TX and RX paths shown in FIG. 2B.

[0062] In the TX path, TX data multiplexing integrated circuit 302 receives a 16 bit wide by 2.5 GBPS nominal bit rate input from a coupled ASIC and produces a 4 bit wide×10 GBPS nominal bit rate TX output. In the embodiment described herein, the TX data multiplexing integrated circuit 302 is constructed in a Silicon CMOS process, for example in a 0.13 micron CMOS process. The TX data multiplexing integrated circuit 302 multiplexes the 16 bit wide by 2.5 GBPS nominal bit rate input to produce a 4 bit wide 10 GBPS nominal bit rate output, which is received by the TX data multiplexing integrated circuit 304. The TX data multiplexing integrated circuit 304 multiplexes the 4 bit wide x 10 GBPS nominal bit rate output to produce a single bit wide output at a nominal bit rate of 40 GBPS.

[0063] The TX data multiplexing integrated circuit 304 must switch at a frequency that is at least four times the rate at which the TX data multiplexing integrated circuit 302 must switch. For this reason, the TX data multiplexing integrated circuit 304 is constructed in an Indium-Phosphate process or in a Silicon-Germanium process. Each of these processes supports the higher switching rates required at the 40 GBPS output of the TX data multiplexing integrated circuit 304. Thus in combination the TX data multiplexing integrated circuit 302 constructed in a CMOS process and the TX data multiplexing integrated circuit 304 constructed in an Indium-Phosphate or Silicon-Germanium process will provide a high performance relatively low cost solution to the interfacing of a 2.5 GBPS nominal bit rate 16 bit wide interface and a 40 GBPS 1 bit wide interface.

[0064] Likewise, in the RX path, the bit stream interface module 102A includes an RX data demultiplexing integrated circuit 308 that receives a single bit stream at a nominal bit rate of 40 GBPS data. The RX data demultiplexing integrated circuit 308 produces a 4 bit wide×10 GBPS nominal bit rate output. The RX data demultiplexing integrated circuit 306 receives the 4 bit wide×10 GBPS nominal bit rate output and produces a 16 bit wide×2.5 GBPS nominal bit rate receive data stream.

[0065] As was the case with the TX data multiplexing integrated circuit 302 and the TX data multiplexing integrated circuit 304, the RX data demultiplexing integrated circuit 306 and the RX data demultiplexing integrated circuit 308 are formed in differing process types. In particular the RX data demultiplexing integrated circuit 306 is constructed in a Silicon CMOS process. Further, the RX data demultiplexing integrated circuit 308 is constructed in an Indium-Phosphate or Silicon-Germanium process so that the RX demultiplexer circuit 308 will support the higher switching speeds of the 1 bit wide×40 GBPS interface to the media interface 206.

[0066] FIG. 4A is a block diagram illustrating a TX data multiplexing integrated circuit constructed according to the present invention. As shown in FIG. 4A, the TX data multiplexing integrated circuit 302 receives 16 bit steams of data at nominal bit rate of 2.5 GBPS on each bit line from the communication ASIC 104A. Each bit line of this 16 bit wide interface however can operate at bit rates of up to 3.125 GBPS. This interface also includes DSCD Data and a 622 MHz clock. The output of the TX data multiplexing integrated circuit 302 includes 4 bit lines, each of which supports a nominal bit rate of 10 GBPS. However, the output of the TX data multiplexing integrated circuit can produce data at bit rates of between 9.95 GBPS and 12.5 GBPS. The TX data multiplexing integrated circuit 302 also produces a clock signal at one-half the nominal bit rate of the 4 bit stream paths. In such case, when the nominal bit rate of the data paths is 10 GBPS, the clock will be produced at 5 GHz.

[0067] FIG. 4B is a block diagram illustrating an RX data demultiplexing integrated circuit 306 constructed according to the present invention. As shown in FIG. 4B, the RX data demultiplexing integrated circuit 306 receives 4 bit streams at nominal bit rates of 10 GBPS each but may operate in the range of 9.95 GBPS to 12.5 GBPS. The RX data demultiplexing integrated circuit 306 also receives a clock signal at one-half the nominal bit rate of the 4 bit stream paths. In such case, when the nominal bit rate of the data paths is 10 GBPS, the clock is received at 5 GHz. The RX data demultiplexing integrated circuit 306 produces 16 bit stream outputs at a nominal bit rate of 2.5 GBPS and DSCD Data. However, the RX data demultiplexing integrated circuit 306 may produce the 16 bit streams output at a bit rate of between 2.5 GBPS and 3.125 GBPS.

[0068] FIG. 5 is a block diagram illustrating the TX data multiplexing integrated circuits 302 and 304 of FIG. 3 and the interfaces serviced thereby. As is shown in FIG. 5, the TX data multiplexing integrated circuit 302 receives 16 bit streams at nominal bit rates of 2.5 GBPS and produces 4 bit streams at nominal bit rates of 10 GBPS. Such operation corresponds to a 16 to 4 multiplexing operation. The TX data multiplexing integrated circuit 302 also produces a framer clock output at 622 MHz, receives a reference clock input at 622 MHz, and also receives a loss of lock signal (TX_LOL) signal from the TX data multiplexing integrated circuit 304.

[0069] Further, the TX data multiplexing integrated circuit 304 receives the 4 bit streams at nominal bit rates of 10 GBPS and produces the single bit output at a nominal bit rate of 40 GBPS. However, the TX data multiplexing integrated circuit 304 that performs the 4:1 multiplexing may operate at an output rate of between 39.8 GBPS and 50 GBPS. The bit rates indicated herein are provided not to limit the scope of the present invention but only to describe contemplated embodiments for implementing the teachings of the present invention.

[0070] The signal transition diagrams of FIG. 5 indicating the data and the TFCLK signal show that the bit rate is twice the rate of the TFCLK signal. In such case, data is latched on the 4 bit×10 GBPS link at each transition of the TFCLK.

[0071] FIG. 6 is a block diagram illustrating the RX data demultiplexing integrated circuits 306 and 308 of FIG. 3 and the interfaces serviced thereby. As is shown in FIG. 6, the RX data demultiplexing integrated circuit 308 receives a single bit stream at a nominal bit rate of 40 GBPS. However, the single bit stream input may operate at bit rates from between 39.8 GBPS and 50 GBPS. The RX data demultiplexing integrated circuit 308 performs a 1:4 demultiplexing operation on the received single bit stream to produce 4 output bit streams at a nominal bit rate of 10 GBPS. However, the RX data demultiplexing integrated circuit 308 may also produce output at bit rates from 9.95 GBPS to 12.5 GBPS.

[0072] The RX data demultiplexing integrated circuit 306 receives the 4 bit streams having nominal bit rates of 10 GBPS each and a QCLKI signal and a RX_LOL signal from the RX data demultiplexing integrated circuit 308. Based upon these input signals, the RX data demultiplexing integrated circuit 306 produces the 16 bit stream outputs at nominal bit rates of 2.5 GBPS. Also shown in FIG. 6, the QCLKI signal operates at one-half the frequency of the bit rate of the data stream received from the RX data demultiplexing integrated circuit 308. Thus, in such case, for the nominal bit rate of 10 GBPS, the QCLKI signal will be provided at 5 GHz.

[0073] FIG. 7 includes a table and a diagram that illustrate operating specifications for the TX interface between the TX data multiplexing integrated circuits of FIG. 3. FIG. 7 includes the transmitter output and clock specifications 700 and an equivalent circuit 702 upon which these specifications are based. As indicated, the output of the TX data multiplexing integrated circuit 302 is a common mode output. Further, the impedance of the output is 50 ohms single ended and 100 ohms differential. The other properties of the TX data multiplexing integrated circuit 302 output are shown at 700. Further, the equivalent circuit for the interface on the transmit side is indicated at 702.

[0074] FIG. 8 includes a table and a diagram that illustrate operating specifications for the RX interface between the RX data demultiplexing integrated circuits of FIG. 3. As shown in FIG. 8, the receiver input parameters are shown at 800 and an equivalent circuit thereupon is shown at 802. As is generally illustrated the receiver input parameters are analogous to the transfer parameters of FIG. 7.

[0075] FIG. 9A is a block diagram illustrating the ordering of data blocks on the TX interface between the TX data multiplexing integrated circuits of FIG. 3. As shown in FIG. 9A, the transmit data format 900 is in a natural order. The transmit data format is produced by the TX data multiplexing integrated circuit 302 and provided to the TX data multiplexing integrated circuit 304. This natural data formatting allows the TX data multiplexing integrated circuit to perform its 4:1 multiplexing operations such that the single bit stream 40 GBPS output will be provided so that the bits are in their natural order.

[0076] FIG. 9B is a block diagram illustrating the ordering of data blocks on the RX interface between the RX data demultiplexing integrated circuits of FIG. 3. Likewise, as is shown in FIG. 9B, the received data format 950 is also in a natural order so that when the data is demultiplexed by the RX data demultiplexing integrated circuit 306, the data will be provided on the 16 lines of the 2.5 GBPS interface in a natural order.

[0077] FIG. 10 is a block diagram illustrating the jitter allocation for the TX link between TX data multiplexing integrated circuits of FIG. 3. One of four data differential data line drivers 1002 of the TX data multiplexing integrated circuit 302 and a differential clock driver 1006 of the TX data multiplexing integrated circuit 302 on the 4 bit stream 10 GBPS side are shown. FIG. 10 also illustrates one of four data input buffers 1004 of the TX data multiplexing integrated circuit 304 and a clock input buffer 1008 of the TX data multiplexing integrated circuit 3004. As is indicated, deterministic jitter for the data interface is specified as a maximum of 6 picoseconds. Further, the skew in the data lines with respect to the clock is limited to ±8 picoseconds.

[0078] FIG. 11 is a block diagram illustrating the jitter allocation for the RX link between RX data demultiplexing integrated circuits of FIG. 3. One of four data differential data line drivers 1102 of the RX data demultiplexing integrated circuit 308 and a differential clock driver 1106 of the RX data demultiplexing integrated circuit 308 on the 4 bit stream 10 GBPS side are shown. FIG. 10 also show one of four data input buffers 1104 of the RX data demultiplexing integrated circuit 306 and a clock input buffer 1108 of the RX data demultiplexing integrated circuit 306. As is indicated, deterministic jitter for the data interface is specified as a maximum of 4 picoseconds. Further, the skew in the data lines with respect to the clock is limited to ±6 picoseconds. The additional information provided in FIG. 11 shows how these jitters may be summed to result at maximum jitters.

[0079] FIG. 12 includes timing diagrams illustrating the set up and hold operations on the 4 bit×10 GBPS links between TX data multiplexing integrated circuits and between the RX data demultiplexing integrated circuits of FIG. 3. In particular, the setup and hold specifications for the TX link are shown via graphs 1200 while the setup and hold specifications for the RX link are shown via graphs 1250.

[0080] FIG. 13 is a block diagram illustrating the pin-out of the TX data multiplexing integrated circuit 302 of FIG. 3. As shown in FIG. 13, the pin-out 1302 of the TX data multiplexing integrated circuit 302 includes the 4 bit×10 GBPS nominal rate differential signals on a first side. As shown, the differential clock is centered on this side to balance the data and clock line. Further, respective ground line shields each of the data lines and the clock lines. The pin-out 1302 also includes the 16 bit stream×2.5 GBPS nominal bit rate lines.

[0081] FIG. 14 is a block diagram illustrating the pin-out of the RX data demultiplexing integrated circuit 306 of FIG. 3. As is shown in FIG. 13, the pin-out 1402 for the RX data demultiplexing integrated circuit 306 includes a symmetrically centered clock on the 4 bit stream×10 GBPS bit rate side. Further, the 16 data lines on the 12.5 GBPS nominal bit rate side are distributed in a particular order. As will be described further herein, the particular orders of the signals that may be produced or received by the RX data demultiplexing integrated circuit 306 are switchable.

[0082] FIG. 15 is a block diagram illustrating a logical implementation for data recovery on the RX and TX links according to the present invention. As is illustrated in FIG. 15, a 4 bit 10 GBPS nominal bit rate interface driven by the TX data multiplexing integrated circuit 302 can support up to a 2 inch PCB trace length. Further, as is shown, the data is re-timed with the 5 GHz DDR differential clock just before exiting the TX data multiplexing integrated circuit 302. Further, data at the TX data multiplexing integrated circuit 304 is re-timed upon receipt with the differential 5 GHz DDR clock. The goal in this operation is to keep data and clock symmetrical with minimal skew to minimize the skew between the data lines and between the clock and the data lines on the 4 line 10 GBPS nominal bit rate interface.

[0083] FIG. 16 is a block diagram illustrating a forward clock implementation for TX data multiplexing integrated circuits and RX data demultiplexing integrated circuits of the present invention. As illustrated in FIG. 16, the operation of the TX data multiplexing integrated circuit 302, TX data multiplexing integrated circuit 304, RX data demultiplexing integrated circuit 306, and RX data demultiplexing integrated circuit 308 may operate in a forward clock implementation. This implementation is shown particularly in FIG. 16.

[0084] FIG. 17 is a block diagram illustrating a reverse clock implementation for TX data multiplexing integrated circuits and RX data demultiplexing integrated circuits of the present invention. Referring now to FIG. 17, the TX data multiplexing integrated circuit 302, the TX data multiplexing integrated circuit 304, the RX data demultiplexing integrated circuit 306, and the RX data demultiplexing integrated circuit 308 may also be operated in a reverse clock implementation as shown.

[0085] FIG. 18A is a block diagram illustrating a first embodiment of one aspect of the first TX data multiplexing integrated circuit 302 of FIG. 3. The first TX data multiplexing integrated circuit 302 receives 16 bit streams at a nominal bit rate of 2.5 GBPS from a coupled communication ASIC. An input ordering and deskew block 1802 orders and deskews these incoming bit streams into a natural order, as was illustrated in FIG. 9A based upon a SPI_TX_ORDER_SLCT signal that is m bits wide. A plurality of TX 4×1 multiplexers 1804, 1806, 1808, and 1810 receive the output from the input ordering and deskew block 1802 in the order received and, based upon the M_CLK signal received from the clock generating circuit 1812, multiplex the input to produce a four bit stream output. The four bit stream output is received by the output ordering block 1814 that produces the four bit streams and the TFCLK of the multiple bit stream interface that interfaces the first TX data multiplexing integrated circuit 302 and the second TX data multiplexing integrated circuit 304 at the nominal bit rate of 10 GBPS. The output ordering block 1814 orders the output bits based upon the n bit wide Q40_TX_ORDER_SLCT signal and outputs the ordered four bit streams of the multiple bit stream interface that are coupled by the four bit stream interface to the second TX data multiplexing integrated circuit 304.

[0086] FIG. 18B is a block diagram illustrating a second embodiment of one aspect of the first TX data multiplexing integrated circuit 302 of FIG. 3. The first TX data multiplexing integrated circuit 302 receives 16 bit streams at a nominal bit rate of 2.5 GBPS from a coupled communication ASIC. An input ordering and deskew block 1852 orders and deskews these incoming bit streams based upon the m bit wide SPI_TX_ORDER_SLCT signal. The output of the input ordering and deskew block 1852 is received by the output ordering block 1864, which orders the sixteen data streams based upon the n bit wide Q40_TX_ORDER_SLCT signal. The output of the output ordering block 1864 is received by a plurality of TX 4×1 multiplexers 1854, 1856, 1858, and 1860 and, based upon the M_CLK signal received from the clock generating circuit 1862, multiplexes the sixteen bit streams to produce a four bit stream output as shown.

[0087] With the embodiments of both FIGS. 18A and 18B, the first TX data multiplexer circuit 302 includes an input ordering block 1802 (1852) that orders/reorders the incoming bit streams. The input ordering block 1814 (1864) is controlled with the SPI_TX_ORDER_SLCT to the outside input lines 12:15 and 0:3 can be reordered via a positional exchange, the inside inputs 8:11 and 4:7 can be reordered via a positional exchange, or both the outside input lines 12:15 and 0:3 and the inside inputs 8:11 and 4:7 can be reordered via a positional exchange. Additionally, the polarity of the (differential) inputs can be inverted and/or repositioned individually or en masse. Output ordering block 1814 (1864 and multiplexers (1854-1860) may invert the ordering of the outputs 0:4 to be their mirror image and/or may invert the polarity of the outputs 0:4 to accommodate flip-chip and wire bond mounting based on one or more states of the n bit Q40_TX_ORDER_SLCT signal. In the multiplexing circuit 302 of both FIGS. 18A and 18B, the data may be received in a natural order, as was illustrated in detail in FIG. 9B.

[0088] FIG. 19A is a block diagram illustrating a first embodiment of one aspect of the RX data demultiplexing integrated circuit 306 of FIG. 3. The first RX data multiplexing integrated circuit 306 receives four bit streams and the QCLKI of a multiple bit stream interface from the second RX data multiplexing integrated circuit 308. An input ordering and deskew block 1914 deskews and orders the incoming bit streams. Ordering/reordering of the four input streams is based upon the n bit Q40_RX_ORDER_SLCT signal received by the input ordering and deskew block 1914. The input ordering and deskew block 1914 may also invert the polarity of the incoming bit streams based upon the Q40_RX_ORDER_SLCT signal. RX 1×4 demultiplexers 1904, 1906, 1908, and 1910 then demultiplex these signals based upon a DMCK produced by the clock generation circuit 1912. The 1×4 demultiplexers 1904, 1906, 1908, and 1910 produce 16 bit streams to output ordering block 1902. The output ordering block 1902 receives the 16 bit streams and orders/reorders the 16 bit streams based upon the m bit SPI_RX_ORDER_SLCT signal to produce 16 bit streams at a nominal bit rate of 2.5 GBPS to a coupled communication ASIC. The output ordering block 1902 also produces the 16 bit streams with a selected polarity based upon the m bit SPI_RX_ORDER_SLCT signal

[0089] FIG. 19B is a block diagram illustrating a second embodiment of one aspect of the RX data demultiplexing integrated circuit 306 of FIG. 3. The first RX data multiplexing integrated circuit 306 receives four bit streams and the QCLKI of a multiple bit stream interface from the second RX data multiplexing integrated circuit 308. A plurality of RX 4×1 demultiplexers 1954, 1956, 1958, and 1960 demultiplex the four bit streams based upon a DMCK produced by clock generation circuit 1962 to produce 16 bit streams to input ordering and deskew block 1964. Input ordering and deskew block 1964 deskews and orders/reorders (and optionally inverts the polarity of) these incoming bit streams based upon the Q40_RX_ORDER_SLCT signal. The output of the input ordering and deskew block 1964 is received by output ordering block 1952 that orders/reorders the 16 bit streams based upon the m bit SPI_RX_ORDER_SLCT signal to produce 16 bit streams at a nominal bit rate of 2.5 GBPS to a coupled communication ASIC. In the demultiplexing circuit 306 of both FIGS. 19A and 19B, the data may be presented in a natural order, as was illustrated in detail in FIG. 9A.

[0090] FIG. 20 is a block diagram illustrating a multiple bit stream interface between the TX data multiplexing integrated circuit 302 and the TX data multiplexing integrated circuit 304 of FIG. 3. The multiple bit stream interface includes four differential bit streams. A first differential bit stream is indicated by TX DATA_O_POS and TX_DATA_O_NEG. A second differential bit stream is indicated by TX_DATA—1_POS and TX_DATA_1_NEG. A third differential bit stream is indicated by TX_DATA—2_POS and TX_DATA—2_NEG. A fourth differential bit stream is indicated by TX_DATA—3_POS and TX_DATA—3_NEG. The natural ordering of the bits of the four bit streams of the interface is indicated in FIG. 9A. A differential source centered TFCLK (as shown in FIG. 5) is carried on lines that are centrally located with respect to the lines that carry the differential bit streams. Further, shielding lines, such as grounds and voltages may serve to shield the data lines and the clocks from one another.

[0091] FIG. 21 is a block diagram illustrating a multiple bit stream interface between the RX data demultiplexing integrated circuit 308 and the RX data multiplexing integrated circuit 306 of FIG. 3. The multiple bit stream interface includes four differential bit streams. A first differential bit stream is indicated by RX_DATA—0_POS and RX_DATA—0_NEG. A second differential bit stream is indicated by RX_DATA—1_POS and RX_DATA—1_NEG. A third differential bit stream is indicated by RX_DATA—2_POS and RX_DATA—2_NEG. A fourth differential bit stream is indicated by RX DATA—3_POS and RX_DATA—3_NEG. The natural ordering of the bits of the four bit streams of the interface are indicated in FIG. 9B. A differential source centered QCLKI (as shown in FIG. 6) is carried on lines that are centrally located with respect to the lines that carry the differential bit streams. Further, shielding lines, such as grounds and voltages may serve to shield the data lines and the clocks from one another.

[0092] FIG. 22 illustrates the clock data relationship between a 40 GBPS bit stream and a 20 GHz self-centered double data rate clock received by the 1:4 RX data demultiplexer circuit 308 of FIG. 3. The RX data demultiplexer circuit 308 uses the source centered, double data rate (DDR) clock 702 to latch in and demultiplex the 40 GBPS bit stream. In the embodiment illustrated, data is received in a natural order with a most significant bit of a series of 16 bits of the bit stream RX15, is received first in time, followed by bits RX14, RX13, RX12 and so on through RX0 (not shown). Each bit is latched by one of the edges of the clock 2202 as shown. The bit pattern is repeated every 16 bits of the bit stream so that each of the 16 bits of the bit stream is split into its corresponding one of 16 demultiplexer channels.

[0093] FIG. 23 is a block diagram illustrating an embodiment of the 1:4 RX data demultiplexer circuit 308 of FIG. 3 supporting a natural ordering of the input and output bit streams. A first 1:2 demultiplexer includes demultiplexer latches 2306 and 2308. Demultiplexer latch 1202 is latches data from bit stream 2302 to its Q output on a high-to-low transition of the 20 GHz clock 2304 (e.g. on the negative edge) and demultiplexer latch 1204 latches data from bit stream 2302 to its Q output on the low-to-high transition of the 20 GHz clock 2304 (e.g. the positive edge). Thus, the two demultiplexer latches alternate latching bits of bit stream 2302 such that bits RX15, RX13, RX11, . . . , RX1 appear sequentially at the Q output of demultiplexer latch 2306, and bits RX14, RX12, RX10, . . . , RX0 appear sequentially at the Q output of demultiplexer latch 2308.

[0094] The Q output of the demultiplexer latch 2306 is then fed into 1:2 demultiplexer 2310 and the output of the demultiplexer latch 2308 is fed into 1:2 demultiplexer 2312. In one embodiment, each of these demultiplexers is also constructed of the same arrangement of demultiplexer latches as is shown for 1:2 demultiplexer latches 2306 and 2308. The only difference is that the demultiplexer latches of demultiplexers 2310 and 2312 are clocked at half the frequency (i.e. 10 GHz clock) of those of demultiplexer 811. In one embodiment, the 20 GHz clock 702 is divided by two by a clock divider (not shown) to achieve the 10 GHz clock. Demultiplexer 2310 produces outputs QDI3 and QDI1, which are made up of demultiplexer channels RX105, RX101, RX7, RX3 and RX103, RX9, RX5, RX1, respectively. Likewise, demultiplexer 2312 produces outputs QDI2 and QDI0, which are made up of demultiplexer channels RX14, RX10, RX6, RX2 and RX12, RX8, RX4, RX0, respectively. In this way, the RX data demultiplexer circuit performs the first stage (i.e. 1:4 demultiplex function) of the 1:16 demultiplexing function. The four 10 GBPS data streams QDI3, QDI1, QDI2 and QDI0, shown with respect to time, represent the natural ordering of the demultiplexed streams as produced by the two-level demultiplexing hierarchy of the RX data demultiplexer circuit 308.

[0095] FIG. 24 is a block diagram illustrating an embodiment of the 4:16 RX data demultiplexer circuit 306 of FIG. 3 supporting a natural ordering of the input and output bit streams. The 1:4 demultiplexers 1904 (1954), 1906 (1956), 1908 (1958), 1910 (1960) of RX data demultiplexer circuit 306, when combined with the 1:4 demultiplexer of RX data demultiplexer circuit 308 of FIG. 23, provides a multi-level demultiplexing hierarchy that yields the desired 1:16 multiplexing function. As is the case for the 1:4 demultiplexer of FIG. 23, each 1:4 demultiplexer circuit 1904 (1954), 1906 (1956), 1908 (1958), 1910 (1960) may be constructed of two levels of 1:2 demultiplexers. In such case, the 1:2 demultiplexers may be constructed substantially in the same manner as the 1:2 multiplexers of FIG. 23 of FIG. 8. However, the RX data demultiplexer circuit 306 of FIG. 24 will typically be formed in a differing manufacturing process than was the RX data demultiplexer circuit 308 of FIG. 23.

[0096] The first level demultiplexers of each of the 1:4 demultiplexer circuits 1904 (1954), 1906 (1956), 1908 (1958), 1910 (1960) receive the 10 GBPS data streams and use the 5 GHz DDR clock to clock the bits in an alternating fashion to produce two demultiplexer channel outputs. These outputs are then fed into the second level (3rd level overall) of demultiplexers to provide the final split into separate demultiplexer channels. The clock used for the second-level demultiplexers of the 1:4 demultiplexer circuits 1904 (1954), 1906 (1956), 1908 (1958), 1910 (1960) is the QCLKI divided by 2 (not shown). Thus, 1:4 demultiplexer 1904 (1954) produces demultiplexer channels RX15, RX7, RX11 and RX3, 1:4 demultiplexer 1906 (1956) produces RX13, RX5, RX9, and RX1, 1:4 demultiplexer 1908 (1958) produces RX14, RX6, RX10 and RX2, and 1:4 demultiplexer 1960 (1960) produces RX12, RX4, RX8 and RXO, each of which is a bit stream at 2.5 GBPS.

[0097] To make the physical order of the demultiplexer channels for each demultiplexer from most significant to least significant, the two inside lines are simply interposed physically with respect to the package output pins. The ordering of the 2.5 GBPS demultiplexer channel output streams are therefore a continuation of the natural ordering that is produced by the 4 level 1:2 demultiplexing hierarchy that spans the RX data demultiplexer circuit 308, and 306.

[0098] Those of skill in the art will recognize that the multiplexing functions performed by TX data multiplexer circuits 302, 304 are the inverse of the demultiplexing functions performed by RX data demultiplexer circuits 306, 308. Thus, to produce a single bit stream at the output of TX data multiplexer circuit 304 using a multiplexing hierarchy that is the inverse of the demultiplexing hierarchy of RX data demultiplexer circuits 306, 308, and that has the same bit ordering as the single bit stream demultiplexed by the RX data demultiplexer circuits 306, 308, one should start with the same natural ordering on the inputs to the TX data multiplexer circuit 304 as that produced by the demultiplexing process.

[0099] FIG. 25 is a block diagram illustrating one embodiment of the 16 to 4 TX data multiplexer circuit 302 of FIG. 3 that supports a natural ordering of the input and output bit streams. The 16:4 multiplexer circuit 302 uses a two-tiered hierarchical multiplexing process to produce the first stage (i.e. 16:4 multiplexing process) of a 16:1 multiplexing process that spans the TX data multiplexer circuits 302 and 304. Four 4:1 multiplexers 1804 (1854), 1806 (1856), 1808 (1858), 1810 (1860) produce the outputs QDO3, QDO1, QDO2, and QDO0 respectively. A first tier of 2:1 multiplexers of 4:1 multiplexers l804 (1854), 1806 (1856), 1808 (1858), 1810 (1860) alternate selecting data from their two inputs on the rising and falling edges of a 2.5 GHz clock (not shown). A second tier of 2:1 multiplexers of 4:1 multiplexers 1804 (1854), 1806 (1856), 1808 (1858), 1810 (1860) are clocked using a 5 GHz DDR clock (generated by multiplying the 2.5 GHz clock by two) to combine the outputs of the first tiers to produce outputs QDO3, QDO1, QDO2 and QDO0, respectively.

[0100] FIG. 26 is a block diagram illustrating one embodiment of the 4:1 TX data multiplexer circuit 304 of FIG. 3 supporting a natural ordering of the input and output bit streams. The second stage of the 16:1 multiplexing process combines the 10 GBPS QDO outputs to produce the serial 40 GBPS stream in the predetermined order. A first tier of 2:1 multiplexers 2610 and 2612 combine data blocks from QDO3 with QDO1 and QDO2 with QDO0, respectively, using a 5 GHz DDR clock. The 2:1 multiplexers 2610 and 2612 produce 20 GBPS outputs that are combined by a second tier 2:1 multiplexer 2614 using a 20 GHz DDR clock to produce the 40 GBPS bit stream. TX data multiplexer circuits 302 and 304 provide a 16:1 multiplexing function in two stages that span both circuits in a manner that is the inverse of the 1:16 demultiplexing process produced by RX data demultiplexer circuits 306 and 308.

[0101] The invention disclosed herein is susceptible to various modifications and alternative forms. Specific embodiments therefore have been shown by way of example in the drawings and detailed description. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the claims.

Claims

1. A bit stream multiplexer that couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media, the bit stream multiplexer comprising: a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality; a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order; a media interface that receives the single bit stream output at the line bit rate and couples the single bit stream output at the line bit rate to the high-speed bit stream media; and wherein the first plurality of bit streams is received by the first transmit data multiplexing integrated circuit in a first input order such that a multiplexing hierarchy of the first transmit data multiplexing integrated circuit produces the second plurality of bit streams having a first output order to such that a multiplexing hierarchy of the second transmit data multiplexing integrated circuit produces the single bit stream in the predetermined order.

2. The bit stream multiplexer of claim 1 wherein the multiplexing hierarchy of the first transmit data multiplexing integrated circuit is based on a series of 2 to 1 multiplexers the depth of which is sufficient to combine the number of bit streams comprising the first plurality of bit streams into the number of bit streams comprising the second plurality of bit streams.

3. The bit stream multiplexer of claim 2 wherein the multiplexing hierarchy of the second transmit data multiplexing integrated circuit is based on a series of 2 to 1 multiplexers the depth of which is sufficient to combine the number of bit streams comprising the second plurality of bit streams into the single bit stream.

4. The bit stream multiplexer of claim 3 wherein the multiplexing hierarchy of the first transmit data multiplexing integrated circuit comprises a 16 to 4 multiplexer further comprising four 4 to 1 multiplexers, each of the 4 to 1 multiplexers comprising a first level of two 2 to 1 multiplexers in series with a second level of one 2 to 1 multiplexer.

5. The bit stream multiplexer of claim 4 wherein the multiplexing hierarchy of the second transmit data multiplexing integrated circuit comprises a 4 to 1 multiplexer further comprising a first level of two 2 to 1 multiplexers in series with a second level of one 2 to 1 multiplexer.

6. The bit stream multiplexer of claim 1 wherein the first transmit data multiplexing integrated circuit further comprises an input ordering block having an input to receive the first plurality of bit streams, and an output that presents to the multiplexing hierarchy of the first transmit data multiplexing integrated circuit the first plurality of bit streams in the first input order or a different input order than the first input order in accordance with an input order select input.

7. The bit stream multiplexer of claim 6 wherein the first plurality of bit streams is presented to the multiplexing hierarchy in the first input order in response to a first state of the input order select input, and in an input order that is a mirror image of the first input order in response to a second state of the input order select input.

8. The bit stream multiplexer of claim 6 wherein: each of the first plurality of bit streams is differential and has a positive and negative polarity signal, a physical ordering of which is the positive signal followed by the negative signal; the first input order includes interpreting a positive differential voltage between the positive and negative polarity signals as a binary one and a negative differential voltage between the two signals as a binary zero state for each of the first polarity of bit streams; and the input order presented to the multiplexer hierarchy is based on interpreting a positive differential voltage to be a binary zero state and a negative differential voltage to be a binary one state for of each of the polarity of bit streams in response to a third state of the input order select input.

9. The bit stream multiplexer of claim 8 wherein the binary states presented to the multiplexer hierarchy are inverted with respect to their interpretation in response to a fourth state of the input order select input.

10. The bit stream multiplexer of claim 1 wherein the first transmit data multiplexing integrated circuit further comprises an output ordering block having an input to receive the first plurality of bit streams, and an output that presents to the multiplexing hierarchy of the first transmit data multiplexing integrated circuit the first plurality of bit streams in the first output order or a different output order than the first output order in accordance with an output order select input.

11. The bit stream multiplexer of claim 6 wherein the first plurality of bit streams is presented by the output ordering block to the multiplexing hierarchy in the first order in response to a first state of the output order select input to produce the first output order, and in an order that is a mirror image of the first order in response to a second state of the output order select input.

12. The bit stream multiplexer of claim 11 wherein the first plurality of bit streams is presented by the output ordering block to the multiplexing hierarchy in a second order in response to a third state of the output order, the second output order swapping the second and third bit streams with respect to the first output order.

13. The bit stream multiplexer of claim 11 wherein the first plurality of bit streams is presented by the output ordering block to the multiplexing hierarchy in a third order in response to a fourth state of the output order select input, the second output order swapping the first and fourth bit streams with respect to the first output order.

14. A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrate Circuit (ASIC), the bit stream demultiplexer comprising: a first receive data demultiplexing integrated circuit having an input that receives a single bit stream at a line bit rate, and an output for producing a first plurality of bit streams at a first bit rate; a second receive data demultiplexing integrated circuit having an input that receives the first plurality of bit streams at the first bit rate from the first receive data demultiplexing integrated circuit, and an output that produces a second plurality of bit streams at a second bit rate, the first plurality having fewer bit streams than the second plurality; a media interface having an output that produces the single bit stream at the line bit rate and couples the high-speed bit stream media to the bit stream demultiplexer; and wherein the first plurality of bit streams is produced by the first receive data demultiplexing integrated circuit in a first order that is the natural result of the predetermined order of the single bit stream and a demultiplexing hierarchy of the first receive data demultiplexing integrated circuit, and wherein the second receive data demultiplexing integrated circuit produces the second plurality of bit streams in a first output order that is the natural result of a multiplexing hierarchy of the second transmit data multiplexing integrated circuit and the natural order of the first plurality of bit streams.

15. The bit stream demultiplexer of claim 14 wherein the demultiplexing hierarchy of the first transmit data demultiplexing integrated circuit is based on a series of 1 to 2 demultiplexers the depth of which is sufficient to produce the number of bit streams comprising the first plurality bit streams from the single but stream.

16. The bit stream demultiplexer of claim 15 wherein the demultiplexing hierarchy of the second transmit data multiplexing integrated circuit is based on a series of 1 to 2 demultiplexers the depth of which is sufficient to produce the number of bit streams comprising the first plurality of bit streams into the number of bit streams of the second plurality of bit streams.

17. The bit stream multiplexer of claim 16 wherein the demultiplexing hierarchy of the first transmit data multiplexing integrated circuit comprises a 1 to 4 demultiplexer further comprising a first level of two 1 to 2 demultiplexers in series with a second level of one 1 to 2 demultiplexer.

18. The bit stream demultiplexer of claim 17 wherein the demultiplexing hierarchy of the second transmit data multiplexing integrated circuit comprises a 4 to 16 demultiplexer further comprising four 1 to 4 demultiplexers, each of the 1 to 4 demultiplexers comprising a first level of two 1 to 2 multiplexers in series with a second level of one 1 to 2 demultiplexer.

19. The bit stream demultiplexer of claim 14 wherein the first receive data multiplexing integrated circuit further comprises an input ordering block having an input to receive the first plurality of bit streams in the first order, and an output that presents to the demultiplexing hierarchy of the first transmit data multiplexing integrated circuit the first plurality of bit streams in the first order or a different order than the first order in accordance with an input order select input.

20. The bit stream demultiplexer of claim 19 wherein the first plurality of bit streams is presented to the demultiplexing hierarchy in the first order in response to a first state of the input order select input, and in an order that is a mirror image of the first order in response to a second state of the input order select input.

21. The bit stream demultiplexer of claim 20 wherein the first plurality of bit streams is presented by the input ordering block to the demultiplexing hierarchy in a second order in response to a second state of the input order select input to produce a second output order that swaps the second and third bit streams with respect to the first order in response to a third state of the input order select input.

22. The bit stream demultiplexer of claim 21 wherein the first plurality of bit streams is presented by the input ordering block to the demultiplexing hierarchy in a third output order in response to a fourth state of the output order select input by swapping the first and fourth bit streams with respect to the first order.

23. The bit stream demultiplexer of claim 14 wherein the first receive data demultiplexing integrated circuit further comprises an output ordering block having an input to receive the second plurality of bit streams from the demultiplexing hierarchy, and an output that presents the second plurality of bit streams to the communications ASIC in the first output order or a different output order than the first output order in accordance with an output order select input.

24. The bit stream multiplexer of claim 23 wherein the second plurality of bit streams is presented by the output ordering block to the communications ASIC in the first order in response to a first state of the output order select, and in an order that is a mirror image of the first order in response to a second state of the output.

25. The bit stream multiplexer of claim 24 wherein the first plurality of bit streams is presented by the output ordering block to the communications ASIC in a second output order in response to a second state of the output order select input to produce a second output order that swaps the polarities of differential output signals of each of the bit streams.