This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0107628 filed on Oct. 20, 2011 and to Korean Patent Application No. 10-2010-0115855 filed on Nov. 19, 2010, the entireties of which are hereby incorporated by reference.
The present invention relates to a signal pattern and dispersion tolerant statistical reference oscillator.
Most wired communication systems including a phase locked loop (PLL) with a limited pull-in range require an additional frequency acquisition loop. A phase frequency detector (PFD) which is typically used in the frequency acquisition loop requires an external reference clock such as a crystal oscillator. This causes the increase of the cost and electric power consumption of an entire system.
Various reference-less clock and data recovery (CDR) technologies directly extract data rate from input data. Also, some of the technologies make use of a frequency detector based on a finite-state machine (FSM). Another technology makes use of a frequency locked loop (FLL) based on a delay locked loop (DLL). Further another technology makes use of a line coding analyzer.
However, the technologies mentioned above have a limit in being commercialized in a high speed wired communication industry because it is difficult to manufacture a complex logic block which operates at a speed of the input data. Moreover, the logic block excessively consumes electric power and depends on the kind of an oscillator which is used and on the pattern of the input data.
Regarding a prior art voltage controlled delay line (VCDL), all of the chips cannot provide the same delay due to process voltage and temperature (PVT) variation. Therefore, this causes inaccurate frequency locking.
Consequently, demand on a technology are made, which makes it possible to easily manufacture the logic block, to reduce electric power consumption of the logic block and to provide accurate frequency locking.
One embodiment is a statistical reference oscillator. The statistical reference oscillator includes: a stochastic reference clock generator which receives an input data outputs a reference signal obtained by dividing the received input data at a first frequency division ratio; a frequency divider which divides the frequency of an output signal at a second frequency division ratio and outputs a feedback signal; a frequency detector which outputs a difference signal based on a difference between the reference signal and the feedback signal; and an output signal generator which outputs the output signal based on the difference signal.
The stochastic reference clock generator includes a multiple threshold slicer and a frequency divider. The multiple threshold slicer detects a signal of the input data by using multiple thresholds. The frequency divider of the stochastic reference clock generator divides an input signal from the multiple threshold slicer at the first division ratio.
The statistical reference oscillator may further include a CID compensation block which prevents a non-random signal within the input data from being inputted to the frequency detector by skipping the non-random signal.
a to 21d show examples of the structures and operations of a conventional single threshold slicer and a multiple threshold slicer;
Hereafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. It is noted that the same reference numerals are used to denote the same elements throughout the drawings. In the following description of the present invention, the detailed description of known functions and configurations incorporated herein is omitted when it may make the subject matter of the present invention unclear.
In the embodiment, a frequency locked loop (FLL) is configured by the frequency divider 400, the frequency generator 200 and the output signal generator 300.
The SRCG 100 according to the embodiment may include a multiple threshold slicer 110 and a frequency divider 120. The multiple threshold slicer 110 detects a signal of the input data by using multiple thresholds and inputs the detected input data signal to the frequency divider 120. This will be described later in detail in connection with
The frequency divider 120 generates and outputs a signal like a clock signal by dividing the input data at a first frequency division ratio “N”. Such an output signal of the frequency divider 120 is designated as a reference signal. A transition probability of a random non-return-to-zero (NRZ) signal is 50%. Therefore, when input random data is divided by the frequency divider, the divided signal is outputted as if it were a reference clock having a duty cycle of 50% with the increase of the number of divisions. This is shown in
A time interval between neighboring transition edges of the random data divided by the frequency divider 120 according to the embodiment may be modeled by using a negative binomial random process. The time interval may be defined as an edge separation.
The negative binomial random process is represented by the number of repetitive trials until the occurrence of the expected number of successes. The number of the successes in the embodiment corresponds to the number of specific data transitions and the number of the trials corresponds to a unit interval (Tunit) of the divided random data.
In the random NRZ signal, a probability that a specific data transition occurs at an edge of the unit interval is 0.5. Cases in which the data transition occurs are independent of each other. If the frequency divider detects only a specific edge (e.g., a rising edge), a transition from the N-divided data to a specific data occurs every 2N data transitions. In this case, a probability that the specific edge exists in two unit interval (2Tunit) the divided random signal is 0.5.
Accordingly, through analysis of the N-divided signal, a mean μ and a variance σ2 of the edge separation are as follows:
The average frequency of the N-divided signal is p/(2NTunit).
When the mean and the variance of the edge separation increase linearly with respect to “N”, an RMS period jitter (Jperiod) of the SRCG 100 according to the embodiment may be defined as follows:
Through equation (3), the Jperiod is inversely proportional to N1/2. That is, an output spectrum of the divided NRZ signal becomes closer to the clock signal with the increase of the division ratio.
The mean, variance and period jitter of the divided data are shown in the following Table 1.
An absolute jitter which is defined as a maximum phase deviation from an ideal clock edge is represented by a phase noise “L(f)” in a frequency domain. A phase jitter is defined as a time difference between an ideal cycle and an actual cycle. The radian of φk which is a phase jitter in the kth cycle is represented in the following radian expression.
φk=2πf0(tk−kT0) Equation (4)
Here, T0 represents a cycle of the signal. Total output jitter is as follows:
Here, Sφ represents a power spectrum density (PSD) of the phase jitter φk.
The cycle of the SRCG is 2μES. The period jitter is represented in the following equation.
Here, tk represents a zero crossing time of the Kth cycle. T0=1/f0 represents a clock cycle. A period jitter sequence corresponds to a first derivative of an absolute jitter sequence, which can be modeled into D(z)=1−z−1 in a Z domain. Therefore, Sφ(ƒ), that is, a power spectrum density function of an absolute phase jitter has the following relation with the power spectrum density function of the period jitter.
SΔφ(ƒ)=Sφ(ƒ)|D(z)D(z−1)|z=e
The variance of the period jitter of σΔφ2 is equal to 2σES2 of Equation (2) and has the following relation with SΔφ.
Since the period jitter of the SRCG is an independent white process, the power spectrum density function SΔφ(ƒ) is a constant as follows:
The power spectrum density of the absolute phase is represented by equation (7) as follows:
D(z) of equation (7) is bilinearly transformed as follows:
An absolute power spectrum density (PSD) function of the divided NRZ signal linearly reduces in a 1/f2 region as the division ratio increases. A high frequency phase noise floor is located at π2(1−p)Tunit/p2 and h as nothing to do with the division ratio.
The simulation result is exactly the same as equation (10). The simulation result is appropriately approximated to equation (11) in the 1/f2 region and is somewhat discrepant from equation (11) in a high frequency region. This is because that the bilinear transformation maps a region corresponding to −π<Ω<π in the Z domain on a region of −∞<f<∞ in a continuous time domain. However, the high frequency region phase noise floor which is expected through the bilinear transformation is equal to the minimum value of equation (10) and well represents an actual phase noise floor.
A SRCG output signal may be computed by using a PSD characteristic function expression 11 of xs(t+φ(t)). Here, since the φ(t) can be modeled by using Gaussian process when “N” is sufficiently large, the φ(t) is represented as follows:
Here, c represents a power spectrum density function given by SΔφ/(2π)2=σΔφ2/T0. Xi represents a Fourier coefficient of xs(t) and is defined as follows:
A normalized form of the single side band power spectrum is as follows:
Here, Sss(f)=2S(2πf). The L(fm) approximated with respect to “c” of a small value and 0≦fss<<f0 is represented as follows:
A line width of the SRCG (fLW) is as follows:
Since the line width and average cycle depend on only the parameter “N”, a
normalized line width transfers much better information on the output signal of the SRCG. The normalized line width is represented as follows.
The normalized line width is proportional to 1/N. The phase noise of the SRCG is reduced as the “N” increases.
Here, a frequency range is
In the SRCG according to the embodiment, when the division ratio is not sufficiently large, a common phase frequency detector may malfunction with the SRCG according to the embodiment.
Such a problem can be alleviated by using a frequency detector which is not sensitive to the accumulated phase jitter. Accordingly, as shown in
An operation principle of a common rotational frequency detector used as the frequency detector 200 is shown in
Here, Δφk represents a phase difference between the kth divided clock signal of the VCO and the reference clock (output signal of the SRCG 100). TREF and TCLK mean one cycle of the reference clock and one cycle of the feedback signal respectively. fREF and fCLK correspond to a frequency of the reference signal and a frequency of the feedback signal respectively. A phase domain transfer function of the FD, which uses z-transform, is as follows.
In order to represent S-domain, the following result is obtained by applying the bilinear transformation on equation (21).
Here, T0 represents an average cycle during a phase update at the frequency of the SRCG output signal.
In the statistical reference oscillator according to the embodiment, the FLL connected to the SRCG is designed in such a manner as to reduce the jitter coming from the SRCG and to refine the shape of the jitter.
Here, KVCO represents a yield of the voltage controlled oscillator (VCO) 320. ICP represents a current of a charge pump. “C” represents a capacitance of a loop filter. “N” represents a division ratio of the frequency divider. The more the division ratio increases, the more the gain of the FLL increases. However, the bandwidth of the FLL is constant. This is because a first pole is represented as follows regardless of the “N”.
An output power spectrum density function of the FLL, which receives the output signal of the SRCG, is given as follows.
When the division ratio “N” is increased, an output phase noise of the SRCG is, as shown in
A common rotational frequency detector (RFD) samples the reference clock by using a multi phase VCO clock, and then extracts a frequency difference between the VCO and the reference clock. A phase difference between the neighboring samples includes frequency information. A general transfer characteristic of the RFD is shown in
The FD created by using a counter counts by using the VCO clock signal during one cycle of the reference clock signal and extracts a frequency difference from a difference between the reference value “M” and the number of the count. The reference value “M” corresponds to the counted number when the desired frequency is locked by the FLL. In this case, as shown in
However, if the “M” is smaller, a quantization effect is obtained as shown in
Actually, the output of the frequency detector 200 is continuous during a time sample interval T0 for holding an update signal. This process may be modeled by zero-order-hold (ZOH) of a cycle of T0. A frequency response of the ZOH process appears on a phase noise curve. A frequency domain transfer function of the ZOH process is as follows:
Through multiplication of equation (25) and equation (26), the phase noise may be represented to show the ZOH effect.
Equation (26) is bilinearly transformed, and then an asymptotic line of equation (27) may be obtained as follows:
The position of the pole of the asymptotic line by the ZOH corresponds to
When a clock and data recovery (CDR) has a signal to noise ratio (SNR) penalty due to channel dispersion, the SRCG sharing the same input with the CDR generates a signal similar to the clock. However, the frequency of the signal may be lower than the frequency of an ideal clock. An error generated in the CDR in an environment including the dispersion causes the SRCG to miss a valid data transition. Therefore, due to the dispersion, data may remain without being partitioned. That is, in an environment including the dispersion and noise, it may occur that the SRCG is not able to correctly detect the input data. In this case, consequently, the frequency is locked in an undesired value.
a and 21b show a structure and operation of the SRCG including a conventional single threshold slicer. In
Therefore, in the embodiment, the multiple threshold slicer 110 may be used to errorlessly detect the signal transformed due to the dispersion and/or noise.
c and 21d show an example of the structure and operation of the SRCG which includes the multiple threshold slicer 110 according to the embodiment and is tolerant of the dispersion.
As shown in
In in conjunction with the structure of
the input signal transformed due to the dispersion and noise through the multiple threshold slicer can be detected without errors. Accordingly, it can be found that the frequency of the divided signal detected through the multiple threshold slicer 110 is the same as an frequency of an ideal case.
In
The multiple threshold slicer 110 according to the embodiment can be implemented as shown in
As shown in
The charge pump 310 increases or decreases its output voltage in response to the up-pulse signal and the down-pulse signal. The statistical references oscillator according to the embodiment may further include a low pass filter (not shown) which removes noise and high frequency components which are included in the output voltage of the charge pump 310.
The voltage controlled oscillator (VCO) 320 outputs a frequency-compensated signal by using the output voltage of the charge pump 310. Consequently, the voltage controlled oscillator (VCO) 320 increases an output frequency by using the width of the up-pulse signal which is output from the frequency detector 200 or decreases an output frequency by using the width of the down-pulse signal.
As shown in
For example, when data including a consecutive identical digit (CID) which may exist in the frame header is divided, duration of the reference signal is increased and a signal output from the voltage controlled oscillator (VCO) 320 comes to have a locking frequency lower than that of an ideal case. Therefore, in order to remove such an error, it is required that the signal having the increased duration should be skipped during the process in which the data is divided by the frequency divider 120.
The skipping process will be described in short below. First, a mean and a variance of the signal from the divided input data are theoretically calculated. It is possible to calculate from the calculated mean and variance by using “student-distribution” how much less the duration of the signal should be with the reliability of 95% or 99%. The duration of the signal can be calculated by counting how many signals of VCO/16 are pulled in during the half cycle of the divided input data. When the statistical reference oscillator including the calculated t-test value is included in a predetermined locking range, the CID compensation block 500 is turned on. Here, when an undesired signal, that is, the CID within the frame header is generated, updating is skipped.
While the embodiment of the present invention has been described with reference to the accompanying drawings, it can be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from its spirit or essential characteristics. Therefore, the foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the foregoing embodiments is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.
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