Patent Application
20170093413
This application is based upon and claims the benefit of priority from Japanese patent application No. 2015-190868, filed on Sep. 29, 2015, the disclosure of which are incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a signal processing apparatus for a measuring machine.
2. Description of Related Art
Measuring machines are required to detect an output signal of a sensor with high-resolution.
Here, the resolution is determined based on an amplification factor of a preamplifier and the number of bits of an analog-to-digital (AD) converter. On the other hand, if the sensor output varies over a wide range, the dynamic range needs to be enlarged.
The dynamic range is also determined based on the amplification factor of the preamplifier and the number of bits of the AD converter. The resolution and the dynamic range have a trade-off relation; the dynamic range becomes narrower as the resolution becomes higher.
Conventionally, the gain (amplification factor) of the preamplifier has been switched according to the range. For example, in the signal processing apparatus for the measuring machine disclosed in JP 2002-162251 A, a user can gradually switch the range as needed. The CPU automatically adjusts the gain according to the range selected by the user.
However, as long as the number of bits of an AD converter is fixed, resolution and a dynamic range keeps a trade-off relation, and it is difficult to perform measurement with a wide dynamic range and high resolution.
A purpose of the present invention is to provide a signal processing apparatus, which can perform measurement with a wide dynamic range and high resolution, for a measuring machine.
A signal processing apparatus for a measuring machine in an aspect of the present invention is the signal processing apparatus, which converts an analog sensor signal corresponding to a measurement value into a digital signal to be used as measurement data, for the measuring machine, the apparatus including:
a first analog-to-digital (AD) converter configured to AD-convert the sensor signal into an upper digital signal;
a first digital-to-analog (DA) converter configured to DA-convert the upper digital signal into an upper analog signal;
a first combining unit configured to generate a lower analog signal by subtracting the upper analog signal from the sensor signal;
an amplifier configured to generate a magnified lower analog signal by magnifying the lower analog signal;
a second AD converter configured to AD-convert the magnified lower analog signal into a lower digital signal; and
a second combining unit configured to combine the upper digital signal regarded as upper side digits with the lower digital signal regarded as lower side digits.
In an aspect of the present invention, resolution of the first DA converter may be set to be equal to or lower than resolution of the first AD converter.
In an aspect of the present invention, the resolution of the first AD converter may be set to be equal to the resolution of the first DA converter.
A measuring machine in an aspect of the present invention includes the signal processing apparatus for the measuring machine and a sensor.
An embodiment of the present invention is illustrated and described with reference to the reference signs attached to the elements in the drawings.
Processing performed by each functional unit is described along the path of a signal in order.
First, a sensor signal E1 is input from a sensor circuit 400 to the signal processing apparatus 100. An example of the sensor signal E1 is illustrated in
For example, the sensor signal E1 is composed of a signal of waviness and fine-unevenness superimposed on an outline as a whole as illustrated in
The sensor signal E1 is branched into two; one is input to a first analog-to-digital (AD) converter 110, and the other is input to a first combining unit 140.
The sensor signal E1 is converted into a digital signal by the first AD converter 110. An example of the result of the AD-converted sensor signal E1 is illustrated in
The signal converted into the digital signal by the first AD converter 110 is referred to as an upper digital signal E2.
As illustrated in
The upper digital signal E2 is branched into two; one is input to a second combining unit 170, and the other is input to a first digital-to-analog (DA) converter 120.
The upper digital signal E2 is converted into an analog signal again by the first DA converter 120. The signal converted into the analog signal by the first DA converter 120 is referred to as an upper analog signal E3.
An example of the upper analog signal E3 is illustrated in
The upper analog signal E3 is obtained by removing the variation below the resolution of the first AD converter 110 from the sensor signal E1.
The upper analog signal E3 is input to the first combining unit 140 after an inverting circuit 130 performs inversion processing. The signal inverted by the inverting circuit 130 is referred to as an inverted upper analog signal E4, and an example thereof is illustrated in
To the first combining unit 140, the sensor signal E1 is input from the one input end, and the inverted upper analog signal E4 is input from the other input end.
The first combining unit 140 combines the sensor signal E1 with the inverted upper analog signal E4. The signal obtained by combining the sensor signal E1 with the inverted upper analog signal E4 is referred to as a lower analog signal E5, and an example thereof is illustrated in
The lower analog signal E5 is obtained by extracting the variation below the resolution of the first AD converter 110 from the sensor signal E1.
The lower analog signal E5 is amplified by an amplifier 150, and the amplified signal is referred to as a magnified lower analog signal E6.
An example of the magnified lower analog signal E6 is illustrated in
The signal converted into the digital signal by the second AD converter 160 is referred to as a lower digital signal E7, and an example thereof is illustrated in
The lower digital signal E7 is input to the second combining unit 170.
To the second combining unit 170, the upper digital signal E2 is input from the one input end, and the lower digital signal E7 is input from the other input end.
The second combining unit 170 combines the upper digital signal E2 with the lower digital signal E7.
At this time, the upper digital signal E2 is regarded as upper side bits, and the lower digital signal E7 is regarded as lower side bits. Then, a combined digital signal E8 illustrated in
The combined digital signal E8 obtained in this manner is measurement data having a wide dynamic range as well as high resolution.
In
Furthermore, as an example, circuit conditions are set as follows:
The measurement range of the sensor is 819.2 um, and the sensor signal E1 is an electric signal having the amplitude of 10 V.
The first AD converter 110 and the first DA converter 120 have the input range of 10 V and the resolution of 7 bits.
Note that, the resolution of the first AD converter 110 is set to be equal to that of the first DA converter 120.
The gains of the operational amplifiers AMP1 and AMP2 which constitute the inverting circuit 130 and the first combining unit 140 respectively are one time, and the gain of the operational amplifier AMP3 constituting the amplifier 150 is 64 times.
The second AD converter 160 has the input range of 10 V and the resolution of 16 bits.
At this time, in the lowest bit (LSB) of the first AD converter 110 and the first DA converter 120, the amplitude level is 78.125 mV and the resolution is equivalent to 6.4 μm.
Here, the second AD converter 160 is described.
The bits below the lowest bit (LSB) (6.4 μm) of the first AD converter 110 and the first DA converter 120 are magnified to the amplitude of 10 V (that is, 128 times), and is expressed with 16 bits.
Thus, the lowest bit (LSB) of the second AD converter 160 is equivalent to 0.000097656 um.
In other words, that the second combining unit 170 combines the upper digital signal with the lower digital signal means that digital conversion can be performed with high resolution equivalent to 23 bits.
819.2 um/0.000097656 um=8388629=(equivalent to) 23 bits
Note that, in order for the first combining unit 140 to combine the sensor signal E1 with the inverted upper analog signal E4, it is necessary that the delay of the inverted upper analog signal E4 to the sensor signal E1 is taken into consideration.
When it is assumed that the sensor signal E1 is a sine wave, the inverted upper analog signal E4 needs to be generated in a half period of the sensor signal E1.
It is assumed that the total delay of the first AD converter 110, the first DA converter 120, and the inverting circuit 130 is td, and the number of bits of the first AD converter 110 (the first DA converter 120) is n.
Furthermore, it is assumed that he shortest period of the sensor signal E1 is Tmin, and the maximum frequency is Fmax.
At this time, T min/2=td×2n is established, and thus Fmax=1/(2×td×2n) is established.
Note that, the present invention is not limited to the above embodiment, and can be appropriately changed without deviating from the scope.
In the above example, the inverting circuit 130 is interposed, but if, for example, the first DA converter 120 performs output inversely, the inverting circuit 130 is not necessary.
Alternately, as long as the first combining unit 140 functions as a subtracting device, the inverting circuit 130 may be omitted.
In the embodiment, it has been exemplified that the resolution of the first AD converter 110 is to be equal to that of the first DA converter 120, but the resolution of the first AD converter 110 may be different from that of the first DA converter 120, and, for example, the resolution of the first DA converter 120 may be lower than that of the first AD converter 110.
It is needless to say that the kind of sensor is not limited.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-190868 | Sep 2015 | JP | national |
