Patent Grant
10644864
This application is a U.S. National Phase of International Patent Application No. PCT/JP2016/065861 filed on May 30, 2016, which claims priority benefit of Japanese Patent Application No. JP 2016-002797 filed in the Japan Patent Office on Jan. 8, 2016 and also claims priority benefit of Japanese Patent Application No. JP 2015-118755 filed in the Japan Patent Office on Jun. 11, 2015. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.
The present technology relates to a signal processing device, a signal processing method, and a program. More particularly, the present technology relates to a signal processing device that processes TLV packets, a signal processing method, and a program.
In digital broadcasting, for example, images (moving images) and the like are encoded by a predetermined encoding method such as Moving Picture Experts Group (MPEG), and the resultant encoded data is placed as the payloads in transport stream (TS) packets. Broadcast waves including TSs formed with such TS packets are transmitted in digital broadcasting. Receivers that receive and process such broadcast waves are also widely used.
Meanwhile, a transition from broadcasting using TS to broadcasting using the Internet Protocol (IP) has also been suggested (see Non-Patent Document 1, for example).
There is a demand for receivers that are compatible with TS packets and are capable of processing new kinds of broadcasts, such as broadcast waves using IP.
The present technology has been developed in view of those circumstances, and is to enable processing of broadcast waves using IP.
A signal processing device of one aspect of the present technology includes: a demodulation processing unit that performs a demodulation process; a processing unit that performs a demux process; and a data signal line, a clock signal line, a sync signal line, and a valid signal line that are provided between the demodulation processing unit and the processing unit. In the signal processing device, a variable-length packet is transmitted between the demodulation processing unit and the processing unit through the data signal line, the clock signal line, the sync signal line, and the valid signal line.
The variable-length packet may be an Internet Protocol (IP) packet.
The variable-length packet may be a Type Length Value (TLV) packet.
The variable-length packet to be transmitted from the demodulation processing unit to the processing unit via the data signal line may be at least part of a TLV packet.
The variable-length packet may be a TLV packet, a GSE packet, a GSE-Lite packet, or an IP packet.
The data signal line may be formed with one to eight data signal lines, and serial transmission or parallel transmission may be performed in accordance with the number of provided data signal lines.
Transmission of the variable-length packet may be performed with an optional bit width of one to eight bits.
The clock signal line may transmit a clock signal, the sync signal line may transmit a sync signal indicating the position of the top of a packet, and the valid signal line may transmit a valid signal indicating a data valid section.
The processing unit may latch data from the demodulation processing unit at a rising edge or a falling edge of the clock signal.
The valid signal may be a signal constantly indicating that data is valid, and the clock signal may be set at a frequency corresponding to the bit width of the data signal line.
The valid signal may be a signal constantly indicating that data is valid, and oscillation of the clock signal may be suspended during a byte gap.
The clock signal may constantly oscillate at a predetermined frequency, and the valid signal may be lowered during a byte gap.
During an in-packet gap or an inter-packet gap, oscillation of the clock signal may be suspended.
The variable-length packet may be a TLV packet, and error information indicating whether there is an error in a packet may be included in a packet header area of the TLV packet.
The variable-length packet may be a TLV packet, and error information indicating whether there is an error in a packet may be included in an area in which information about the type of a packet included in the TLV packet is written.
The signal processing device may further include an error signal line that transmits the error information.
The error information may be transmitted for each error correction code, or be transmitted for each variable-length packet.
The demodulation processing unit may convert a partial TLV packet compliant to the ISDB-C standards into a TLV packet, and transmit the TLV packet to the processing unit.
The demodulation processing unit may transmit a J.382-compliant GSE packet to the processing unit.
The demodulation processing unit may convert a J.382-compliant GSE packet into a TLV packet, and transmit the TLV packet to the processing unit.
The demodulation processing unit may transmit an ATSC-compliant ALP packet to the processing unit.
The header of the ALP packet may include at least 2-bit type information as information indicating the type of data placed in a payload, and 1-bit error information indicating whether there is an error in a packet.
The type information may be information for identifying four packet types among the following five packet types: an IP packet of IPv4, a compressed IP packet, an LLS packet, an extension packet, and a TS packet compliant with MPEG2-TS.
In a case where there is an error in a packet, a sync signal to be transmitted by the sync signal line and a valid signal to be transmitted by the valid signal line may not simultaneously rise.
A signal processing method of one aspect of the present technology is a signal processing method implemented in a signal processing device that includes: a demodulation processing unit that performs a demodulation process; a processing unit that performs a demux process; and a data signal line, a clock signal line, a sync signal line, and a valid signal line that are provided between the demodulation processing unit and the processing unit. The signal processing method includes the step of transmitting a variable-length packet between the demodulation processing unit and the processing unit, using the data signal line, the clock signal line, the sync signal line, and the valid signal line.
A program of one aspect of the present technology causes a computer to perform a process. The computer includes: a demodulation processing unit that performs a demodulation process; a processing unit that performs a demux process; and a data signal line, a clock signal line, a sync signal line, and a valid signal line that are provided between the demodulation processing unit and the processing unit. The process includes the step of transmitting a variable-length packet between the demodulation processing unit and the processing unit, using the data signal line, the clock signal line, the sync signal line, and the valid signal line.
In a signal processing device, a signal processing method, and a program of one aspect of the present technology, a demodulation processing unit that performs a demodulation process, and a processing unit that performs a demux process are provided, and a data signal line, a clock signal line, a sync signal line, and a valid signal line are provided between the demodulation processing unit and the processing unit. The data signal line, the clock signal line, the sync signal line, and the valid signal line are used in transmitting a variable-length packet between the demodulation processing unit and the processing unit.
According to one aspect of the present technology, broadcast waves using IP can also be processed.
It should be noted that the effect of the present technology is not necessarily limited to that described herein, and may be any effect described in the present disclosure.
The following is a description of modes (hereinafter referred to as embodiments) for carrying out the present technology. It should be noted that the description will be made in the following order.
1. Configuration of a receiver
2. TLV packet
3. Signal lines
4. Where the clock signal changes, but the valid signal does not change
5. Where the clock signal is suspended, and the valid signal does not change
6. Where the clock signal constantly oscillates, and the valid signal is lowered as appropriate
7. Signals during a gap in a packet or between packets in the case of 8-bit parallel transmission
8. Signals during a gap in a packet or between packets in the case of 1-bit serial transmission
9. Transmission of an error signal
10. Processing of an NTP
11. First output pattern of data
12. Second output pattern of data
13. Third output pattern of data
14. Fourth output pattern of data
15. Fifth output pattern of data
16. Outputting an NTP at regular intervals
17. Application to Cable Retransmission
18. Application to ALP
19. Description of a computer to which the present technology is applied
The present technology described below can be applied to a receiver in a broadcasting system, and therefore, explanation of an example of a receiver in a broadcasting system is continued below.
The system is also designed so that broadcast waves can be transmitted from the transmitter 10 to the receiver 11 via the network 12. Also, transmission via the network 12 may be transmission of information related to content being broadcast.
An example case where broadcast waves from the transmitter 10 are transmitted by a method called MPEG Media Transport (MMT)+Type Length Value (TLV), and are received by the receiver 11 is now described. The MMT+TLV method is a method of transmitting a video signal, an audio signal, and a control signal stored in an Internet Protocol (IP) packet. With this method, the distinction between broadcasting and communication as transmission channels is eliminated.
By this method, broadcast waves and a communication channel can be simultaneously used, and it becomes possible to adopt such a type of broadcasting that a video image captured by a main camera for unspecified viewers is transmitted by broadcast waves, and a video image captured by a sub camera selected by an individual viewer is transmitted via a communication channel (the network 12).
<Configuration of the Receiver>
As the present technology can be applied to the receiver 11 that receives and processes broadcast waves transmitted by the above described MMT+TLV method, the configuration of the receiver 11 is now described in greater detail.
A receiving system that includes the receiver 11 includes an antenna 31, the receiver 11, and a display 32. The receiver 11 includes a tuner 41, a demodulation processing unit 42, and a processing unit 43. The demodulation processing unit 42 includes a demodulation unit 51 and an error correction unit 52. The processing unit 43 includes a multiplexing/separating unit 53 and a decoder 54.
The antenna 31 receives TLV digital broadcast waves transmitted from the transmitter 10, for example, and supplies the resultant reception signal to the receiver 11. The receiver 11 restores and processes the TLV from the reception signal received from the antenna 31, extracts a video image and sound, and outputs the video image and the sound to the display 32.
The error correction unit 52 performs error correction on a demodulation signal from the demodulation unit 51, and supplies the resultant TLV signal or the like to the processing unit 43. The processing unit 43 may be formed with a system-on-a-chip (SOC), for example. The processing unit 43 performs a demux process, such as a process of separating video content into a video portion, an audio portion, a subtitles portion, and the like.
The processing unit 43 is supplied with a sync signal, a valid signal, a data signal, and a clock signal as signals output from the demodulation unit 51.
The multiplexing/separating unit 53 of the processing unit 43 separates the video data and the audio data contained in the data signal from each other, for example. The decoder 54 decodes the video data into a video signal, and decodes the audio data into an audio signal, to generate video and audio signals. The decoder 54 then outputs the video and audio signals to the display 32.
<TLV Packet>
Referring now to
Broadcast waves are transmitted from the transmitter 10 frame by frame, as shown in
One frame may be formed with streams of the same broadcast station, or one frame may include streams of different broadcast stations. Further, the number of streams included in one frame is not necessarily three, though
Meanwhile, one frame is formed with 120 slots. In the example shown in
Although an example case where 120 slots are included in one frame is described herein, the number of slots is not necessarily 120. It should be noted that the upper limit for the number of slots included in one frame is fixed at 120 by ARIB STD-B44, for example, and therefore, is fixed at 120 in a case where this rule is complied with.
One slot includes one or more TLV packets. Since a TLV packet has a variable length as described later, the number of packets included in one slot may vary by slot.
Some of the slots (some of the TLV packets) include packets containing a network time protocol (NTP). An NTP is time information, and is allotted to each TLV stream ID. An NTP is used so that a clock based on received time information in the NTP format can be reproduced and stored on the side of the receiver 11.
An NTP is placed at one point in one frame among the streams with the same TLV stream ID. In
Even in a case where slots of one broadcast station are scattered in one frame, an NTP is disposed at a predetermined point among the TLV streams in one frame.
As shown in the upper portion of
The packet type area is allocated as the area to be used for identifying the type of the packet to be stored in the TLV, and the allocation is shown in the lower portion of
The data length area is the area in which the number of data bits that follow is written. The area of data (data area) is formed with (8×N) bits, and is a variable-length area. Data is to be written into the data area.
In a case where a value “0x01” is written in the packet type area, for example, the data format in the data area is an IPv4 packet. In a case where the data format in the data area is an IPv4 packet, the IP packet in the data area has the structure shown in the second row in
As shown in the second row in
In a case where a value “0x02” is written in the packet type area, for example, the data format in the data area is an IPv6 packet. In a case where the data format in the data area is an IPv6 packet, the IP packet in the data area has the structure shown in the third row in
As shown in the third row in
In a case where a value “0x03” is written in the packet type area, for example, the data format in the data area is an IP packet with a compressed header. In a case where the data format in the data area is an IP packet with a compressed header, the IP packet in the data area has the structure shown in the fourth row in
As shown in the fourth row in
As described above, a TLV packet includes an IP packet.
<Signal Lines>
Meanwhile, there is a device that processes transport stream (TS) packets and is used as a conventional receiver 11, for example. To be able to process TLV packets in such a device, and to process TLV packets as a new device, the process described below is performed.
The demodulation processing unit 42 may be an LSI that performs a demodulation process. In addition, the processing unit 43 may be an LSI that performs a demux process. The demodulation processing unit 42 and the processing unit 43 may be formed with one LSI, or may be formed with different LSIs. In a case where the demodulation processing unit 42 and the processing unit 43 are formed with different LSIs, the demodulation processing unit 42 needs to output data so that the processing unit 43 in the next stage can process the data (or the conditions required by the processing unit 43 are satisfied).
According to the present technology, the demodulation processing unit 42 can supply data demodulated in such a format that satisfies the conditions required by the processing unit 43.
In the example case described below, the demodulation processing unit 42 and the processing unit 43 are formed as different LSIs. As shown in the upper diagram in
Of the four signal lines, one is a 1-bit signal line for transmitting a sync (SYNC) signal, one is a 1-bit signal line for transmitting a valid (VALID) signal, one is a 1-bit signal line for transmitting a clock (CLK) signal, and one is a 1-bit signal line for transmitting a data (DATA) signal. The data signal line might be formed with one to eight signal lines corresponding to one to eight bits.
For example, the data signal line is formed with one signal line in the case of serial transmission, and the data signal line is formed with eight signal lines in the case of 8-bit parallel transmission. Parallel transmission is not limited to eight bits, but may involve any appropriate number of bits. In accordance with the number of bits, signal lines are arranged. As described below, according to the present technology, the sync signal, the valid signal, and the clock signal can be controlled in accordance with the number of data signal lines (or the number of bits to be transmitted in one cycle of the clock signal).
Alternatively, as shown in the lower diagram in
The clock signal is a signal indicating the output timing of the data forming the TLV. The clock signal is a pulse-like signal that repeatedly switches between the L-level and the H-level.
The sync signal indicates the timing of the top of each packet included in the TLV. Only at the timing of the top of each packet, for example, the sync signal temporarily switches from the low (L) level to the high (H) level.
The valid signal indicates the sections (valid sections) in which a packet exists in the TLV. For example, the valid signal is at the H-level in the valid sections, and is at the L-level in the sections (invalid sections) other than the valid sections.
The data signal is a TLV signal, and includes all or part of each TLV packet. A packet has a data length (packet length) of four to 65535 bytes, for example.
Although not shown in the drawing, if an error signal line is provided, an error signal is also transmitted. The error signal is at the H-level when there is an error, and is at the L-level when there is not an error.
The data signal supplied from the demodulation processing unit 42 to the processing unit 43 is all or part of a TLV packet. Referring now to
Transmission data A is the data of the entire TLV packet. In this case, all the data in the TLV packet, from the packet header of the TLV packet to the data area, is supplied from the demodulation processing unit 42 to the processing unit 43.
Transmission data B is the data of the entire TLV packet, except for the packet header. In this case, the data in the packet type area, the data in the data length area, and the data in the data area in the TLV packet are supplied from the demodulation processing unit 42 to the processing unit 43.
Transmission data C is the data in the data area in the TLV packet. In this case, the data in the data area in the TLV packet is supplied from the demodulation processing unit 42 to the processing unit 43.
Transmission data D is the data other than the IPv4 header of an IPv4 packet in a case where the data in the data area in the TLV packet is an IPv4 packet. In this case, the data in the UDP header portion and the data in the data portion in the IPv4 packet are supplied from the demodulation processing unit 42 to the processing unit 43.
Transmission data E is the data portion in an IPv4 packet (or the payload of a UDP packet) in a case where the data in the data area in the TLV packet is an IPv4 packet. In this case, the payload of the UDP packet in the IPv4 packet is supplied from the demodulation processing unit 42 to the processing unit 43.
Transmission data F is the data other than the IPv6 header of an IPv6 packet in a case where the data in the data area in the TLV packet is an IPv6 packet. In this case, the data in the UDP header portion and the data in the data portion in the IPv6 packet are supplied from the demodulation processing unit 42 to the processing unit 43.
Transmission data G is the data portion in an IPv6 packet (or the payload of a UDP packet) in a case where the data in the data area in the TLV packet is an IPv6 packet. In this case, the payload of the UDP packet in the IPv6 packet is supplied from the demodulation processing unit 42 to the processing unit 43.
Transmission data H is the data portion (or the payload) in a compressed IP packet in a case where the data in the data area in the TLV packet is a compressed IP packet. In this case, the payload of the compressed IP packet is supplied from the demodulation processing unit 42 to the processing unit 43.
For example, in the case of the processing unit 43 requesting a supply of the entire TLV packet, the transmission data A is transmitted from the demodulation processing unit 42. Also, in the case of the processing unit 43 requesting a supply of part of the TLV packet, for example, one set of the transmission data B through H is transmitted from the demodulation processing unit 42 in accordance with the requested data.
In this manner, all or part of the TLV packet is supplied from the demodulation processing unit 42 to the processing unit 43. The TLV packet is a variable-length packet, and is a packet including an IP packet as described above. Such a TLV packet is transmitted from the demodulation processing unit 42, and is received by the processing unit 43.
In addition, the supply of the TLV packet is conducted at the timing based on the clock signal, the sync signal, and the valid signal, which have been described above with reference to
As described above, the data signal line might be formed with one to eight signal lines (one to eight bits). In the description below, the following example cases will be explained: an example case where one data signal line is provided, and 1-bit serial transmission is performed; an example case where the number of data signal lines is two, and 2-bit parallel transmission is performed; an example case where the number of data signal lines is four, and 4-bit parallel transmission is performed; and an example case where the number of data signal lines is eight, and 8-bit parallel transmission is performed.
It should be noted that the present technology can be applied to transmission other than the above described transmission, such as 3-bit parallel transmission, and is not limited to the example cases described below.
<Where the Clock Signal Changes, But the Valid Signal Does Not Change>
Referring first to
The processing unit 43 can receive (latch) the data of a data signal at each rising edge of the clock signal. It should be noted that, although data is to be latched at each rising edge of the clock signal in the description continued below, data may be latched at each falling edge of the clock signal.
The clock signal shown in
As described above, the valid signal is maintained at the H-level, which indicates a valid section, and the frequency of the clock signal varies with the number of bits to be transmitted at once. In this manner, data is transmitted.
For example, in a case where eight data signal lines are provided between the demodulation processing unit 42 and the processing unit 43, data is transmitted in accordance with the clock signal and the valid signal shown in
In each of the cases of the clock signals described above with reference to
As is apparent from a comparison between the frequency of the clock signal in the 8-bit parallel transmission shown in
If the number of bits to be transmitted in one cycle of the clock signal is small, or, in other words, if the number of signal lines is small, or, further in other words, if the number of pins to be used for data transmission among the pins of the LSI forming the processing unit 43 is small, the frequency of the clock signal is high. Meanwhile, broadcasting is becoming even higher in resolution. As the resolution becomes higher, the amount of data to be transmitted from the demodulation processing unit 42 to the processing unit 43 becomes larger.
To transmit a larger amount of data, the frequency of the clock signal needs to be made higher. However, there is an upper limit to the frequency of the clock signal. Furthermore, power consumption cannot be effectively reduced simply by increasing the frequency of the clock signal.
For example, to transmit a large amount of data without an increase in the frequency of the clock signal, the number of pins in the LSI is increased, and for example, 8-bit parallel transmission is performed. However, not increasing the number of pins in the LSI is also desirable.
In view of the above facts, when the 4-bit parallel transmission shown in
<Where the Clock Signal Is Suspended, And the Valid Signal Does Not Change>
Referring now to
As the processing unit 43 latches the data of the data signal at a rising edge of the clock signal, the clock signal is suspended (lowered) after the passage of time equivalent to one cycle until the next data transmission timing (during a byte gap). The valid signal is always at the H-level, which means that the valid signal indicates a valid section in which a packet exists in this case.
As 8-bit data is transmitted in two cycles, and the processing unit 43 can also latch the 8-bit data in the two cycles, the clock signal is suspended (lowered) after the passage of time equivalent to two cycles until the next data transmission timing (during a byte gap).
As 8-bit data is transmitted in four cycles, and the processing unit 43 can also latch the 8-bit data in the four cycles, the clock signal is suspended (lowered) after the passage of time equivalent to four cycles until the next data transmission timing (during a byte gap).
As 8-bit data is transmitted in eight cycles, and the processing unit 43 can also latch the 8-bit data in the eight cycles, the clock signal is suspended (lowered) after the passage of time equivalent to eight cycles until the next data transmission timing (during a byte gap).
As described above, the valid signal is maintained at the H-level, which indicates a valid section, and the frequency of the clock signal remains the same regardless of the number of bits to be transmitted at once. The clock signal is in a suspended state after the transmission until the next transmission timing.
For example, in a case where eight data signal lines are provided between the demodulation processing unit 42 and the processing unit 43, data is transmitted in accordance with the clock signal and the valid signal shown in
In each of the cases of the clock signals described above with reference to
Furthermore, the clock signal is suspended during each byte gap. Thus, the power to be consumed on the clock frequency can be reduced, and the receiver 11 can be made to consume less power.
<Where the Clock Signal Constantly Oscillates, and the Valid Signal is Lowered as Appropriate>
Referring now to
As transmission of 8-bit data is completed in one cycle of the clock signal, the valid signal is suspended (lowered) after the passage of time equivalent to one cycle until the next data transmission timing (during a byte gap).
As described above, the valid signal is at the H-level only during the valid section, and the clock signal constantly oscillates regardless of the number of bits to be transmitted at once.
For example, in a case where eight data signal lines are provided between the demodulation processing unit 42 and the processing unit 43, data is transmitted in accordance with the clock signal and the valid signal shown in
In each of the cases of the clock signals described above with reference to
This is also effective for the processing unit 43 that cannot keep operating properly if the supply of the clock signal is stopped.
<Signals During a Gap in a Packet or Between Packets in the Case of 8-Bit Parallel Transmission>
The clock signal and the valid signal at a time of 8-bit data transmission have been described with reference to
An in-packet gap does not constantly appear, but appears in a parity portion or a portion existing in two slots or the like, for example. An inter-packet gap appears when there is no transmission data between packets, and appears in a portion in which a null packet exists.
Suspending the clock signal in portions in which an in-packet gap or an inter-packet gap appears is now described.
Referring to
The sync signal indicates the timing of the top of each packet included in the TLV, and only at the timing of the top of each packet, the sync signal temporarily switches from the low (L) level to the high (H) level. The clock signal constantly oscillates in the example shown in the upper diagram in
The valid signal is at the H-level in the sections (valid sections) in which there is a packet, and is at the L-level in the sections (invalid sections) other than the valid sections. As 8-bit parallel transmission is performed, 8-bit data in one packet is transmitted in one cycle of the clock signal when the valid signal is at the H-level. It should be noted that, in
As shown in the upper diagram in
In the example shown in the upper diagram in
In a case where the processing unit 43 does not allow suspension of the clock signal, for example, control is performed to maintain a state in which the clock signal constantly oscillates, as shown in the upper diagram in
In a case where the processing unit 43 allows suspension of the clock signal, the oscillation of the clock signal is suspended when a gap appears, as shown in the lower diagram in
As shown in the lower diagram in
In this manner, the clock signal is suspended in each section in which a gap appears. Thus, power consumption can be reduced.
It should be noted that, in the example shown in the lower diagram in
Even if the valid signal indicates a valid section, the clock signal is suspended, and therefore, the processing unit 43 does not latch data. Because of this, in a case where the clock signal is suspended when a gap appears and data is invalid, the valid signal may be maintained at the H-level indicating a valid section, or may be lowered to the L-level indicating an invalid section.
When a byte gap appears, the clock signal may also be suspended. In a case where the clock signal is suspended when a byte gap appears, the control described above with reference to
The clock signal shown in
The present technology can be applied in any case where the clock signal is either in the rising edge mode or in the falling edge mode. Also, the embodiment described with reference to
Although examples of 8-bit parallel transmission have been described with reference to
<Signals During a Gap in a Packet or Between Packets in the Case of 1-Bit Serial Transmission>
Referring now to
As 1-bit serial transmission is performed, when the valid signal is at the H-level, 1-bit data in one packet is transmitted in one cycle of the clock signal, and 8-bit data is transmitted in eight cycles. The valid signal is at the H-level in the sections (valid sections) in which there is a packet, and is at the L-level in the sections (invalid sections) other than the valid sections. Accordingly, in each section with an in-packet gap or an inter-packet gap, the valid signal is at the L-level indicating an invalid section. Also, in a case where a byte gap appears, the valid signal in the gap section is also at the L-level indicating an invalid section.
In the example shown in the upper diagram in
In a case where the processing unit 43 does not allow suspension of the clock signal, for example, control is performed to maintain a state in which the clock signal constantly oscillates, as shown in the upper diagram in
In a case where the processing unit 43 allows suspension of the clock signal, the oscillation of the clock signal is suspended when a gap appears, as shown in the lower diagram in
As shown in the lower diagram in
In this manner, the clock signal is suspended in each section in which an in-packet gap or an inter-packet gap appears. Thus, power consumption can be reduced.
The clock signal shown in
The present technology can be applied in any case where the clock signal is either in the rising edge mode or in the falling edge mode.
In the cases described with reference to
Referring now to
The valid signal is at the H-level in sections (valid sections) in which there is a packet, and is at the L-level in the sections (invalid sections) other than the valid sections. However, in the examples shown in the upper and lower diagrams in
The case described with reference to
In the example shown in the upper diagram in
As shown in the lower diagram in
When a byte gap appears but the valid signal indicates a valid section, the oscillation of the clock signal is also suspended (the clock signal is lowered).
In this manner, the clock signal is suspended in each section in which an in-packet gap, an inter-packet gap, or a byte gap appears. Thus, power consumption can be reduced.
The clock signal shown in
The present technology can be applied in any case where the clock signal is either in the rising edge mode or in the falling edge mode. Also, the embodiment described with reference to
<Transmission or an Error Signal>
Next, transmission of an error signal is described.
A conventional demodulation processing unit 42 handles TS packets, and each TS packet includes information called a transport error indicator that indicates whether there is an error in the data.
The error information indicated by such a transport error indicator is transferred between the demodulation processing unit 42 and the processing unit 43 via a special-purpose signal line, for example. Referring again to the lower diagram in
In the case of such a configuration, data indicating that an error has occurred is transmitted from the demodulation processing unit 42 to the processing unit 43 via the error signal line.
In a case where TLV packets can be transmitted between the demodulation processing unit 42 and the processing unit 43, information equivalent to the transport error indicator is included in each TLV packet, so that error information can be transmitted from the demodulation processing unit 42 to the processing unit 43.
Referring now again to
Also, as shown in the lower diagram in
In a case where an error indicator is included in each TLV packet as above, the demodulation processing unit 42 can transmit error information indicated by the error indicator (or information indicating that an error has occurred or has not occurred) to the processing unit 43. That is, in a case where TLV packets are handled, error information can also be transmitted.
In a case where an error signal line is provided, the error information can be transmitted from the demodulation processing unit 42 to the processing unit 43 through the error signal line, as in the above described case.
Further, in a case where any error signal line is not provided, or in the case of the configuration shown in the upper diagram in
As shown in
Further, the (BCH ERR1) section and the (BCH ERR2) section are located in a section of a variable-length packet output #1, the (BCH ERR2) section is also located in a section of a variable-length packet output #2, and the (BCH ERR3) section is located in a section of a variable-length packet output #4.
In a case where the error information is output for each error correction code in such circumstances, the error information is output as indicated by the waveform denoted by ERR1 in
In a case where the error information is output for each variable-length packet, the error signal continues to be output (the error signal is maintained at the H-level) first during the section of the variable-length packet output #1, since the (BCH ERR1) section is located in the section of the variable-length packet output #1.
Since the (BCH ERR2) section is located in the section of the variable-length packet output #1 and the section of the variable-length packet output #2, the error signal continues to be output (the error signal is maintained at the H-level) during the section of the variable-length packet output #1 and the section of the variable-length packet output #2.
Since the (BCH ERR3) section is located in the section of the variable-length packet output #4, the error signal continues to be output (the error signal is maintained at the H-level) during the section of the variable-length packet output #4.
As described above, the error information may be output so as to vary with error correction codes, or may be output so as to vary with variable-length packets.
<Processing of NTPs>
Next, processing of NTPs is described. As described above with reference to
The PCR transmitting side transmits PCR data included in an independent packet or a video or audio PES to the receiver side at regular intervals. The PCR contains a 42-bit system time clock (STC) value counted with a 27-MHz clock on the transmitting side.
The receiver side recognizes the location of the PCR data from the description in a PMT, and loads the STC value included in the PCR data into a clock reproduction unit. The clock reproduction unit compares the STC value loaded from the PCR of the TS with a count value counted with a 27-MHz oscillator, and performs control so that the difference becomes 0. As a result, the clock on the transmitting side can be locked with a certain degree of accuracy.
The PCR used in such control is equivalent to NTPs in TLV packets. As described above, NTPs are included in TLV packets at predetermined intervals on the transmitting side (by the transmitter 10), and are transmitted to the receiver 11. Using the NTPs, the receiver 11 needs to reproduce the predetermined intervals, and synchronize with the clock on the transmitting side.
Referring now to
In a case where data is output in the manner described below with reference to
In each of
A TLV stream formed with slots #6 through #10, which forms one of the TLV streams from the broadcast station B, is demodulated by 16APSK, a TLV stream formed with slots #11 through #15 is demodulated by 16APSK, and a TLV stream formed with slots #16 to #20 is demodulated by QPSK. In this manner, TLV streams in one frame may include streams demodulated by different methods in some cases.
Such TLV streams are transmitted from the transmitter 10 to the receiver 11, for example. The receiver 11 decodes the received TLV streams by a decoding method compatible with the demodulation method. Of the decoded TLV streams, TLV streams from the desired broadcast station, which is the broadcast station B in this case, are extracted.
TLV packets are further extracted from the TLV streams. In
Shaded (filled) areas in
Since an in-packet gap is a parity portion or the like, an in-packet gap exists in each slot in the example shown in
The TLV packet #1 is a packet extracted from the slot #6. The TLV packet #2 is a packet extracted from the slot #6, the slot #7, and the slot #8. Since the TLV packet #2 exists over the three slots, two in-packet gaps (between the slot #6 and the slot #7, and between the slot #7 and the slot #8) are formed.
The TLV packet #3 is a packet extracted from the slot #8. The TLV packet #4 is a packet extracted from the slot #8 and the slot #9. Since the TLV packet #4 exists over the two slots, one in-packet gap (between the slot #8 and the slot #9) is formed.
The TLV packet #5 is a packet extracted from the slot #9 and the slot #11. Since the TLV packet #5 exists over the three slots #9 through #11 but the slot #10 is a null packet, an in-packet gap and an inter-packet gap are formed.
The TLV packet #6 is a packet extracted from the slot #11 and the slot #12. Since the TLV packet #6 exists over the two slots, one in-packet gap (between the slot #11 and the slot #12) is formed. The TLV packet #7 is a packet extracted from the slot #12.
The TLV packet #8 is a packet extracted from the slot #12 and the slot #13. Since the TLV packet #8 exists over the two slots, one in-packet gap (between the slot #12 and the slot #13) is formed. The TLV packet #9 is a packet extracted from the slot #13.
The TLV packet #10 is a packet extracted from the slot #13 and the slot #14. Since the TLV packet #10 exists over the two slots, one in-packet gap (between the slot #13 and the slot #14) is formed.
The TLV packet #11 is a packet extracted from the slot #16. The TLV packet #12 is a packet extracted from the slot #16 and the slot #17. Since the TLV packet #12 exists over the two slots, one in-packet gap (between the slot #16 and the slot #17) is formed.
<First Output Pattern of Data>
The lowermost row in
As the sync signal is switched to the H-level at the top of each TLV packet, the sync signal is switched to the H-level at the timings of the respective tops of the TLV packets #1 through #12, as shown in the lowermost row in
The valid signal is switched to the L-level at each point where a gap appears. In accordance with the sync signal and the valid signal, the TLV packets #1 through #12 are sequentially transmitted. The timings of the transmission (transmission sections) are substantially the same as the timings of extraction of the TLV packets (extraction sections).
As data is output when demodulated by the demodulation processing unit 42 in this manner, the demodulation processing unit 42 does not need to perform a process of temporarily storing data, and may not be equipped with a buffer or the like for output operations.
<Second Output Pattern of Data>
Referring now to
In the example case shown in
In the example shown in
It should be noted that, in
As the TLV packets continue to be output during one frame, the valid signal is maintained at the H-level indicating a valid section. Accordingly, the valid signal is basically always at the H-level.
In this manner, the TLV packets extracted from one frame may be transmitted throughout a 1-frame section. In such a case, the demodulation processing unit 42 includes a buffer or the like that temporarily stores the data of one frame. After storing the data of one frame, the demodulation processing unit 42 divides the time equivalent to one frame in accordance with the stored data amount, controls the clock signal, and then transmits the data to the processing unit 43.
Accordingly, the clock signal can be set at a relatively low frequency. As a result, serial transmission or parallel transmission with a small number of bits can be performed, for example, and the number of pins in the processing unit 43 can be reduced.
<Third Output Pattern of Data>
Referring now to
In the example case shown in
In the example shown in
In the sections other than inter-packet gaps, the valid signal is maintained at the H-level indicating a valid section. For example, in the first output pattern described above with reference to
In the third output pattern, in the section in which the TLV packet #2 is output, the valid signal is maintained at the H-level indicating a valid section, as shown in the lowermost row in
In the third output pattern, outputting of data is controlled so that the valid signal is not lowered in the TLV packets.
In the case of the third output pattern, the demodulation processing unit 42 needs to have a buffer or the like that temporarily stores the TLV packets. However, the amount of data to be stored is small, and accordingly, the buffer capacity may be small. Furthermore, as the demodulation processing unit 42 outputs data after temporarily storing the data, control can be performed so that data transmission to the processing unit 43 is performed with a low-frequency clock signal.
As a result, serial transmission or parallel transmission with a small number of bits can be performed, for example, and the number of pins in the processing unit 43 can be reduced.
<Fourth Output Pattern of Data>
Referring now to
In the example case shown in
In the example shown in
Accordingly, in this case, the TLV packets #1 through #5 are smoothed at a constant rate and are then output during the section equivalent to the five slots of the slots #6 through #10.
As for the other sections in the example shown in
It should be noted that five slots are used as a unit in this example, because the modulation method may be changed for each five slots in highly-sophisticated BS, for example. Therefore, an example where five slots form a unit and TLV packets are smoothed at a constant rate is described herein.
In the example shown in
Also, in the example shown in
As the sync signal is also switched to the H-level at the top of each TLV packet in the case of the fourth output pattern, the sync signal is switched to the H-level at the timings of the respective tops of the TLV packets #1 through #12, as shown in the lowermost row in
If neither in-packet gaps nor inter-packet gaps exist, the valid signal is maintained at the H-level indicating a valid section (the state shown in
It should be noted that, although an example case where the clock signal is variable and constantly oscillates has been described above, the fourth output pattern can be formed in the case of some other control operation.
Although not shown in the drawing, control may be performed so that the valid signal is maintained at the H-level indicating a valid section while the clock signal is suspended as necessary. In this manner, the valid signal is prevented from switching to the L-level while TLV packets are being output. In this case, in a section having an in-packet gap therein, for example, the clock signal is suspended, but the valid signal is maintained at the H-level.
Further, for example, there are cases where slots of the broadcast station B are not successively arranged in one frame (120 slots), and a slots of the broadcast station C might be inserted between slots of the broadcast station B. In such a case, the clock signal is suspended in the section corresponding to the slot of the broadcast station C, and the valid signal is maintained at the H-level. Through such control, the valid signal can be controlled not to switch to the L-level while the TLV packets of the broadcast station B are being output.
In the case of the fourth output pattern, the demodulation processing unit 42 needs to include a buffer or the like that temporarily stores TLV packets. However, as the demodulation processing unit 42 outputs data after temporarily storing the data, data transmission to the processing unit 43 can be performed with a low-frequency clock signal.
As a result, serial transmission or parallel transmission with a small number of bits can be performed, for example, and the number of pins in the processing unit 43 can be reduced.
<Fifth Output Pattern of Data>
Referring now to
The frequency of the clock signal in a case where the fifth output pattern is adopted is lower than the frequency of the clock signal in a case where the first output pattern is adopted. The fifth output pattern can be used to lower the frequency of the clock signal, for example.
In the example case shown in
In the example shown in
Likewise, smoothing is performed at a constant rate in the section from the top of the slot #11, from which the TLV packet #5 has been extracted, to the end of the slot #14, from which the TLV packet #10 has been extracted. The TLV packets #5 through #10 extracted from the slots #11 through #14 are then output.
Likewise, smoothing is performed at a constant rate in the section from the top of the slot #16, from which the TLV packet #11 has been extracted, to the end of the slot #17, from which the TLV packet #12 has been extracted. The TLV packets #11 and #12 extracted from the slots #16 and #17 are then output.
As the sync signal is also switched to the H-level at the top of each TLV packet in such a case, the sync signal is switched to the H-level at the timings of the respective tops of the TLV packets #1 through #12, as shown in the lowermost row in
In the fifth output pattern, smoothing is performed in a single slot, and the frequency of the clock signal is fixed. Outputting of data is controlled in this manner.
In such a case, the demodulation processing unit 42 needs to include a buffer or the like that temporarily stores TLV packets. However, as the demodulation processing unit 42 outputs data after temporarily storing the data, data transmission to the processing unit 43 can be performed with a low-frequency clock signal as described above.
As a result, serial transmission or parallel transmission with a small number of bits can be performed, for example, and the number of pins in the processing unit 43 can be reduced.
<Outputting NTP at Regular Intervals>
The first through fifth output patterns have been described above. Referring now to
The first row in
The second row in
As described above with reference to
It should be noted that, for example, in a case where TLV streams of the broadcast station B demodulated by different demodulation methods (16APSK demodulation and QPSK demodulation in the drawings) are included in one frame as in the examples shown in
It should be noted that, in the description below, an NTP is placed in the first slot in each TLV stream. However, each slot in which an NTP is placed may be at a predetermined location in a TLV stream, and the position of an NTP is not necessarily in the first slot in a TLV stream.
Referring back to
The fourth through eighth rows in
As shown in the fourth through eighth rows in
In the first output pattern shown in the fourth row in
An NTP is placed in the first slot in each TLV stream, and therefore, is located at the same point in each frame. Accordingly, in a case where outputting is performed at the timing of decoding as in the first output pattern, an NTP is also output at regular intervals. Thus, in the first output pattern, an NTP can be supplied from the demodulation processing unit 42 to the processing unit 43 at predetermined intervals, and a clock recovery can be achieved in the processing unit 43.
In the second output pattern shown in the fifth row in
In the second output pattern, TLV packets are output throughout a 1-frame section, and an NTP is output at the timing of outputting the first slot in each one frame. Accordingly, an NTP is also output at regular intervals in the second output pattern. Thus, an NTP can be supplied from the demodulation processing unit 42 to the processing unit 43 at the regular intervals, and a clock recovery can be achieved in the processing unit 43.
In the third output pattern shown in the sixth row in
The third output pattern is a pattern in which data is output so that the valid signal is not lowered in the TLV packets. Accordingly, an NTP is also output at regular intervals in the third output pattern. Thus, an NTP can be supplied from the demodulation processing unit 42 to the processing unit 43 at the regular intervals, and a clock recovery can be achieved in the processing unit 43.
It should be noted that, in the third output pattern, the demodulation processing unit 42 temporarily stores TLV packets, and the output timings are controlled so that no in-packet gaps are formed. Thus, the intervals at which an NTP is output can be finely adjusted, and control can be performed so that the intervals become precisely constant intervals. This also applies in the second output pattern.
In the fourth output pattern shown in the seventh row in
The fourth output pattern is an output pattern in which smoothing is performed in slots, and the output rate is variable. When the NTP placed in the first slot in a TLV stream is decoded, the NTP is output from the demodulation processing unit 42 to the processing unit 43. Accordingly, in the fourth output pattern, the intervals at which an NTP is output are also intervals each equivalent to one frame, and are constant intervals. In the fourth output pattern, an NTP can also be supplied from the demodulation processing unit 42 to the processing unit 43 at regular intervals, and thus, a clock recovery can be achieved in the processing unit 43.
In the fifth output pattern shown in the eighth row in
The fifth output pattern is an output pattern in which smoothing is performed in slots, and the output rate is fixed. When the NTP placed in the first slot in a TLV stream is decoded, the NTP is output from the demodulation processing unit 42 to the processing unit 43. Accordingly, in the fifth output pattern, the intervals at which an NTP is output are also intervals each equivalent to one frame, and are constant intervals. In the fifth output pattern, an NTP can also be supplied from the demodulation processing unit 42 to the processing unit 43 at regular intervals, and thus, a clock recovery can be achieved in the processing unit 43.
As described above, in any of the first through fifth output patterns, an NTP can be supplied from the demodulation processing unit 42 to the processing unit 43 at regular intervals, and thus, a clock recovery can be achieved in the processing unit 43.
<Application to Cable Retransmission>
Although example cases where TLV packets are handled have been described in the above embodiments, the present technology can also be applied in cases where packets such as Generic Stream Encapsulation (GSE) packets, GSE-Lite (DVB) packets, and IP packets are handled.
An example case where the above described embodiment is applied to digital cable television broadcasting is now described, and the present technology is further explained.
Satellite broadcasts received by the antenna 101 are supplied to the transmitter 10. The transmitter 10 includes a satellite tuner 121 and a cable retransmission conversion unit 122. The transmitter 10 is a device on the side of a broadcast station that conducts digital cable television broadcasting. The transmitter 10 converts the broadcast waves of a satellite broadcast received by the antenna 101 into broadcast waves of a digital cable television broadcast, and transmits the converted broadcast waves to the side of the receiver 11 via a predetermined cable.
The receiver 11 has a configuration similar to that of the receiver 11 shown in
A satellite broadcast is broadcast as TLV digital broadcast waves as described above, and is received by the antenna 101. The transmitter 10 converts TLV digital broadcast waves into broadcast waves of a digital cable television broadcast, such as partial TLV packets, and then transmits the converted broadcast waves (this method will be referred to as the first conversion method). Alternatively, the transmitter 10 converts TLV digital broadcast waves into GSE packets, and then transmits the GSE packets (this method will be referred to as the second conversion method).
The first conversion method is adopted in a case where cable retransmission compliant with the ISDB-C standards is performed. By the first conversion method, the transmitter 10 performs a process of converting a received TLV packet into partial TLV packets, as shown in
A partial TLV packet is a packet having a fixed length of 188 bytes. Of the 188 bytes, three bytes are the header, and the remaining 185 bytes are the payload. In
In the example shown in
The partial TLV packet 3 is a packet that includes data of the TLV packet 1 and data of the TLV packet 2. In this manner, the payload of a partial TLV packet may include more than one divided TLV packets.
As shown in
The transport error indicator is a flag that indicates the existence/non-existence of a bit error in the partial TLV packet. When the transport error indicator is “1”, for example, there exists at least a 1-bit uncorrectable error in the partial TLV packet.
When the TLV packet start indicator is “1”, the payload of the partial TLV packet includes the top of a TLV packet. For example, the partial TLV packet 2 includes only the TLV packet 1, and does not include the top of the TLV packet 1. Therefore, the TLV packet start indicator of the partial TLV packet 2 is set at “0”. Meanwhile, the partial TLV packet 3 includes the TLV packet 1 and the TLV packet 2, and also includes the top of the TLV packet 2. Therefore, the TLV packet start indicator of the partial TLV packet 3 is set at “1”, for example.
The PID is an area to be used for identifying the data in the payload as TLV data.
The TLV top indicator is the first one byte in the payload, and is used when the TLV packet start indicator is “1”. The value of the TLV top indicator indicates at which byte in the payload the top of a TLV packet is located. With this configuration, the receiving side can detect the location of the top of the TLV packet included in the payload of the partial TLV packet. When the TLV packet start indicator is “0”, the TLV top indicator is not inserted into the payload.
The transmitter 10 converts a TLV packet into partial TLV packets, performs cable modulation on the partial TLV packets, and transmits the partial TLV packets to the side of the receiver 11 via a cable.
The receiver 11 receives the partial TLV packets. The receiver 11 converts the received partial TLV packets into a TLV packet. For example, the original TLV packet is restored from the partial TLV packets by the demodulation processing unit 42. In the case shown in
The TLV packet start indicator of the partial TLV packet 3 is set at “1”, for example, and a TLV top indicator is inserted into the payload. Receiving the partial TLV packet 3, the side of the receiver 11 notices that the TLV packet start indicator of the partial TLV packet 3 is “1”, and recognizes that the top of the TLV packet 2 is located at the byte indicated by the TLV top indicator inserted in the payload. The bytes after the TLV top byte are then regarded as part of the TLV packet 2, and the TLV packet 2 is restored.
In this manner, the demodulation processing unit 42 obtains a TLV packet from partial TLV packets. As a result, the demodulation processing unit 42 outputs a TLV packet to the processing unit 43. The output of a TLV packet from the demodulation processing unit 42 to the processing unit 43 is the same as that in the above described embodiment, and the above described embodiment can be applied to the processing and the like related to the output.
It should be noted that, in a case where cable retransmission compliant with the ISDB-C standards is performed, a Reed-Solomon (RS) code is used in error correction. Therefore, when the above described embodiment is applied, the processing related to the error correction code needs to be replaced with a Reed-Solomon code.
In the error information transmission described above with reference to
Next, a case where broadcast waves for a cable network are converted by the second conversion method is described. The second conversion method is adopted in a case where J.382-compliant cable retransmission is performed.
By the second conversion method, the transmitter 10 performs a process of converting received TLV packets into GSE packets, and further converting the GSE packets into baseband (BB) frames, as shown in
A TLV packet is formed with a packet header (TLV Header) and data (TLV Data), as shown in
In the example shown in
The transmitter 10 further creates a BB frame (Base Band Frame) by placing one or more GSE packets in the data field (BB Frame Data Field) and adding a BB (Base Band) header thereto. The transmitter 10 then transmits the BB frame to the side of the receiver 11 via a predetermined cable. In the examples shown in
Referring now to
The first two bits “01” in the TLV header and the 6-bit reserved area (Reserved) that follows are not necessary in the GSE header after the packet conversion, and therefore, are not used. Meanwhile, a start indicator (S), an end indicator (E), and a label type (LT) need to be placed in the GSE header, and therefore, a predetermined number of bits are placed therein.
Here, bits suitable for the GSE packet are allocated to the start indicator (S) and the end indicator (E), but the bits “10” indicating a broadcast are allocated to the label type (LT), for example.
Also, the packet type (Type) in the TLV header corresponds to the protocol type (Protocol Type) in the GSE header. Although the packet type (Type) in the TLV header involves one byte (B), the protocol type (Protocol Type) in the GSE header involves two bytes (B). Therefore, it is necessary to perform conversion to adjust the sizes. Here, the type conversion table shown in
According to this conversion table, when an IPv4 packet is transmitted, for example, “0x01” allocated as the packet type (Type) in the TLV header is converted into “0x0800”, to correspond to the protocol type (Protocol Type) in the GSE header.
Likewise, in a case where an IPv6 packet is transmitted, the packet type “0x02” is converted into a protocol type “0x86DD”. Also, in a case where a compressed IP packet is transmitted, the packet type “0x03” is converted into a protocol type “0x22F2”. Further, in a case where a transmission control signal packet is transmitted, the packet type “0xFF” is converted into a protocol type “0x0087”. It should be noted that, in the case of a null packet, “0xFF” is allocated as the packet type, but does not need to be retransmitted, because the packet is a null packet. In this case, any specific conversion is not performed. It should be noted that, in a case where a packet type (Type) is added, a value of a protocol type (Protocol Type) for conversion is newly defined.
Referring back to
In the above manner, the TLV header in which “01”, the reversed area (Reserved), the packet type (Type), and the data length (Length) are placed is converted into the GSE header in which the start indicator (S), the end indicator (E), the label type (LT), the GSE length (GSE Length), a frag ID (Frag ID), the total length (Total Length), and the GSE length (GSE Length) are placed. The GSE header is then added to the payload, so that a GSE packet is created. In this manner, a TLV packet is converted into a GSE packet.
A BB frame including one or more such GSE packets is received on the side of the receiver 11. The demodulation processing unit 42 (
In a case where a GSE packet is output from the demodulation processing unit 42 to the processing unit 43, the processing related to the output can be performed basically through the same process as that in a case where a TLV packet is output from the demodulation processing unit 42 to the processing unit 43. Thus, the above described embodiment can be applied.
Alternatively, the demodulation processing unit 42 may not output a GSE packet, but may further convert a GSE packet into a TLV packet and then output the TLV packet to the processing unit 43. The demodulation processing unit 42 extracts (the data in) a GSE packet from a BB frame, converts the extracted GSE packet into a TLV packet, and then outputs the TLV packet to the processing unit 43.
When a GSE packet is converted into a TLV packet, the opposite of the process described above with reference to
As described above with reference to
In this manner, the demodulation processing unit 42 obtains a TLV packet from a GSE packet. As a result, the demodulation processing unit 42 outputs a TLV packet to the processing unit 43. The output of a TLV packet from the demodulation processing unit 42 to the processing unit 43 is the same as that in the above described embodiment, and the above described embodiment can be applied to the processing and the like related to the output.
In the above manner, the present technology can also be applied to digital cable television broadcasting.
<Application to ALP>
The above described present technology can also be applied to Advanced Television Systems Committee (ATSC) methods. In the example case described below, the present technology is applied to an ATSC method.
As shown in
At the top of the ALP header (base header), 3-bit type information (Packet Type) is set. As shown in
Specifically, in a case where an IP packet of IPv4 (IP/UDP packet) is placed in the payload, “000” is set in the type information. Also, in a case where a compressed IP packet (IP/UDP packet) is placed in the payload, “010” is set in the type information.
Further, in a case where a link layer signaling (LLS) packet is placed in the payload, “100” is set in the type information. This LLS packet is a packet for transmitting an LLS signal. The LLS signal includes information indicating the structures of streams and services in a broadcasting network. With this LLS packet, an L2 signal that is a Layer-2 signal can also be transmitted, for example.
Also, in a case where an extension packet (Packet Type Extension) is placed in the payload, “110” is set in the type information. Further, in a case where a TS packet compliant with MPEG2-TS is placed in the payload, “111” is set in the type information.
It should be noted that, in
Referring back to
It should be noted that, in the single packet mode, an ALP packet without an extension header is called a “normal packet”. On the other hand, an ALP packet with an extension header is called a “long packet”.
In a case where “1” is set as the packet setting information (PC), on the other hand, a segmentation mode (Segmentation mode) or a concatenation mode (Concatenation mode) starts in accordance with the 1-bit S/C (Segmentation/Concatenation) placed after the packet setting information, and 11-bit length information (Length) and an extension header (Additional header) are placed in the ALP header.
In addition, in the ALP packet, a payload is placed after the ALP header having the above described structure. In this payload, for example, an IP packet of IPv4 (IP/UDP packet), an LLS packet, or the like can be placed in accordance with the type information in the ALP header (base header).
In a case where an ALP packet having such a structure is processed in the receiver 11 (
However, an ALP packet does not include error information indicating that an error has occurred, when there is an error. Referring now again to
This transport error indicator is a flag that indicates the existence/non-existence of a bit error in the TS packet. When the transport error indicator is “1”, for example, there exists at least a 1-bit uncorrectable error in the TS packet.
On the other hand, the ALP packet shown in
To counter this, an ALP packet is output from the demodulation processing unit 42 to the processing unit 43, and error information is also output. A method for enabling this is now described.
First, a method by which an error indicator (EI) is included in an ALP packet is described as a first method for outputting error information. Referring again to
The 3-bit type information is reduced to 2-bit information, and the remaining one bit is used as the error indicator. In a case where the type information is 2-bit information, four packet types can be defined. However, in the type information described above with reference to
For example, type information is defined as shown in
Also, in a case where an extension packet (Packet Type Extension) is placed in the payload, “10” is set in the type information. Further, in a case where a TS packet compliant with MPEG2-TS (MPEG2 Transport Stream) is placed in the payload, “11” is set in the type information.
Alternatively, type information may be defined as shown in
Also, in a case where an LLS packet (Link layer signaling packet) is placed in the payload, “10” is set in the type information. Further, in a case where an extension packet (Packet Type Extension) is placed in the payload, “11” is set in the type information.
Type information may be defined in accordance with either
An IP packet of IPv4 (IPv4 packet) and a compressed IP packet (Compressed IP packet) each have a high frequency of use, and are considered important, and therefore, these two packet types are not excluded but are left. In addition, an extension packet (Packet Type Extension) is considered as important as an IP packet of IPv4 and a compressed IP packet, and therefore, this packet type is not excluded but is left. The type information shown in
The type information can be designed as information for identifying the four packet types: an IP packet of IPv4, a compressed IP packet, an extension packet, and an LLS packet.
The type information shown in
Also, type information other than the type information shown in
In a case where 2-bit type information is defined as above, an ALP packet has the structure shown in
Like the ALP packet shown in
After the type information, a 1-bit error indicator (EL) is placed. Like the 1-bit transport error indicator in the packet header in the TS packet shown in
As the error indicator is included in the ALP header as described above, error information can be transmitted from the demodulation processing unit 42 to the processing unit 43. Thus, in a case where ALP packets are handled, error information can also be transmitted.
Next, a method by which the existence/non-existence of an error is indicated with a special signal is described as a second method for outputting error information.
Referring to
The clock signal (ALP CLK) is a signal indicating the output timing of the data forming the ALP. The clock signal is a pulse-like signal that repeatedly switches between the L-level and the H-level.
The sync signal (ALP SYNC) indicates the timing of the top of each packet included in the ALP. Only at the timing of the top of each packet, for example, the sync signal temporarily switches from the low (L) level to the high (H) level.
The valid signal (ALP VALID) indicates the sections (valid sections) in which a packet exists in the ALP. For example, the valid signal is at the H-level in the valid sections, and is at the L-level in the sections (invalid sections) other than the valid sections.
The data signal (ALP DATA) is an ALP signal, and includes all or part of an ALP packet. A packet has a data length (packet length) of three to 65539 bytes, for example.
As shown in the portion enclosed with a frame X in
That is, as shown in the portion enclosed with the frame Y in
For example, in a case where the valid signal rises at the same time as the sync signal as described above, the processing unit 43 (
In this manner, error information may be transmitted with the use of a special signal.
In a case where error information is transmitted with the use of a special signal, the error information can also be transmitted from the demodulation processing unit 42 to the processing unit 43. Thus, in a case where ALP packets are handled, error information can also be transmitted.
Further, in a case where an ALP packet is demodulated by the demodulation processing unit 42 and is then output to the processing unit 43, the processing related to the output can be performed basically through the same process as that in a case where a TLV packet is output from the demodulation processing unit 42 to the processing unit 43. Thus, the above described embodiment can be applied.
<Description of a Computer to which the Present Technology is Applied>
Meanwhile, the above described series of processes may be performed by hardware or may be performed by software. In a case where the series of processes are performed by software, the program that forms the software may be installed in a computer incorporated into special-purpose hardware, or may be installed from a recording medium into a general-purpose personal computer or the like, for example, that can execute various kinds of functions by installing various kinds of programs.
An input unit 1006, an output unit 1007, a storage unit 1008, and a communication unit 1009 are connected to the input/output interface 1005: the input unit 1006 is formed with an input device such as a keyboard or a mouse through which a user inputs an operation command; the output unit 1007 outputs an image of a process operating screen or a processing result to a display device; the storage unit 1008 is formed with a hard disk drive or the like that stores programs and various kinds of data; and the communication unit 1009 is formed with a local area network (LAN) adapter or the like, and performs a communication process via a network that is typically the Internet. A drive 1010 is also connected to the input/output interface 1005. The drive 1010 performs data reading and writing on a removable medium 1011, such as a magnetic disk (such as a flexible disk), an optical disk (such a Compact Disc-Read-Only Memory (CD-ROM) or a Digital Versatile Disc (DVD)), a magnetooptical disk (such as Mini Disc (MD)), or a semiconductor memory.
A program stored in the ROM 1002 or in the removable medium 1011 such as a magnetic disk, an optical disk, a magnetooptical disk, or a semiconductor memory is read and installed into the storage unit 1008. In accordance with the program loaded from the storage unit 1008 into the RAM 1003, the CPU 1001 performs various kinds of processes. The RAM 1003 also stores data and the like necessary for the CPU 1001 to perform various processes as appropriate.
In the computer having the above described configuration, the CPU 1001 loads a program stored in the storage unit 1008 into the RAM 1003 via the input/output interface 1005 and the bus 1004, for example, and executes the program, so that the above described series of processes are performed.
The program to be executed by the computer (the CPU 1001) may be recorded on the removable medium 1011 as a package medium to be provided, for example. Alternatively, the program can be provided via a wired or wireless transmission medium, such as a local area network, the Internet, or digital satellite broadcasting.
In the computer, the program can be installed into the storage unit 1008 via the input/output interface 1005 when the removable medium 1011 is mounted on the drive 1010. Also, the program may be received by the communication unit 1009 via a wired or wireless transmission medium, and be installed into the storage unit 1008. Alternatively, the program may be installed beforehand into the ROM 1002 or the storage unit 1008.
In this specification, the processes to be performed by the computer in accordance with the program are not necessarily performed in chronological order compliant with the sequences shown in the flowcharts. That is, the processes to be performed by the computer in accordance with the program include processes to be performed in parallel or independently of one another (such as parallel processes or object-based processes).
In addition, the program may be executed by one computer (processor), or may be executed in a distributive manner by more than one computer. Further, the program may be transferred to a remote computer, and be executed therein.
Furthermore, in this specification, a system means an assembly of components (devices, modules (parts), and the like), and not all the components need to be provided in the same housing. In view of this, devices that are housed in different housings and are connected to one another via a network form a system, and one device having modules housed in one housing is also a system.
It should be noted that embodiments of the present technology are not limited to the above described embodiments, and various modifications may be made to them without departing from the scope of the present technology.
For example, the present technology can be embodied in a cloud computing configuration in which one function is shared among devices via a network, and processing is performed by the devices cooperating with one another.
Also, the respective steps described with reference to the above described flowcharts can be carried out by one device or can be shared among devices.
Further, in a case where more than one process is included in one step, the processes included in the step can be performed by one device or can be shared among devices.
It should be noted that the present technology may also be embodied in the configurations described below.
(1)
A signal processing device including:
a demodulation processing unit that performs a demodulation process;
a processing unit that performs a demux process; and
a data signal line, a clock signal line, a sync signal line, and a valid signal line that are provided between the demodulation processing unit and the processing unit,
in which a variable-length packet is transmitted between the demodulation processing unit and the processing unit through the data signal line, the clock signal line, the sync signal line, and the valid signal line.
(2)
The signal processing device of (1), in which the variable-length packet is an Internet Protocol (IP) packet.
(3)
The signal processing device of (1), in which the variable-length packet is a Type Length Value (TLV) packet.
(4)
The signal processing device of any of (1) to (3), in which the variable-length packet to be transmitted from the demodulation processing unit to the processing unit via the data signal line is at least part of a TLV packet.
(5)
The signal processing device of (1), in which the variable-length packet is one of a TLV packet, a GSE packet, a GSE-Lite packet, an ALP packet, and an IP packet.
(6)
The signal processing device of any of (1) to (5), in which the data signal line is formed with one to eight data signal lines, and serial transmission or parallel transmission is performed in accordance with the number of provided data signal lines.
(7)
The signal processing device of any of (1) to (6), in which transmission of the variable-length packet is performed with an optional bit width of one to eight bits.
(8)
The signal processing device of any of (1) to (7), in which the clock signal line transmits a clock signal, the sync signal line transmits a sync signal indicating a position of a top of a packet, and the valid signal line transmits a valid signal indicating a data valid section.
(9)
The signal processing device of (8), in which the processing unit latches data from the demodulation processing unit at one of a rising edge and a falling edge of the clock signal.
(10)
The signal processing device of (8) or (9), in which
the valid signal is a signal constantly indicating that data is valid, and
the clock signal is set at a frequency corresponding to the bit width of the data signal line.
(11)
The signal processing device of (8) or (9), in which
the valid signal is a signal constantly indicating that data is valid, and
oscillation of the clock signal is suspended during a byte gap.
(12)
The signal processing device of (8) or (9), in which
the clock signal constantly oscillates at a predetermined frequency, and
the valid signal is lowered during a byte gap.
(13)
The signal processing device of any of (8) to (12), in which, during one of an in-packet gap and an inter-packet gap, oscillation of the clock signal is suspended.
(14)
The signal processing device of any of (1) to (13), in which the variable-length packet is a TLV packet, and error information indicating whether there is an error in a packet is included in a packet header area of the TLV packet.
(15)
The signal processing device of any of (1) to (13), in which the variable-length packet is a TLV packet, and error information indicating whether there is an error in a packet is included in an area in which information about the type of a packet included in the TLV packet is written.
(16)
The signal processing device of (14) or (15), further including an error signal line that transmits the error information.
(17)
The signal processing device of any of (14) to (16), in which the error information is transmitted for each error correction code, or is transmitted for each variable-length packet.
(18)
The signal processing device of any of (1) to (17), in which the demodulation processing unit converts a partial TLV packet compliant to ISDB-C standards into a TLV packet, and transmits the TLV packet to the processing unit.
(19)
The signal processing device of any of (1) to (17), in which the demodulation processing unit transmits a J.382-compliant GSE packet to the processing unit.
(20)
The signal processing device of any of (1) to (17), in which the demodulation processing unit converts a J.382-compliant GSE packet into a TLV packet, and transmits the TLV packet to the processing unit.
(21)
The signal processing device of any of (1) to (17), in which the demodulation processing unit transmits an ATSC-compliant ALP packet to the processing unit.
(22)
The signal processing device of (21), in which a header of the ALP packet includes at least 2-bit type information as information indicating a type of data placed in a payload, and 1-bit error information indicating whether there is an error in a packet.
(23)
The signal processing device of (22), in which the type information is information for identifying four packet types among the following five packet types: an IP packet of IPv4, a compressed IP packet, an LLS packet, an extension packet, and a TS packet compliant with MPEG2-TS.
(24)
The signal processing device of (21), in which, in a case where there is an error in a packet, a sync signal to be transmitted by the sync signal line and a valid signal to be transmitted by the valid signal line do not simultaneously rise.
(25)
A signal processing method implemented in a signal processing device that includes:
a demodulation processing unit that performs a demodulation process;
a processing unit that performs a demux process; and
a data signal line, a clock signal line, a sync signal line, and a valid signal line that are provided between the demodulation processing unit and the processing unit,
the signal processing method including
a step of transmitting a variable-length packet between the demodulation processing unit and the processing unit, using the data signal line, the clock signal line, the sync signal line, and the valid signal line.
(26)
A computer-readable program for causing a computer to perform a process,
the computer including:
a demodulation processing unit that performs a demodulation process;
a processing unit that performs a demux process; and
a data signal line, a clock signal line, a sync signal line, and a valid signal line that are provided between the demodulation processing unit and the processing unit, the process including
a step of transmitting a variable-length packet between the demodulation processing unit and the processing unit, using the data signal line, the clock signal line, the sync signal line, and the valid signal line.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-118755 | Jun 2015 | JP | national |
| 2016-002797 | Jan 2016 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/065861 | 5/30/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2016/199603 | 12/15/2016 | WO | A |
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| Number | Date | Country | |
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| 20180139033 A1 | May 2018 | US |
