This application claims priority to Taiwan Application Serial Number 105119586, filed Jun. 22, 2016, which is herein incorporated by reference.
Audio processing devices are widely used in various electronic devices. In some related arts, in the audio processing device, an acoustic echo cancellation (AEC) mechanism is typically configured to process signals prior to a beamforming mechanism.
With such arrangements, in general, the number of circuits in the AEC mechanism will be proportional to the number of microphone. When the number of circuits of the AEC mechanism is too large, overall computation and complexity of the audio processing device are too high. As a result, it is less suitable to be applied in electronic products with low computational capability, e.g., mobile devices.
In some embodiments, a device is disclosed that includes an acoustic echo cancellation (AEC) circuit, a blocking matrix circuit, a first controller, a subtractor and a filter. The AEC circuit is configured to perform an AEC process based on a far-end signal and a first input signal, to generate a first processed signal. The blocking matrix circuit is configured to suppress a target signal component of the first input signal and a second input signal, to generate a reference signal. The first controller is configured to generate a first control coefficient based on the first processed signal and the second input signal. The subtractor is configured to generate a first output signal based on the first processed signal and a filtered signal. The filter is configured to generate the filtered signal in response to the first control coefficient, the reference signal and the first output signal.
In some embodiments, a device that includes an acoustic echo cancellation (AEC) circuit, a first frequency converter circuit, a second frequency converter circuit, a blocking matrix circuit, a first controller, a subtractor and a filter. The AEC circuit is configured to perform an acoustic echo cancellation process based on a far-end signal and a first input signal, to generate a first processed signal. The first frequency converter circuit is configured to generate the first input frequency domain signal corresponding to the first input signal. The second frequency converter circuit is configured to generate the second input frequency domain signal corresponding to the second input signals. The blocking matrix circuit is configured to generate reference signals based on the first input frequency domain signal and the second input frequency domain signals. The first controller is configured to generate a first control coefficient based on the first processed signal and the second input signal. The subtractor is configured to generate a first output signal based on the first processed signal and a filtered signal. The filter is configured to generate the filtered signal in response to the first control coefficient, the reference signal and the first output signal.
In some embodiments, a method that includes the steps outlined below. An AEC process is performed based on a far-end signal and a first input signal to generate a first processed signal. A target signal component of the first input signal and second input signals are suppressed to generate reference signals. A first control coefficient is generated based on the first processed signal and the second input signals. A first output signal is generated based on the first processed signal and a filtered signal. The filtered signal is generated in response to the first control coefficient, the reference signals and the first output signal.
This disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
The terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another.
In addition, as used herein, the terms “coupled,” “connected” may refer to two or more elements are in direct physical or electrical contact as, or as an entity or indirect mutual electrical contact, and can also refer to two or more elements or acts interoperability.
Reference is now made to
The AEC circuit 110 is configured to perform an AEC process based on the input signal S1 and a far-end signal SFA, to generate a processed signal SAEC. As illustratively shown in
The blocking matrix circuit 120 is coupled to the microphones 101A-101M to receive the corresponding input signals S1-SM. The blocking matrix circuit 120 is configured to suppress target signal components of the input signals S1-SM to generate reference signals SREF. In some embodiments, the target signal components are major power signals that are expected to be received by the microphones 101A-101M, for example, the speaker's voice. In some embodiments, the blocking matrix circuit 120 can be implemented by M adaptive filters. In some embodiments, the blocking matrix circuit 120 generates M−1 reference signals. For example, when M is 2, the blocking matrix circuit 120 can subtract one of the input signals S1 and S2 from another one of the input signals S1 and S2 to obtain the reference signal SREF.
The implementations of the blocking matrix circuit 120 illustrated above are given for illustrative purposes. Various implementations to implement the above functions of the blocking matrix circuit 120 are within the contemplated scope of the present disclosure.
In some embodiments, the audio processing device 100 further includes a delay time circuit 125. The delay time circuit 125 is coupled to the microphones 101B-101M, and is configured to delay the input signals S2-SM for a predetermined time to generate delayed input signals SD2-SDM. In some embodiments, the predetermined time mentioned above is corresponding to the operating time of the AEC circuit 110. With such arrangements, the delayed input signals SD2-SDM can be synchronized with the processed signal SAEC.
The controller 130 is configured to generate control coefficient C1 based on the processed signal SAEC and the input signals S2-SM. In some embodiments, the controller 130 is configured to estimate a direction corresponding to the target signal components based on the processed signal SAEC and one of the delayed input signals SD2-SDM.
For example, the controller 130 can employ a direction of arrival (DOA) estimation to estimate the direction. In some embodiments, the controller 130 can perform a generalized cross correlation (GCC) calculation on the processed signal SAEC and one of the delayed input signals SD2-SDM, in order to estimate the direction of the target signal components and to generate control coefficient C1 accordingly. For example, in some embodiments, the above described operating method of control coefficient C1 can be expressed as follows:
where, THL is a predetermined low threshold, THH is a predetermined high threshold, τ′ denotes a delay sample, which can be used to calculate the direction, of the target signal components, and GCC denotes the generalized cross correlation (GCC) calculation, which is shown to delay the input signal SD2 as an example.
The above arrangements of the controller 130 are given for illustrative purpose. Various types of the controller 130 are within the contemplated scope of the present disclosure.
The subtractor 140 is coupled to the AEC circuit 110 and the filter 150, to receive the processed signal SAEC and a filtered signal SF respectively. The subtractor 140 is configured to subtract the filtered signal SF from the processed signal SAEC, to generate an output signal SO1.
The filter 150 is coupled to the controller 130, the blocking matrix circuit 120 and the subtractor 140, to receive the control coefficient C1, the reference signal SREF and the output signal SO1 respectively. The filter 150 is configured to generate the filtered signal SF in response to the control coefficient C1, the reference signal SREF and the output signal SO1. In some embodiments, the filter 150 can be implemented by an adaptive filter, and can control whether to adjust weighting coefficients of taps within the filter 150 in accordance with the control coefficient C1. In some embodiments, the filter 150 is configured to output the filtered signal SF based on the control coefficient C1, one or more reference signals SREF and the output signal SO1, in order to reduce the interference components of the output signal 501.
With such arrangements, the signal processing device 100 can reduce the echo and the interference components of the output signal SO1 only under the operation of the single AEC circuit 110. As a result, compared to the related art discussed above, the amount of the computation and the complexity of the signal processing device 100 can be reduced obviously.
The signal processing device 100 in
Compared to the signal processing device 100 in
In this example, the blocking matrix circuit 120 is further configured to generate reference signals FREF based on the input frequency domain signals F1-FM. The frequency converter circuit 202 is coupled to the AEC circuit 110 to receive the processed signal SAEC. The frequency converter circuit 202 is configured to generate a corresponding processed frequency signal FAEC based on the processed signal SAEC. In this example, the subtractor 140 is further configured to subtract a filtered signal FF from the processed frequency signal FAEC to generate the output signal SO1.
The inverse frequency converter circuit 203 is coupled to the subtractor 140 to receive the output signal SO1. The inverse frequency converter circuit 203 is configured to generate a corresponding output signal SO2 in response to the output signal SO1. In this example, the output signal SO1 is in the frequency domain. In some embodiments, the inverse frequency converter circuit 203 is configured to convert the output signal SO1 in the frequency domain to the corresponding output signal SO2 in the time domain. In some embodiments, the inverse frequency converter circuit 203 is configured to perform an inverse fast Fourier transform on the output signal SO1 to generate the output signal SO02. The arrangements of the inverse frequency conversion are given for illustrative purposes. Various arrangements of the inverse frequency conversion are within the contemplated scope of the present disclosure.
Reference is now made to
Compared to the signal processing device 200 in
where K=1−M and M is the length of the subband, TH1K and TH2 are the predetermined thresholds, and SERK is the ratio of a first value and a second value. In some embodiments, the first value is a smoothed amplitude corresponding to the Kth subband of the processed frequency signal FAEC, and the second value is the smoothed amplitude corresponding to the Kth subband of the processed frequency signal FEC; SERSPEECH is the ratio of a third value and a fourth value, in which the third value is a summation of the smoothed amplitudes corresponding to the subbands of a predetermined bandwidth of the processed frequency signal FAEC, and the fourth value is the summation of the smoothed amplitudes corresponding to the subbands of a predetermined bandwidth of the processed frequency signal FEC. In some embodiments, the predetermined bandwidth is a voice frequency band, e.g., approximately 500-3000 Hz.
In some embodiments, the filter 150 is further configured to generate the filtered signal FF in response to the control coefficient C1, the control coefficient C2, the reference signals FREF and the output signal SO1. For example, in the embodiments in
The above arrangements of the controller 320 are given for illustrative purpose. Various types of the controller 320 are within the contemplated scope of the present disclosure. In some other embodiments, the frequency converter circuit 301 and the controller 320 may be built in the AEC circuit 110. In some embodiments, the predicted acoustic echo signal SEC may also be replaced with various kinds of computational information generated by the AEC circuit 110.
In operation S410, the AEC process is performed on the input signal S1 and the far-end signal SFA to generate the processed signal SAEC. For illustration, as shown in
In operation S420, the target signal components of the input signals S1-SM are suppressed to generate one or more reference signals SREF. For illustration, as shown in
In operation 8430, the control coefficient C1 is generated based on the processed signal SAEC and one of the input signals S1-SM. For illustration, as shown in
In operation 8440, the output signal SO1 is generated based on the processed signal SAEC and the filtered signal SF.
In operation 8450, the filtered signal SF is generated in response to the control coefficient C1, one or more reference signals SREF and the output signal SO1. For illustration, as shown in
The operations of the signal processing method 400 are given for illustrative purposes and are not necessarily performed in the order shown. Alternatively stated, operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure.
In summary, the signal processing device and the signal processing method are able to reduce the echo and the interference components of the output signal with operations of a single AEC circuit. As a result, the amount of the computation and the complexity of the signal processing device can be reduced efficiently.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Number | Date | Country | Kind |
---|---|---|---|
105119586 | Jun 2016 | TW | national |