SIGNAL PROCESSING METHOD AND DEVICE

Abstract

Periodically sampled digital data (e.g., digital audio data) are once stored in a work RAM and are then subjected to signal processing such as arithmetic operations using coefficients. A primary accumulator register stores results of arithmetic operations. A secondary accumulator register is specialized in handling a relatively high processing load (e.g., down-sampling) having a plurality of steps, which are distributed and appropriately assigned to a plurality of periods in response to output timings. In order to execute other processing in each period, intermediate results of arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register. The number of steps assigned to each period is appropriately changed in response to interruption of the other processing, whereas the relatively high processing load is given a first priority in comparison with the other processing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, aspects, and embodiments of the present invention will be described in more detail with reference to the following drawings, in which:

FIG. 1 is a block diagram showing the constitution of a portable telephone having signal processing functions in accordance with a preferred embodiment of the present invention;

FIG. 2 is a block diagram showing an internal constitution of a digital signal processor included in the portable telephone shown in FIG. 1;

FIG. 3 is a time-related flow chart showing operations of the digital signal processor shown in FIG. 2;

FIG. 4 is a block diagram showing the constitution of a conventionally-known digital signal processor; and

FIG. 5 is a time-related flow chart showing operations of the digital signal processor shown in FIG. 4.

Claims

1. A signal processing method for processing digital data, which are produced by way of periodical sampling in units of periods, comprising the steps of: distributing a plurality of steps having a relatively high processing load to a plurality of periods in response to output timings;performing signal processing on the plurality of steps in the plurality of periods; andtemporarily storing intermediate results of the signal processing in an accumulator register, which is specialized in the relatively high processing load.

2. A signal processing method according to claim 1, wherein a number of the steps assigned to each of the periods is changed in response to interruption of other processing, which is performed non-periodically.

3. A signal processing method according to claim 1, wherein a minimum number of the steps is assigned to each of the periods.

4. A signal processing method according to claim 1, wherein the relatively high processing load is given a priority and is performed in a last period within the plurality of periods irrespective of interruption.

5. A signal processing method according to claim 1, wherein the digital data correspond to digital audio data, and the relatively high processing load corresponds to down-sampling for reducing a sampling frequency.

6. A signal processing device for performing signal processing on digital data, which are produced by way of periodical sampling, said signal processing device comprising: a storage section for temporarily storing the digital data input thereto;a coefficient storage section for storing a plurality of coefficients for use in the signal processing;an arithmetic operation section for performing arithmetic operations by use of the digital data read from the storage section and the coefficients read from the coefficient storage section;a primary accumulator register for storing results of the arithmetic operations;a control section for producing instructions for the arithmetic operations, addresses for read/write operations of the digital data, and control signals; anda secondary accumulator register, which is specialized in a relatively high processing load having a plurality of steps,wherein the control section distributes the plurality of steps to a plurality of periods in response to output timings, so that intermediate results of the arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register.

7. A signal processing device according to claim 6, wherein a number of the steps assigned to each of the periods is changed in response to interruption of other processing, which is performed non-periodically.

8. A signal processing device according to claim 6, wherein a minimum number of the steps is assigned to each of the periods.

9. A signal processing device according to claim 6, wherein the relatively high processing load is given a priority and is performed in a last period within the plurality of periods irrespective of interruption.

10. A signal processing device according to claim 6, wherein the digital data correspond to digital audio data, and the relatively high processing load corresponds to down-sampling for reducing a sampling frequency.