Patent Application
20180269881
The present application is based on, and claims priority form, Taiwan Patent Application No. 106108231 filed Mar. 14, 2017 the disclosure of which is hereby incorporated by reference herein in its entirety.
The technical field generally relates to a signal processing system and method, and in particular, to a signal processing system and method, applicable to an environment of temperature compensation processing for LC-tank oscillator resonance frequency (OSC), by using temperature sensor/analog-digital-converter (ADC), temperature compensation processing module, fractional-N frequency divider, linear phase-locked loops (LPLL), and frequency-locked loops (FLL) to find the K, M and N values required by the fractional-N frequency divider for the fractional-N frequency divider to output precise clock signals.
In the development of electronic products, due to the rapid evolution of semiconductor process technology, there have been powerful, complex large-scale integrated circuits. Some electronic products, such as mobile phones, tablet PCs, USB peripheral products, require single-chip applications; moreover, in the complex large-scale integrated circuit, but the accurately synchronized clock signals are needed to achieve high-specification processing efficiency. Therefore, the clock generator, that is, the phase-locked loop (PLL), is widely used in the frequency synthesizer, clock and data recovery circuit, and so on.
For the known non-quartz crystal oscillator, the common structures for voltage-controlled oscillator (VCO) can be divided into two types: one is the inductor capacitor tank (LC-tank) oscillator, and the other is the ring oscillator. For CMOS manufacturing process, the phase noise of the ring oscillator is still unable to meet the requirements of the VCO specification for the communication, and therefore the VCO is often designed as an LC-tank oscillator.
For high-speed input/output (I/O) interfaces and wireless communication systems, the low-cost, high-efficiency clock generators are required to use LC-tank oscillator to reduce phase noise to meet high-quality communication specification.
In an article in IEEE Journal of Solid-State Circuits, March 2007, “A monolithic and self-referenced RF LC clock generator compliant with USB 2.0”, the author, Michael S McCorquodale, disclosed how to solve the problem of frequency change from the PLL caused by XTAL due to environmental change, such as, temperature. The solution is to add a phase interpolation circuit before feeding back to the frequency divider in the PLL to shift phase to achieve adjusting the PLL output frequency at different temperatures.
Taiwan Patent No. 1558095 titled “clock generation circuit and method” disclosed a clock generation circuit and a clock generation method to generate a clock. The clock generating circuit comprises: a reference clock generating circuit disposed in a chip for independently generating a reference clock; a temperature sensor for sensing ambient temperature to generate a temperature information; a temperature compensation module coupled to the temperature sensor for generating a temperature compensation coefficient based on the temperature information; and a clock adjusting circuit coupled to the reference clock generating circuit for generating the clock, based on the reference clock and the temperature compensation coefficient; wherein the temperature compensation module dynamically generates the temperature compensation coefficient so that the frequency of the clock approaches a target frequency and does not substantially vary with temperature. However, the temperature compensation module of the “Clock Generation Circuit and Method” of Taiwan Patent No. 1558095 generates the temperature compensation coefficient corresponding to each temperature based on the reference value and the slope, and the temperature compensation coefficient is obtained by interpolation of a value N.F for a certain temperature, in order to deduce backward to obtain the temperature compensation coefficient.
Taiwan Patent No. 1485986 “Clock signal synthesis method and apparatus” disclosed a method and apparatus of adjusting the frequency of the output clock signal to the required accuracy of the oscillation frequency. An embodiment of the method comprises the steps of: entering a calibration mode; generating a first control character to control the timing of a clock signal synthesizer; adjusting the first control character until the timing of the synthesizer is substantially within a preset range of a reference clock timing; sensing a temperature by using a temperature sensor; storing the output preset value of the first control character to a nonvolatile memory; exiting the calibration mode; using the temperature sensor to sense the temperature; and generating a second control character based on the output of the nonvolatile memory and the output of the temperature sensor to control the timing of the clock signal synthesizer. However, Taiwan Patent No. 1485986 “Clock signal synthesis method and apparatus” uses a single-point calibration and temperature compensation mechanism to maintain the frequency of the clock signal to within the accuracy range of the specified frequency under the influence of process, voltage and temperature fluctuation.
Taiwan Publication No. 201543803 “Clock generation circuit and method” disclosed a clock generation circuit and a clock generation method to generate a clock. The clock generating circuit comprises: a reference clock generating circuit disposed in a chip for independently generating a reference clock; a temperature sensor for sensing ambient temperature to generate a temperature information; a temperature compensation module coupled to the temperature sensor for generating a temperature compensation coefficient based on the temperature information; and a clock adjusting circuit coupled to the reference clock generating circuit for generating the clock, based on the reference clock and the temperature compensation coefficient; wherein the temperature compensation module dynamically generates the temperature compensation coefficient so that the frequency of the clock approaches a target frequency and does not substantially vary with temperature. However, the temperature compensation module of the “Clock Generation Circuit and Method” of Taiwan Publication No. 201543803 generates the temperature compensation coefficient corresponding to each temperature based on the reference value and the slope, and the temperature compensation coefficient is obtained by interpolation of a value N.F for a certain temperature, in order to deduce backward to obtain the temperature compensation coefficient.
Therefore, the issues need to be addressed include how to adjust phase by using digital PLL to find frequency division and the relation between the temperature and the phase, instead of adjusting the phase of the VOC of the analog PLL without using XTAL, phase interpolation circuit, and single-point calibration.
An object of the present invention is to provide a signal processing system and method, applicable to an environment of the temperature compensation processing of the resonant frequency (OSC) of the LC-tank oscillator, by using temperature sensor/analog ADC to obtain the different K values associated with the different temperatures, and recording the K-values in the one-time programmable read-only-memory (OTPROM) in the temperature-compensation processing module; the fractional-N frequency divider dividing the higher frequency OSC outputted by the LC-tank oscillator; using LPLL to suppress the clock jitter in the clock outputted by the fractional-N frequency divider, the FLL finding the M-value and N-value required by the fractional-N frequency divider according to the clock processed by the LPLL for jitters, the frequency of an external clock signal applied externally, and passing the M-value and N-value to the temperature compensation processing module, and the temperature compensation processing module transmitting the K-value, M-value, and N-value to the fractional-N frequency divider so that the fractional-N frequency divider can output accurate clock signals.
Another object of the present invention is to provide a signal processing system and method, applicable to an environment of the temperature compensation processing of the resonant frequency (OSC) of the LC-tank oscillator, to use smaller chip area to achieve self-calibration of the frequency drift in the LC clock generator caused by temperature without using open loop temperature compensation circuit and binary-weighted capacitor array.
Yet another object of the present invention is to provide a signal processing system and method, applicable to an environment of the temperature compensation processing of the resonant frequency (OSC) of the LC-tank oscillator, without using XTAL, phase interpolation circuit, and single-point calibration so that the fraction-N frequency divider being able to output accurate clock signals.
Yet another object of the present invention is to provide a signal processing system and method, applicable to an environment of the temperature compensation processing of the resonant frequency (OSC) of the LC-tank oscillator, instead of adjusting the phase of the VCO in the analog PLL, but to use digital PLL to find frequency division, and the relation between the temperature and the phase to adjust the phase so that the fraction-N frequency divider being able to output accurate clock signals.
Yet another object of the present invention is to provide a signal processing system and method, applicable to an environment of the temperature compensation processing of the resonant frequency (OSC) of the LC-tank oscillator, using the physical quantity of the temperature linear changes and the linear change of the OSC frequency with the temperature change, and using two points to determine a straight line without any restriction on the temperature range, and then using fractional-N frequency division to divide the OSC frequency to the required output frequency; in other words, using two or more temperatures of non-specific values to calibrate the frequency division so that the divided frequency is a required frequency.
To achieve the aforementioned objects, the present invention provides a signal processing system, comprising: a temperature sensor/ADC, a temperature compensation processing module, a fractional-N frequency divider, a linear phase-locked loop (LPLL), and a frequency-locked loop (FLL); wherein the temperature compensation processing module comprising a temperature compensation processor, and a memory.
The temperature sensor/ADC: the temperature sensor obtains a current temperature and converts to a voltage, the ADC converts to a code character to control the K-value of the fractional-N frequency divider, with a different K-value for each different temperature.
The temperature compensation processing module: the temperature compensation processing module comprises a temperature compensation processor, and a memory, wherein the memory has a one-time programmable read only memory (OTPROM), and a lookup table; the OTPOM records two or more K values at different temperatures, for example, two K values are recorded for two point calibration, three K values are recorded for three point calibration; the temperature compensation processor uses two or more K values in the OTPROM, the lookup table, and the M value and N value from the FLL to obtain a frequency offset ratio estimation, and the frequency offset ratio estimation is sent to the fractional-N frequency divider so that the fractional-N frequency divider can output an accurate clock signal.
The fractional-N frequency divider: the fractional-N frequency divider receives higher OSC frequency outputted from the LC-tank oscillator, such as frame clock output (FCO) and generates a clock signal FOUT, and transmits the clock signal FOUTS to the LPLL.
Moreover, after the fractional-N frequency divider receives the frequency offset ratio estimation, the fractional-N frequency divider divides the higher OSC frequency outputted from the LC-tank oscillator, such as frame clock output (FCO) downwards so that the fractional-N frequency divider can output an accurate clock signal.
The LPLL: because the clock of the clock signal FOUT outputted from the fractional-N frequency divider has a larger jitter, the clock of the clock signal FOUT outputted from the fractional-N frequency divider uses the LPLL to suppress the clock jitter of the clock signal FOUT outputted from the fractional-N frequency divider.
The FLL: The LPLL transmits the clock of the clock signal FOUT after the jitter processing to the FLL, the FLL finds the M-value and the N-value required by the fractional-N frequency divider according to the clock of the clock signal FOUT after the jitter processing, the frequency of an external clock signal applied externally, such as, 24 MHz or 48 MHz, and then transmits the M-value and the N-value to the temperature compensation processing module, and the temperature compensation processor of the temperature compensation processing module uses two or more K values in the OTPROM, the lookup table, and the M-value and the N-value from the FLL to obtain a frequency shift ratio estimation and transmits the frequency shift ratio estimation to the fractional-N frequency divider so that the fractional-N frequency divider can output an accurate clock signal.
When using the signal processing system to perform signal processing method, the first step is to perform temperature measurement: the temperature sensor obtaining a current temperature and converting to a voltage, the ADC converting to a code character to control the K-value of the fractional-N frequency divider, with a different K-value for each different temperature; the OTPOM recording two or more K values at different temperatures, for example, two K values recorded for two point calibration, three K values recorded for three point calibration.
Then, the next step is to perform frequency shift ration estimation: the temperature compensation processing module using two or more K values in the OTPROM, the lookup table, and the M-value and the N-value from the FLL to obtain a frequency shift ratio estimation and transmitting the frequency shift ratio estimation to the fractional-N frequency divider.
Then, the next step is to perform accurate clock signal outputting: based on the received frequency shift ratio estimation, the fractional-N frequency divider being able to output an accurate clock signal.
Wherein, the detailed process for performing frequency shift ration estimation comprises: first, performing clock signal FOUT generation process: the fractional-N frequency divider receiving higher OSC frequency outputted from the LC-tank oscillator, such as, frame clock output (FCO) and generates a clock signal FOUT, and transmits the clock signal FOUTS to the LPLL; then, performing clock jitter processing process: because the clock of the clock signal FOUT outputted from the fractional-N frequency divider having a larger jitter, the clock of the clock signal FOUT outputted from the fractional-N frequency divider using the LPLL to suppress the clock jitter of the clock signal FOUT outputted from the fractional-N frequency divider; then, the LPLL transmitting the clock of the clock signal FOUT after the jitter processing to the FLL, the FLL finding the M-value and the N-value required by the fractional-N frequency divider according to the clock of the clock signal FOUT after the jitter processing, the frequency of an external clock signal applied externally, such as, 24 MHz or 48 MHz, and then transmitting the M-value and the N-value to the temperature compensation processing module; and, finally, performing frequency shift ratio estimation process: the temperature compensation processor of the temperature compensation processing module using two or more K values in the OTPROM, the lookup table, and the M-value and the N-value from the FLL to obtain a frequency shift ratio estimation and transmits the frequency shift ratio estimation to the fractional-N frequency divider.
The foregoing will become better understood from a careful reading of a detailed description provided herein below with appropriate reference to the accompanying drawings.
The embodiments can be understood in more detail by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:
In the following detailed description, for purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
The temperature sensor/ADC 111: the temperature sensor obtains a current temperature and converts to a voltage, the ADC converts to a code character to control the K-value of the fractional-N frequency divider 113, with a different K-value for each different temperature.
The temperature compensation processing module 112: the temperature compensation processing module 112 comprises a temperature compensation processor, and a memory, wherein the memory has a one-time programmable read only memory (OTPROM), and a lookup table; the OTPOM records two or more K values at different temperatures, for example, two K values are recorded for two point calibration, three K values are recorded for three point calibration; the temperature compensation processor uses two or more K values in the OTPROM, the lookup table, and the M value and N value from the FLL 114 to obtain a frequency offset ratio estimation, and the frequency offset ratio estimation is sent to the fractional-N frequency divider 113 so that the fractional-N frequency divider 113 can output an accurate clock signal.
The fractional-N frequency divider 113: the fractional-N frequency divider 113 receives higher OSC frequency outputted from the LC-tank oscillator 2, such as frame clock output (FCO) and generates a clock signal FOUT, and transmits the clock signal FOUTS to the LPLL 115.
Moreover, after the fractional-N frequency divider 113 receives the frequency offset ratio estimation, the fractional-N frequency divider 113 divides the higher OSC frequency outputted from the LC-tank oscillator 2, such as frame clock output (FCO) downwards so that the fractional-N frequency divider 113 can output an accurate clock signal.
The LPLL 115: because the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 has a larger jitter, the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 uses the LPLL 115 to suppress the clock jitter of the clock signal FOUT outputted from the fractional-N frequency divider 113.
The FLL 114: The LPLL 115 transmits the clock of the clock signal FOUT after the jitter processing to the FLL 114, the FLL 114 finds the M-value and the N-value required by the fractional-N frequency divider 113 according to the clock of the clock signal FOUT after the jitter processing form the LPLL 115, the frequency of an external clock signal applied externally, such as, 24 MHz or 48 MHz, and then transmits the M-value and the N-value to the temperature compensation processing module 112, and the temperature compensation processor of the temperature compensation processing module uses two or more K values in the OTPROM, the lookup table, and the M-value and the N-value from the FLL 114 to obtain a frequency shift ratio estimation (not shown) and transmits the frequency shift ratio estimation to the fractional-N frequency divider 113 so that the fractional-N frequency divider 113 can output an accurate clock signal.
As shown in
Then, step 22 is to perform frequency shift ration estimation: the temperature compensation processing module 112 using two or more K values in the OTPROM, the lookup table, and the M-value and the N-value from the FLL 114 to obtain a frequency shift ratio estimation and transmitting the frequency shift ratio estimation to the fractional-N frequency divider 113. Then. Proceed to step 23.
Step 23 is to perform accurate clock signal outputting: based on the received frequency shift ratio estimation, the fractional-N frequency divider 113 being able to output an accurate clock signal 1131.
In performing clock jitter processing process 222: because the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 having a larger jitter, the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 using the LPLL 115 to suppress the clock jitter of the clock signal FOUT outputted from the fractional-N frequency divider 113; and then, proceeding to process 223.
In process 223, finding the M-value and N-value process: the LPLL 115 transmitting the clock of the clock signal FOUT after the jitter processing to the FLL 114, the FLL 114 finding the M-value and the N-value required by the fractional-N frequency divider 113 according to the clock of the clock signal FOUT after the jitter processing from LPLL 115, the frequency of an external clock signal applied externally, such as, 24 MHz or 48 MHz, and then transmitting the M-value and the N-value to the temperature compensation processing module 112; and then, proceeding to process 224.
In process 224, performing frequency shift ratio estimation process: the temperature compensation processor of the temperature compensation processing module 112 using two or more K values in the OTPROM, the lookup table, and the M-value and the N-value from the FLL 114 to obtain a frequency shift ratio estimation and transmits the frequency shift ratio estimation to the fractional-N frequency divider 113.
The temperature sensor/ADC 111: the temperature sensor obtains a current temperature and converts to a voltage, the ADC converts to a code character to control the K-value of the fractional-N frequency divider 113, with a different K-value for each different temperature. For example, for temperatures of 0° C./25° C./50° C., such as, at 0° C., the code character Vbe_0⇒ADC_Code_0,FLL⇒K0; while at 50° C., the code character Vbe_50⇒ADC_Code_50,FLL⇒K50; while at 25° C., the code character Vbe_25⇒ADC_Code_25,FLL⇒K25; therefore, when the temperature is at X° C., the code character Vbe_x⇒ADC_Code_X⇒Kx (the required K value); by using the lookup table to input Kx to the fractional-N frequency divider 113. Here, the exemplary temperature is not absolute. For two-point calibration, it is sufficient to measure a K-value at room temperature and a K-value at high temperature.
The temperature compensation processing module 112: the temperature compensation processing module 112 comprises a temperature compensation processor 1121, and a memory 1122, wherein the memory 1122 has a one-time programmable read only memory (OTPROM) 1123, and a lookup table (LUT) 1124; the OTPOM 1123 records two or more K values at different temperatures, for example, two K values are recorded for two point calibration, three K values are recorded for three point calibration; the temperature compensation processor 1121 uses two or more K values in the OTPROM 1123, the lookup table 1124, and the M value and N value from the FLL 114 to obtain a frequency offset ratio estimation, and the frequency offset ratio estimation is sent to the fractional-N frequency divider 113 so that the fractional-N frequency divider 113 can output an accurate clock signal 1132.
The fractional-N frequency divider 113: the fractional-N frequency divider 113 receives higher OSC frequency outputted from the LC-tank oscillator 2, such as frame clock output (FCO) and generates a clock signal FOUT, and transmits the clock signal FOUTS to the LPLL 115.
Moreover, after the fractional-N frequency divider 113 receives the frequency offset ratio estimation, the fractional-N frequency divider 113 divides the higher OSC frequency outputted from the LC-tank oscillator 2, such as frame clock output (FCO) downwards so that the fractional-N frequency divider 113 can output an accurate clock signal 1132.
The LPLL 115: because the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 has a larger jitter, the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 uses the LPLL 115 to suppress the clock jitter of the clock signal FOUT outputted from the fractional-N frequency divider 113.
The FLL 114: The LPLL 115 transmits the clock of the clock signal FOUT after the jitter processing to the FLL 114, the FLL 114 finds the M-value and the N-value required by the fractional-N frequency divider 113 according to the clock of the clock signal FOUT after the jitter processing form the LPLL 115, the frequency of an external clock signal applied externally, such as, 24 MHz or 48 MHz, and then transmits the M-value and the N-value to the temperature compensation processing module 112, and the temperature compensation processor 1121 of the temperature compensation processing module uses two or more K values in the OTPROM 1123, the lookup table 1124, and the M-value and the N-value from the FLL 114 to obtain a frequency shift ratio estimation (not shown) and transmits the frequency shift ratio estimation to the fractional-N frequency divider 113 so that the fractional-N frequency divider 113 can output an accurate clock signal 1132.
In the present embodiment, integer⇒N, f=(K+M)/2M, wherein 2M=1000000, K change by 1⇒f change by 1.0 ppm, and the LPLL 115 filters out the clock jitter outputted from the fractional-N frequency divider; the FLL 114 uses the externally applied accurate frequency 48 MHz or 24 Mhz to find N/M/K0, K25, K50, and usually 2M=1000000 is determined first, then N can be determined; M and N should be determined by the required accuracy and frequency required by the following stages.
As shown in
Then, step 32 is to perform frequency shift ration estimation: the temperature compensation processor 1122 using two or more K values in the OTPROM 1123, the lookup table 1124, and the M-value and the N-value from the FLL 114 to obtain a frequency shift ratio estimation and transmitting the frequency shift ratio estimation to the fractional-N frequency divider 113. Then. Proceed to step 33.
Step 33 is to perform accurate clock signal outputting: based on the received frequency shift ratio estimation, the fractional-N frequency divider 113 being able to output an accurate clock signal 1132.
In performing clock jitter processing process 322: because the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 having a larger jitter, the clock of the clock signal FOUT outputted from the fractional-N frequency divider 113 using the LPLL 115 to suppress the clock jitter of the clock signal FOUT outputted from the fractional-N frequency divider 113; and then, proceeding to process 323.
In process 323, finding the M-value and N-value process: the LPLL 115 transmitting the clock of the clock signal FOUT after the jitter processing to the FLL 114, the FLL 114 finding the M-value and the N-value required by the fractional-N frequency divider 113 according to the clock of the clock signal FOUT after the jitter processing from LPLL 115, the frequency of an external clock signal applied externally, such as, 24 MHz or 48 MHz, and then transmitting the M-value and the N-value to the temperature compensation processing module 112; and then, proceeding to process 324.
In process 324, performing frequency shift ratio estimation process: the temperature compensation processor of the temperature compensation processor 1121 using two or more K values in the OTPROM 1123, the lookup table, and the M-value and the N-value from the FLL 114 to obtain a frequency shift ratio estimation and transmits the frequency shift ratio estimation to the fractional-N frequency divider 113.
In summary, the signal processing system and method of the present invention is applicable to an environment of the temperature compensation processing of the resonant frequency (OSC) of the LC-tank oscillator, by using temperature sensor/analog ADC to obtain the different K values associated with the different temperatures, and recording the K-values in the one-time programmable read-only-memory (OTPROM) in the temperature-compensation processing module; the fractional-N frequency divider dividing the higher frequency OSC outputted by the LC-tank oscillator; using LPLL to suppress the clock jitter in the clock outputted by the fractional-N frequency divider, the FLL finding the M-value and N-value required by the fractional-N frequency divider according to the clock processed by the LPLL for jitters, the frequency of an external clock signal applied externally, and passing the M-value and N-value to the temperature compensation processing module, and the temperature compensation processing module transmitting the K-value, M-value, and N-value to the fractional-N frequency divider so that the fractional-N frequency divider can output accurate clock signals. The signal processing system and method of the present invention provides the following advantages:
The present invention uses a temperature sensor/ADC to obtain different K values related to different temperatures and records K values in OTPROM in temperature compensation processing module; a fractional-N frequency divider divides the higher OSC outputted by LC-tank; a linear PLL (LPLL) suppresses the timing jitter of the clock outputted by the fractional-N frequency divider, the frequency-locked loops (FLL) finds the M and N values required by fractional-N frequency divider according to the processed clock after the LPLL processing timing jitter and an applied external clock frequency, and transmits to temperature compensation processing module; and the temperature compensation processing module transmits the K, M and N values to fractional-N frequency divider so that the fractional-N frequency divider outputs accurate clock.
The present invention can use smaller chip area to achieve self-calibration of the frequency drift in the LC clock generator caused by temperature without using open loop temperature compensation circuit and binary-weighted capacitor array.
The present invention, without using XTAL, phase interpolation circuit, and single-point calibration, can make the fraction-N frequency divider output accurate clock signals.
The present invention, instead of adjusting the phase of the VCO in the analog PLL, uses digital PLL to find frequency division, and the relation between the temperature and the phase to adjust the phase so that the fraction-N frequency divider being able to output accurate clock signals.
The present invention uses the physical quantity of the temperature linear changes and the linear change of the OSC frequency with the temperature change, and using two points to determine a straight line without any restriction on the temperature range, and then using fractional-N frequency division to divide the OSC frequency to the required output frequency; in other words, using two or more temperatures of non-specific values to calibrate the frequency division so that the divided frequency is a required frequency.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 106108231 | Mar 2017 | TW | national |
