BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects as well as advantages of the invention will become clear by the following description of preferred embodiments of the invention. A number of benefits not recited in this specification will come to the attention of the skilled in the art upon the implementation of the present invention.
FIG. 1 is a block diagram illustrating a constitution of a signal processor (data compressing device) according to a preferred embodiment 1 of the present invention.
FIGS. 2A-2B are (first) illustrations of a processing concept in a data compressing method according to the preferred embodiment 1.
FIGS. 3A-3C are (second) illustrations of the processing concept in the data compressing method according to the preferred embodiment 1.
FIG. 4 is an illustration of processings in chronological order in the signal processor according to the preferred embodiment 1.
FIG. 5 is an illustration of a processing time per frame in the data compressing method according to the preferred embodiment 1 executed based on the H.264/AVC encoding method.
FIG. 6 is a block diagram illustrating a constitution of a signal processor (data compressing device) according to a preferred embodiment 2 of the present invention.
FIG. 7 is an illustration of processings in chronological order in the signal processor according to the preferred embodiment 2.
FIG. 8 is a block diagram illustrating a constitution of a signal processor (data compressing device) according to a preferred embodiment 3 of the present invention.
FIGS. 9A-9B are (first) conceptual views of parameter adjustment in a data compressing method according to the preferred embodiment 3.
FIGS. 10A-10B are (second) conceptual views of the parameter adjustment in the data compressing method according to the preferred embodiment 3.
FIG. 11 is an illustration of processings in chronological order in the signal processor according to the preferred embodiment 3.
FIG. 12 is a block diagram illustrating a constitution of a signal processor (data compressing device) according to a preferred embodiment 4 of the present invention.
FIG. 13 is an illustration of processings in chronological order in the signal processor according to the preferred embodiment 4.
FIGS. 14A-14D are schematic views of various devices comprising the signal processor according to the present invention.
FIG. 15 is a block diagram illustrating a constitution of a conventional signal processor (data compressing device).
FIGS. 16A-16 are (first) illustrations of a processing concept in the conventional signal processor.
FIGS. 17A and 17B are (second) illustrations of the processing concept in the conventional signal processor.
FIG. 18 is an illustration of processings in chronological order in the conventional signal processor.
FIG. 19 is a block diagram illustrating a constitution of another conventional signal processor (data compressing device).
FIG. 20 is an illustration of processings in chronological order in the another conventional signal processor.