Patent Grant
8837654
The disclosed embodiments relate generally to the field of signal processing at signal receivers, and in particular to a system and method for compensating for group delay distortions and, optionally, amplitude distortions at a signal receiver.
Signal receivers often include apparatus and circuitry (such as, analog signal processing circuitry) to condition received signals to have desired amplitude, phase and/or frequency characteristics. The apparatus and circuitry at the signal receivers may also be designed to eliminate or reduce the effects of interfering noise and other distortions introduced into the signals along the signal propagation path, prior to being received at the signal receivers.
In the process of conditioning the received signals, the apparatus and circuitry (such as, the analog signal processing circuitry) at the signal receivers may introduce additional signal distortions or undesired characteristics to the received signals.
One form of signal distortion that may be introduced by the apparatus and circuitry at the signal receivers is phase distortion (sometimes herein called group-delay distortion). Phase distortions introduced by the components of the signal receiver result from a non-linear phase response of the respective components of the signal receiver. Phase distortions are observed as non-linear phase vs. frequency characteristics, or a non-uniform group delay over the frequency pass band of interest. Phase distortions limit the ability of the signal receiver to combine information from signals having different frequencies, thereby limiting the accuracy of measurements derived from wideband signals obtained from combining multiple signals or multi-frequency signals.
Another form of signal distortion potentially introduced by the apparatus and circuitry at the signal receivers is amplitude distortion. Amplitude distortions introduced by the components of the signal receiver result from a non-symmetric magnitude response of the respective components of the signal receiver. Amplitude distortions are observed as non-symmetric magnitude vs. frequency characteristics over the frequency pass band of interest.
Some embodiments provide a signal receiver that includes an antenna interface for receiving signals from an antenna, analog signal processing circuitry coupled to the antenna interface for processing the received signals to produce filtered signals, sampling circuitry to sample the filtered signals so as to produce digitized received signals, a compensation mechanism to receive the digitized received signals and compensate for non-uniform group delay and amplitude distortion introduced by the analog signal processing circuitry to produce compensated digitized received signals, and a digital processor to process the compensated digitized received signals so as to produce a result.
Some embodiments provide a method of signal compensation performed at a signal receiver. The method includes configuring a compensation mechanism at the signal receiver in accordance with processed digital signals received by the compensation mechanism in response to injection of a calibration signal at the signal receiver by a calibration signal generator, the configuring including configuring the compensation mechanism to compensate for non-uniform group delay and amplitude distortion introduced by analog signal processing circuitry of the signal receiver. The method further includes receiving signals at the signal receiver, processing the received signals at the signal receiver to produce digitized received signals, and compensating the digitized received signals using the compensation mechanism to produce compensated signals.
Some embodiments provide a method of signal compensation performed at a signal receiver. The method includes receiving signals from an antenna; processing the received signals with analog signal processing circuitry to produce filtered signals; sampling the filtered signals with sampling circuitry to produce digitized received signals; compensating the digitized received signals, with a compensation mechanism, for non-uniform group delay and amplitude distortion introduced by the analog signal processing circuitry to produce compensated digitized received signals; and processing the compensated digitized received signals so as to produce a result.
In some of the aforementioned embodiments, the compensation mechanism is configured by injecting a calibration signal at the signal receiver; transforming digital signals, corresponding to the injected calibration signal, received by the compensation mechanism from time-domain to frequency-domain to produce a complex-valued frequency-domain representation of the processed digital signals; and extracting magnitude and phase values from the complex-valued frequency-domain representation of the processed digital signals. Configuring the compensation mechanism further includes computing phase residuals by subtracting the extracted phase values from target frequency-dependent phase information, computing magnitude response residuals by determining ratios of the extracted magnitude values with target magnitude response information, generating a set of complex values from the computed phase residuals and magnitude response residuals, and transforming the set of complex values from frequency-domain to time-domain to produce complex-valued time-domain filter coefficients corresponding to a finite impulse response filter.
Like reference numerals refer to corresponding parts throughout the drawings.
It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without changing the meaning of the description, so long as all occurrences of the “first contact” are renamed consistently and all occurrences of the second contact are renamed consistently. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments. However, various embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.
GNSS 100 comprises one or more GNSS satellite(s) 110 and Signal Receiver 120. GNSS satellite(s) 110 transmits signals (e.g., signals containing navigation information) to be received by Signal Receiver 120. The signals transmitted by GNSS satellite(s) 110 travel through various propagation media (e.g., layers of the atmosphere) prior to reaching Signal Receiver 120.
The propagation media include undesired Noise and Distortion Source(s) 130 which introduce noise and/or distortions into the transmitted signals, causing the signals transmitted by GNSS satellite(s) 110 to be impacted detrimentally. Some detrimental effects of noise and distortions introduced by Noise and Distortion Source(s) 130 include degradation of signal to noise ratio (e.g., by the introduction of undesired noise power with frequency content outside—and often within—the frequency bands of interest), and undesirable and often non-uniform, non-deterministic changes to the amplitude, frequency and phase content of the transmitted signals.
Signal Receiver 120 typically includes analog and digital circuitry to at least partially mitigate or counteract the detrimental effects of Noise and Distortion Source(s) 130 on the received signal.
Further, Signal Receiver 120 includes signal conditioning elements (e.g., filters and amplifiers) in the analog signal processing circuitry that selectively emphasize signals having frequencies of interest, and reject or attenuate signals that do not have frequencies within the bandwidth of interest.
Antenna Interface 204 receives signals from an antenna (e.g., Antenna 202) and optionally from a calibration signal generator (e.g., Calibration Signal Generator 230).
Receiver(s) 206 includes Analog Signal Processing Circuitry 208 and Sampling Circuitry 210. Analog Signal Processing Circuitry 208 is coupled to Antenna Interface 204 for processing the received signals to produce filtered signals. In some embodiments, Analog Signal Processing Circuitry 208 includes various frequency, amplitude and phase conditioning components, such as, one or more analog filters and/or one or more gain (amplification) stages. In some embodiments, Analog Signal Processing Circuitry 208 corresponds to or includes a low noise amplifier. In some implementations, Analog Signal Processing Circuitry 208 includes a (quadrature) demodulator to down-convert the received signals to produce orthogonal baseband signals (for example, orthogonal I and Q signal components). Sampling Circuitry 210 samples the filtered signals from Analog Signal Processing Circuitry 208 so as to produce digitized received signals. In some embodiments, circuitry for producing the digitized received signals further includes quantization circuitry and digitization circuitry. It may be noted that in some implementations, Signal Receiver 120 includes separate Receivers 206 (and consequently, separate Analog Signal Processing Circuitry 208 and Sampling Circuitry 210) for two or more frequency bands of interest. Optionally, Signal Receiver 120 includes separate Receivers 206 for every frequency band of interest. As shown in the example in
Compensation Mechanism(s) 212 receives the digitized received signals and compensates for non-uniform group delay and, in some implementations, amplitude distortion introduced by the analog signal processing circuitry 208 to produce compensated digitized received signals. In some embodiments, the compensation mechanism (e.g., Compensation Mechanism 212) compensates for signal distortions in the digitized received signals produced by the analog signal processing circuitry in one or more predefined ranges of frequencies. In some embodiments, the signal distortions are phase distortions introduced by the non-linear phase response of Analog Signal Processing Circuitry 208. The non-linear phase response of Analog Signal Processing Circuitry 208 causes undesirable variations in group delay when processing signals that span a desired range of frequencies. In some embodiments, the signal distortions include amplitude distortions introduced by a non-symmetric magnitude response of Analog Signal Processing Circuitry 208. The non-symmetric magnitude response of Analog Signal Processing Circuitry 208 causes undesirable effects on signals that span a desired range of frequencies.
In some implementations, Compensation Mechanism(s) 212 is implemented in a digital signal processor, sometimes called a DSP. In some other implementations, Compensation Mechanism(s) 212 is implemented in circuitry, such as an FIR filter and one or more registers. Alternatively, or in addition, Compensation Mechanism(s) 212 is implemented in software executed by a general purpose processor. It may be noted that the term “non-uniform,” as used herein, indicates having different delays for different frequencies in a predefined range of frequencies. In some implementations, Signal Receiver 120 is configured to include a separate Compensation Mechanism 212 for every frequency band of interest. As shown in the example in
It should be understood that the frequency bands and frequency bandwidth described (such as L1, L2, and L5 frequency bands, and corresponding bandwidth) are merely illustrative and representative; the signal receiver and methods performed by the signal receiver described herein can be configured to operate at frequency bands or frequencies not specifically listed here.
Digital Processor 214 processes compensated digitized received signals so as to produce a Result 220. In some implementations, the result (e.g., Result 220) includes a range to satellite, ranges to multiple satellites, navigation result(s), geographical location(s), and/or satellite time value(s). In some embodiments, Digital Processor 214 is implemented using one or more microprocessors or other programmable processors. Digital Processor 214 is further described herein with reference to
In some embodiments, Calibration Signal Generator 230 is coupled to Antenna Interface 204, to inject a calibration signal at Antenna Interface 204.
In some embodiments, Clock 240 provides synchronized clock timing signals to Calibration Signal Generator 230 and Sampling Circuitry 210.
In some embodiments, Antenna Interface 204, Analog Signal Processing Circuitry 208, Sampling Circuitry 210, Compensation Mechanism 212, Digital Processor 214 and Calibration Signal Generator 230 are all contained within Housing 250.
In some embodiments, Antenna Interface 204, Analog Signal Processing Circuitry 208, Sampling Circuitry 210, Compensation Mechanism 212, Digital Processor 214 and Calibration Signal Generator 230 are mounted on a single circuit board (e.g., Circuit Board 260). Alternatively, Antenna Interface 204 is not mounted on the circuit board on which the other components are mounted. Typically, in embodiments that include Housing 250, Circuit Board 260 is contained within Housing 250.
In some embodiments, the signal receiver (e.g., Signal Receiver 120) is a satellite signal receiver.
In some embodiments, Compensation Mechanism 212 is configured (for example, using Configuring Mechanism 320) to process Digitized Received Signals 312 using a finite impulse response filter or FIR filter (e.g., Complex FIR 314) using a set of complex filter coefficients (e.g., Complex FIR coefficients 334) to compensate for non-uniform group delay and, in some implementations, amplitude distortion introduced by at least the analog signal processing circuitry (e.g., Analog Signal Processing Circuitry 208).
In some embodiments, the compensation mechanism (e.g., Compensation Mechanism 212) is configured (e.g., by Configuring Mechanism 320) in accordance with signals received by the compensation mechanism in response to injection of the calibration signal at the antenna interface, for example by Calibration Signal Generator 230.
In some embodiments, Configuring Mechanism 320 performs a method of configuring the compensation mechanism as described with reference to
As shown in
An FFT 324 (e.g., N-Point FFT 324-a, shown in
Target Response Curve 326 (e.g., Target Response 404, shown in
In some embodiments, residual phase differences (e.g., Residuals 328 or Phase Residuals 406) are computed by subtracting the phase values (e.g., Actual Phase Response 402) of corresponding frequency components of the digitized received signals from the target phase values (e.g., Target Response Curve 326 or Target Response 404). In some embodiments, residual magnitude differences (e.g., Residuals 328 or Magnitude Residuals 416) are computed by determining ratios of the extracted magnitude values (e.g., Actual Magnitude Response 412) of corresponding frequency components of the digitized received signals with the target magnitude response information (e.g., Target Response Curve 326 or Target Response 404).
An inverse Fast Fourier Transform (e.g., iFFT 330) is performed on a representation of the residual phase differences (e.g., Residuals 328 or Phase Residuals 406) and, in some implementations, magnitude response residuals (e.g., Magnitude Residuals 416) to produce an initial set of complex values corresponding to FIR coefficients. It may be noted that iFFT 330 may be implemented using software executed by a digital signal processor or general purpose microprocessor, or hardware (e.g., on an FFT circuit). In some implementations, FFT 324 and iFFT 330 are implemented using the same FFT circuit, or the same program(s) executed by a digital signal processor or general purpose microprocessor.
Optionally, a windowing operation (Windowing 332) is performed on initial set of complex values obtained from iFFT 330, which conditions the results produced by iFFT 330 by reducing the magnitude of the edge components of the results of iFFT 330 by multiplying the results of iFFT 330 by a windowing function (e.g., a Tukey window, or even more specifically a Tukey 0.5 window). In some implementations, Windowing 332 is implemented using software executed by a digital signal processor or general purpose microprocessor, or hardware. “Edge components” of results of iFFT 330 are typically components not in a predefined central portion of the results. In one example, in an implementation that produces 128 complex FIR coefficients as the result of iFFT 330, sequentially numbered from 1 to 128, the center components include at least components 32 to 96, and the edge components include components 1 to 31 and 97 to 128 or a subset of components 1 to 31 and 97 to 128.
In various embodiments, any of a number of windowing functions are used to window the set of complex values obtained from iFFT 330 to produce the complex FIR coefficients, such as windowing functions described in G. Heinzel, A. Rudiger, R. Schilling, “Spectrum and spectral density estimation by the Discrete Fourier transform (DFT), including a comprehensive list of window functions and some new flat-top windows,” Internal Report, Max-Planck-Institut fur Gravitationsphysik, Hannover, 2002; and F J Harris, “On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform,” Proceedings of IEEE, vol. 66, pp. 51-83, 1978.
The method performed by Configuring Mechanism 320 is explained further in relation to
Alternatively, in some implementations, the filter coefficients stored in Coefficient Register 356 are obtained from Filter Coefficients Library 358. Filter Coefficients Library 358 stores multiple sets of filter coefficients as shown in
In some embodiments, the calibration signal produced by Calibration Signal Generator 230 includes a time domain signal corresponding to orthogonal frequency components in a predefined range of frequencies. In such embodiments, the duration (or period) of the time domain signal is equal to, or an integral multiple of, the inverse of the frequency spacing between the orthogonal frequency components. In some embodiments, the calibration signal includes a step carrier signal. In some embodiments, the calibration signal includes a swept carrier signal. In some embodiments, the calibration signal includes evenly spaced frequency components, such as frequency components from X1 MHz to X2 MHz in Y MHz increments (e.g., 1 MHz increments), where X1 and X2 MHz correspond to the frequency span or bandwidth of the received signal (received at Antenna Interface 204), sometimes called the passband of interest, and Y MHz defines the (typically uniform) spacing (i.e., frequency interval) between consecutive frequency components. In such embodiments, some implementations provide a duration (or period) of the calibration signal equal to, or an integral multiple of, the inverse of the frequency interval (i.e., spacing—e.g., Y MHz) between the consecutive frequency components.
In the example implementation shown in
Control Signal 360 controls Clock Generator 361. In some embodiments, Clock Generator 361 provides a timing reference to Quadrature Modulator 366 and to a Store 362 that stores a quadrature time series for generating orthogonal tones, also called multi-tone time-domain digital signals. In some implementations, the multi-tone time-domain digital signals are read from Store 362 and converted into analog signals by one or more Digital-to-Analog converter(s) (e.g., DAC 364-a and DAC 364-b), which provide the resulting analog signals to Quadrature Modulator 366. Quadrature Modulator 366 modulates the analog signals onto a carrier signal to produce Calibration Signal 368. From another view, Store 362 stores a time-domain representation of a target set of multi-tone signals, which are converted into an analog signal by one or more DAC's 364 and then modulated onto a carrier signal to produce the Calibration Signal 368.
In some embodiments, the calibration signal generator (e.g., Calibration Signal Generator 230) injects the calibration signal at Antenna Interface 204 at a duty cycle less than a predefined fraction (e.g., at a duty cycle less than one percent). In some embodiments, the calibration signal is injected at a low duty cycle (e.g., a duty cycle of less than 10 percent, 1 one percent, 0.1 percent or 0.02 percent). In one example, calibration signals are added for an insertion period (sometimes also called a calibration period) once per duty period (e.g., a period of time between 20 milliseconds and 2 seconds). In some embodiments, the insertion period of the calibration signal has a duration of no less than one “symbol period” of the Calibration Signal 368 (e.g., the period of time required to maintain orthogonality of all the frequency components in the calibration signal). Typically, the insertion period of the calibration signal has a duration of two or more symbol periods. In some embodiments, a very low duty cycle calibration signal minimally impacts the GNSS signal carrier to noise power density ratio (CNo).
In some embodiments, the calibration signal generator injects the calibration signal at the antenna interface as a pseudorandom or random signal, to reduce any detrimental impact on the various GNSS signal structures.
In some embodiments, the calibration signal has an amplitude at least a predefined amount (e.g., 40 dB) greater than an amplitude of the received signals from the antenna. In some embodiments, the average power of the calibration signal is less than the broadband noise floor for the signal receiver. In some implementations, the amplitude and duration of the calibration signal is determined in accordance with a criterion that the average power of the calibration signal is maintained lower than a value which would impact gain settings of a gain control circuit (e.g., an Automatic Gain Control circuit) of the signal receiver. In some embodiments, the gain control circuit corresponds to the AGC circuit of the analog signal processing circuitry of the signal receiver. In some implementations, the calibration signal is injected after fixed or variable intervals of time, such as 10 milliseconds, 10 seconds, 10 minutes, 20 minutes, etc. Maintaining intervals of time between the injection instances of the calibration signal facilitates keeping the average calibration signal power lower than a value (corresponding to the broadband noise floor of the signal receiver) that would cause the gain control circuit (e.g., the AGC circuit) to change its gain settings. In alternative embodiments, the AGC circuit may be switched off (or prevented from changing its state) during injection of the calibration signal.
In some embodiments, the calibration signal generator (e.g., Calibration Signal Generator 230) is controlled, at least in part, by the digital processor (e.g., Digital Processor 214) of the signal receiver 120. For example, the digital processor would determine the timing and/or duration of injection and potentially the interval between calibration signal injection instances. Furthermore, in some implementations having two or more receivers 206 (see
To this end, Accumulated FFT 370 includes Coherent Sample Accumulator 322 and FFT 324 (as previously described with reference to Calibration Mechanism 320, in
Coherent Sample Accumulator 322 is used to store and coherently accumulate Digitized RF samples 372 (e.g., Digitized Received Signals 312) received by the compensation mechanism (e.g., Compensation Mechanism 212) in response to injection of the calibration signal at the antenna interface (for example by Calibration Signal Generator 230). Accordingly, Digitized RF samples 372 are shifted and stored using an N-Stage Shift Register 322-a and coherently accumulated (e.g., combined by summation or filtering approaches), and optionally, averaged using N-Stage Accumulator 322-b.
FFT 324 (e.g., N-point FFT (over M symbols) 324-a) performs a complex Fourier Transform on the coherently accumulated samples, for instance using a Fast Fourier Transform implementation.
A timing reference for the signal samples (e.g., Digitized RF Samples 372) is provided, in some implementations, using Sample Clock 374 (for example, obtained from or synchronized with Clock 240). Another timing reference, Symbol Time Enable (duty cycle) 376, enables operation of the Coherent Sample Accumulator 322 and FFT 324 at times during or corresponding to injection of the calibration signal. In some embodiments, clock dividers, Divide by N 374-a and Divide by M 374-b, divide the frequency of Sample Clock 374 by predefined values (e.g., N and M, respectively) to produce clock timing signals with reduced frequencies, as required by N-Stage Accumulator 322-b and N-point FFT (over M symbols) 324-a, respectively.
Each of the above identified elements may be stored in one or more of the previously mentioned memory devices, and corresponds to a set of instructions for performing a function described above. The set of instructions can be executed by one or more processors (e.g., the CPUs 602). The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise re-arranged in various embodiments. In some embodiments, memory 610 may store a subset of the modules and data structures identified above. Furthermore, memory 610 may store additional modules and data structures not described above.
Although
In some embodiments, target phase values are previously stored. In alternative embodiments, the target phase values (e.g., Target Response Curve 326 or Target Response 404) are computed from the measured phases (e.g., Actual Phase Response 402) of the filtered signal at various frequencies, for example, using a straight line fit (e.g., Straight Line 404-a) to the phase values of corresponding frequency components of the digitized received signals.
In some embodiments, the residual phase differences (e.g., Residuals 328 or Phase Residuals 406) are computed by subtracting the phase values of corresponding frequency components of the digitized received signals from the target phase values. As shown in
In some embodiments, target magnitude values are previously stored. In alternative embodiments, the target magnitude values (e.g., Target Response Curve 326 or Target Magnitude Response 414 shown in
In some embodiments, the magnitude response residuals (e.g., Residuals 328 or Magnitude Residuals 416 shown in
In
According to method 500 shown in
The signal receiver compensates (515) the digitized received signals, with a compensation mechanism (e.g., Compensation Mechanism 212), for non-uniform group delay and amplitude distortion introduced by the analog signal processing circuitry to produce compensated digitized received signals (e.g., Compensated Digitized Received Signals 316). In some embodiments, compensating the digitized received signals includes (516) compensating for signal distortions in a predefined range of frequencies. For example, if the signal receiver is a GPS signal receiver, the predefined range of frequencies optionally includes one or more of: (L1, E1) 1559 MHz-1591 MHz, 1559 MHz to 1610 MHz, (L2, L5) 1211 MHz-1243 MHz, and 1160 MHz-1192 MHz. In some embodiments, the amplitude distortion comprises (517) deviation of a magnitude response of the analog signal processing circuitry from a uniform magnitude response across a predefined frequency range or a magnitude response curve that is symmetric with respect to a predefined center frequency of the predefined frequency range. For example, as shown in
The signal receiver processes (518) the compensated digitized received signals so as to produce a result (e.g., Result 220). In some implementations, the result includes (519) a navigation result. For example, the result includes a range to satellite, ranges to multiple satellites, navigation result(s), geographical location(s), and/or satellite time value(s).
In some embodiments, the signal receiver configures (520) the compensation mechanism to process the digitized received signals using a finite impulse response filter (FIR filter), such as Complex FIR 314 (
The signal receiver injects (526) a calibration signal at the antenna interface (e.g., Antenna Interface 204) of the signal receiver using a calibration signal generator (e.g., Calibration Signal Generator 230) coupled to the antenna interface. In some embodiments, the calibration signal generator injects (528) the calibration signal at the antenna interface at a duty cycle of less than a predefined fraction (e.g., one percent). In some embodiments, the calibration signal includes (530) a time domain signal corresponding to orthogonal frequency components in a predefined range of frequencies. In some embodiments, the calibration signal includes (532) a step carrier signal. In some embodiments, the calibration signal includes (534) a swept carrier signal. In some embodiments, the calibration signal has (536) an amplitude at least a predefined amount (e.g., 40 dB) greater than an amplitude of the received signals from the signal receiver's antenna (e.g., Antenna 202). In some implementations, the amplitude and duration of the calibration signal is determined (538) in accordance with a criterion that the average power of the calibration signal is maintained lower than a value which would impact gain settings of a gain control circuit of the signal receiver. Operation of the calibration signal generator is further described with reference to
In some embodiments, the signal receiver provides (540) synchronized clock timing signals from a clock (e.g., Clock 240), to the signal receiver's calibration signal generator and sampling circuitry.
In some implementations, Signal Receiver 120 configures (542) Compensation Mechanism 212 in accordance with signals received by Compensation Mechanism 212 in response to injection of the calibration signal at Antenna Interface 204. In some embodiments, configuring Compensation Mechanism 212 includes (543) coherently accumulating digitized received signals corresponding to the injected calibration signals. For example, as shown in
In some embodiments, Signal Receiver 120 stores (544) control instructions at Digital Processor 214. In some implementations, control instructions include (546) instructions for controlling when Calibration Signal Generator 230 injects the calibration signal at Antenna Interface 204. In some implementations, control instructions include (548) instructions for controlling configuration of Compensation Mechanism 212 in accordance with the digitized received signals received in response to the injection of the calibration signal at Antenna Interface 204.
In some embodiments, Signal Receiver 120 configures (550) Compensation Mechanism 212 by performing additional, or alternative, steps 552-564 described next, for example using Configuring Mechanism 320 (shown and described above with reference to
In some embodiments, Signal Receiver 120 transforms (552) the digitized received signals, received in response to injection of the calibration signal, from time-domain to frequency-domain to produce a complex-valued frequency-domain representation of the digitized received signals. It may be noted that a real-valued representation is a special case of a complex-valued representation. In some implementations, the transformation from time-domain to frequency-domain is a Discrete Fourier Transform implemented using, for example, a Fast Fourier Transform (FFT) implementation. As described in relation to the example embodiment in
In some embodiments, Signal Receiver 120 extracts (554) magnitude (e.g., Actual Magnitude Response 412,
In some embodiments, if the total phase change (or phase shift) over the frequency span or bandwidth of the digitized received signals exceeds 2π radians, resulting discontinuities (e.g., due to phase-wrapping) in the phase (e.g., Actual Phase Response 402,
In some implementations, Signal Receiver 120 obtains (556) target frequency-dependent phase information and target magnitude response information. For example, target frequency-dependent phase information (Target Response Curve 326 in
In some embodiments, Signal Receiver 120 computes (558) phase residuals by subtracting the extracted phase values from the target frequency-dependent phase information. For example, as shown in
In some embodiments, Signal Receiver 120 generates (560) a set of complex values from the computed phase residuals and magnitude response residuals. For example, if a computed phase residual is ‘θ’ and the computed magnitude response residual is ‘R’ for a given frequency, then the complex value generated for that frequency corresponding to magnitude ‘R’ and phase residual ‘θ’ would be of the form R×(cos θ+j sin θ).
In some implementations, Signal Receiver 120 transforms (562) the set of complex values (e.g., complex filter response) from frequency-domain to time-domain to produce complex-valued time-domain filter coefficients (e.g., FIR Coefficients 408,
In some implementations Signal Receiver 120 multiplies (564) initial complex-valued time-domain filter coefficients with a windowing function (e.g., a Tukey window) to produce the complex-valued time-domain filter coefficients. In other words, the step of transforming includes multiplying an initial set of complex-valued time-domain filter coefficients by a windowing function (e.g., Windowing 332,
According to method 570 shown in
The signal receiver configures (576) a compensation mechanism (for example, but not limited to Compensation Mechanism 212) at the signal receiver in accordance with digital signals received by the compensation mechanism in response to injection of a calibration signal at the signal receiver by a calibration signal generator (for example, but not limited to Calibration Signal Generator 230). The configuring includes (578) configuring the compensation mechanism to compensate for non-uniform group delay and amplitude distortion introduced by analog signal processing circuitry of the signal receiver. In some embodiments, the amplitude distortion comprises (579) deviation of a magnitude response of the analog signal processing circuitry from a uniform magnitude response across a predefined frequency range or a magnitude response curve that is symmetric with respect to a predefined center frequency of the predefined frequency range. For example, as shown in
The signal receiver compensates (583) the digitized received signals using the compensation mechanism to produce compensated signals. In some embodiments, compensating the digitized received signals includes (584) compensating for signal distortions in a predefined range of frequencies that includes (L1, E1) 1559 MHz-1591 MHz, or 1559 MHz to 1610 MHz, or (L2, L5) 1211 MHz-1243 MHz, or 1160 MHz-1192 MHz.
The signal receiver processes (586) the compensated signals so as to produce a result. In some implementations, the result includes (588) a navigation result. For example, the result includes a range to satellite, ranges to multiple satellites, navigation result(s), geographical location(s), and/or satellite time value(s).
The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
This application claims priority to U.S. Provisional Patent Application No. 61/657,654, filed Jun. 8, 2012, which is hereby incorporated by reference in its entirety.
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