Various embodiments described herein relate to signal sampling, and more particularly, to signal sampling timing drift compensation.
Transfer of data in high-speed communications requires accurate timing of clock signals. As the frequency of operation for system interfaces continually increases, timing tolerances become progressively tighter as smaller margins for error are allowed when data is transferred. Reliable transfer of data over an interface typically requires, at a minimum, that a window or “eye” be provided where the data value remains stable and correct, and that such a window or “eye” be reliably sampled at its center, or alternatively, a position where the data has a maximum likelihood of being the correct value.
In practice, however, timing drift caused by various factors, such as system jitter, temperature change or supply voltage variation, for example, may introduce uncertainty in the sampling process, causing the sampling point to drift off center. As the frequency of data transfer increases, the window becomes smaller, and drift may often become more problematic. In lower frequencies of operation, system designers have allowed the window to be tolerant of off-center sampling to some extent, by making the window wide enough to tolerate imprecision in window alignment.
Moreover, various schemes have been devised in attempts to alleviate the effect of timing drift in transfers of data at higher frequencies. For example, one such scheme utilizes a training method in which a transmitting device sends a test pattern over a communication link and is gradually shifted in time for a receiving device to find a center sampling position. Shifted test patterns are transmitted periodically to compensate for the drift. However, such test patterns can only be sent when no other data is being transmitted over the same link, thereby resulting in bus interface downtime in order to allow the transmitting device to send the test patterns and train the receiving device for timing compensation. Such interface downtime results in inefficient data transfer and waste of valuable time and power.
There is a need to develop a method which can keep the sampling point centered without having to stall the mission-mode data traffic.
Exemplary embodiments are directed to apparatus and method for signal sampling timing drift compensation.
In an embodiment, a method of compensating for signal sampling timing drift is provided, the method comprising: measuring raw time values between a clock and data; filtering the measured raw time values to generate filtered time information; comparing the filtered time information to an upper bound and a lower bound; and based upon a determination that the filtered time information is outside the upper bound and the lower bound, computing an amount of timing compensation based upon the filtered time information; and sending a signal to reset the clock based upon the amount of timing compensation.
In another embodiment, a method for compensating for signal sampling timing drift is provided, the method comprising the steps for: measuring raw time values between a clock and data; filtering the measured raw time values to generate filtered time information; comparing the filtered time information to an upper bound and a lower bound; and based upon a determination that the filtered time information is outside the upper bound and the lower bound, performing the steps for: computing an amount of timing compensation based upon the filtered time information; and sending a signal to reset the clock based upon the amount of timing compensation.
In another embodiment, an apparatus for compensating for signal sampling timing drift is provided, the apparatus comprising: means for measuring raw time values between a clock and data; means for filtering the measured raw time values to generate filtered time information; means for comparing the filtered time information to an upper bound and a lower bound; means for computing an amount of timing compensation based upon the filtered time information if the filtered time information is outside the upper bound and the lower bound; and means for sending a signal to reset the clock based upon the amount of timing compensation.
In yet another embodiment, a non-transitory machine-readable storage medium encoded with instructions executable to perform operations to compensate for signal sampling timing drift is provided, the instructions comprising instructions to: measure raw time values between a clock and data; filter the measured raw time values to generate filtered time information; compare the filtered time information to an upper bound and a lower bound; and based upon a determination that the filtered time information is outside the upper bound and the lower bound, compute an amount of timing compensation based upon the filtered time information; and sending a signal to reset the clock based upon the amount of timing compensation.
The accompanying drawings are presented to aid in the description of embodiments of the disclosure and are provided solely for illustration of the embodiments and not limitations thereof.
Aspects of the disclosure are described in the following description and related drawings directed to specific embodiments. Alternate embodiments may be devised without departing from the scope of the disclosure. Additionally, well known elements will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments” does not require that all embodiments include the discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a,” “an,” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Moreover, it is understood that the word “or” has the same meaning as the Boolean operator “OR,” that is, it encompasses the possibilities of “either” and “both” and is not limited to “exclusive or” (“XOR”), unless expressly stated otherwise.
Furthermore, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits, such as application specific integrated circuits (ASICs), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the disclosure may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example, “logic configured to” perform the described action.
Moreover, terms such as “transmitter” and “receiver” are intended to encompass any system, apparatus, device, component, structure, hardware, software, firmware, or any combination thereof, that are capable of, respectively, transmitting and receiving digital or analog signals, data, instructions, commands, information, bits, symbols, chips, or any combination thereof. Transmission and reception of signals, data, instructions, commands, information, bits, symbols, chips, or any combination thereof may occur over one or more analog or digital communication links, including but not limited to wireless links, wired links, optical fiber links, data buses or computer interfaces.
Although exemplary embodiments of the disclosure are described with respect to signal sampling timing drift compensation over communication links between components of a computer, for example, between a system-on-a-chip (SoC) in which a central processing unit (CPU) is embedded and a memory, such as a dynamic random access memory (DRAM), it will be understood by persons skilled in the art that the principles disclosed herein are also applicable to timing drift compensation over various other communication links.
In an embodiment, a DRAM interface 124 is also provided in the SoC 102. A DRAM control or data bus 125 is connected to the DRAM interface 124 to provide links for transmitting control signals and data to another device, such as the DRAM 104. In a further embodiment, a timing adjustment block 126 is provided in the DRAM interface 124 to adjust the timing of clock pulses in response to time information received from another device that receives the clock pulses. In an embodiment, the DRAM control or data bus 125 is connected to the timing adjustment block 126 within the DRAM interface 124. In a further embodiment, a DRAM clock bus 128 is connected to the timing adjustment block 126 within the DRAM interface 124 to provide clock pulses to the DRAM 104. Alternatively, the timing adjustment block 126 may be provided outside the DRAM interface 124 in another part of the SoC 102.
In an embodiment, the DRAM 104 includes a first receiver 130 connected to the DRAM control or data bus 125 to receive control signals as well as data from the DRAM interface 124 in the SoC 102. In an embodiment, the DRAM 104 also includes a second receiver 132 connected to the DRAM clock bus 128 to receive clock pulses from the timing adjustment block 126 of the DRAM interface 124. In a further embodiment, a first latch 134 and a second latch 136 may be provided in the DRAM 104. The first and second latches 134 and 136 may be gated D latches with a data input “D,” a clock input “en,” and an output “Q,” for example. In an embodiment, a multiplexer 138 is connected to the Q outputs of the first and second latches 134 and 136. In a further embodiment, a DRAM cell array 140 is connected to the output of the multiplexer 138.
In an embodiment, a timing drift measurement block 142 is provided in the DRAM 104 to provide time information as a feedback to the timing adjustment block 126 of the DRAM interface 124 in the SoC 102. The time information may be fed back to the timing adjustment block 126 through a communication link 144, which may be a dedicated wire or a line in an existing interface, for example. In other embodiments, the link 144 for sending the time information from the timing drift measurement block 142 to the timing adjustment block 126 may be a wireless link, an optical link, or another type of link that is capable of conveying analog signals or digital data.
In an embodiment, the first receiver 130 in the DRAM 104 which receives DRAM control signals or data through the DRAM control or data bus 125 has an output 146 connected to the D inputs of the first and second latches 134 and 136 as well as the timing drift measurement block 142. In an embodiment, the second receiver 132 in the DRAM 104 which receives DRAM clock pulses through the DRAM clock bus 128 has an output 148 connected to the clock or “en” input of the first latch 134 as well as the timing drift measurement block 142. In a further embodiment, the second receiver 132 also has a complementary output 150 connected to the clock or “en” input of the second latch 136. In an embodiment, the timing drift measurement block 142 receives both clock pulses from the second receiver 132 and the data from the first receiver 130 to measure time drift between clock pulses and data bits.
In the embodiment shown in
In the embodiment shown in
In an embodiment, not every consecutive data bit and every corresponding clock pulse need to be sampled. The reset signal may be programmed such that sampling is performed in one of every two clock pulses, for example. Sampling of data drift may be performed even less frequently, for example, once every three or four clock pulses, for example. In the embodiment shown in
Referring to
In the embodiment shown in
For example, compared to the sampled voltages of 0.31V and 0.29V in case of perfect or near perfect alignment in
Referring to the flowchart of
If, however, it is determined that the time drift is outside the upper and lower bounds in step 512, then the timing drift measurement block computes the amount of timing compensation required to reset the clock in step 514. The timing drift measurement block may then send a signal to the timing adjustment block to reset the clock based upon the amount of timing compensation required in step 516. In an embodiment, the clock may be reset by sending a new series of clock pulses from the timing adjustment block 126 in
Referring to
In an embodiment, the upper and lower bounds for the time drift used for deciding whether to reset the clock may be set as the amount of time drift allowed as a predetermined fraction of the length of a clock pulse. For example, in the embodiments described above in which the center of a data bit is measured with respect to the falling edge of a respective clock pulse, a deviation of 0% means that the falling edge of the clock pulse is exactly at the center of the data bit. An upper bound may be set at +20% of a length of the clock pulse, that is, where the center of a data bit is in advance of the falling edge of the respective clock pulse by 20% of the length of the clock pulse. Similarly, a lower bound may be set at −20% of the length of the clock pulse, that is, where the center of the data bit is behind the falling edge of the respective clock pulse by 20% of the length of the clock pulse. In an alternate embodiment, the rising edge instead of the falling edge of a clock pulse may be compared to the center of a respective data bit.
In an embodiment, if it is determined that the deviation between the rising or falling edge of a clock pulse and the center of a respective data bit is outside the upper and lower bounds, the clock may be reset by sending a series of new clock pulses by taking into account the amount of compensation required. For example, if it is determined that the center of a data bit is in advance of the falling edge of a respective clock pulse by 30% of the length of the clock pulse, which is outside the upper bound of 20% in the example described above, then an advance adjustment or compensation of 30% of the length of the clock pulse is required for the new clock pulses. In an embodiment, the clock may be reset by advancing or delaying either the rising edge or the falling edge of each clock pulse by the amount of compensation required such that the rising or falling edge of each clock pulse in the series of new clock pulses is aligned with the center of a respective data bit.
Although specific embodiments have been described with respect to timing drift measurement and adjustment for data transfer between a computer SoC 102 and a DRAM 104 as shown in
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure.
The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an embodiment of the disclosure may include a computer readable medium embodying a method for compensating signal sampling timing drift. Accordingly, the scope of the appended claims is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the disclosure.
While the foregoing disclosure describes illustrative embodiments, it should be noted that various changes and modifications could be made herein without departing from the scope of the appended claims. The functions, steps or actions in the method and apparatus claims in accordance with the embodiments described herein need not be performed in any particular order unless explicitly stated otherwise. Furthermore, although elements may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.