Patent Grant
9252827
The present disclosure relates generally to wireless devices for communication systems. More specifically, the present disclosure relates to systems and methods for a signal splitting carrier aggregation receiver architecture.
Electronic devices (cellular telephones, wireless modems, computers, digital music players, Global Positioning System units, Personal Digital Assistants, gaming devices, etc.) have become a part of everyday life. Small computing devices are now placed in everything from automobiles to housing locks. The complexity of electronic devices has increased dramatically in the last few years. For example, many electronic devices have one or more processors that help control the device, as well as a number of digital circuits to support the processor and other parts of the device.
These electronic devices may communicate wirelessly with each other and with a network. As the demand for information by these electronic devices has increased, the downlink throughput has also increased. One such way to increase downlink throughput is the use of carrier aggregation. In carrier aggregation, multiple carriers may be aggregated on the physical layer to provide the required bandwidth (and thus the required throughput).
It may be desirable for an electronic device to maximize battery life. Because an electronic device often runs on a battery with a limited operation time, reductions in the power consumption of an electronic device may increase the desirability and functionality of the electronic device.
The electronic devices have also become smaller and cheaper. To facilitate both the decrease in size and the decrease in cost, additional circuitry and more complex circuitry are being used on integrated circuits. Thus, any reduction in the die area used by circuitry may reduce both the size and cost of an electronic device. Benefits may be realized by improvements to electronic devices that allow an electronic device to participate in carrier aggregation while minimizing the cost and size of the electronic device while also minimizing the power consumption of the electronic device.
A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a primary signal splitting carrier aggregation architecture that includes a primary antenna and a transceiver chip. The primary signal splitting carrier aggregation architecture reuses a first diversity/simultaneous hybrid dual receiver path. The wireless communication device also includes a secondary signal splitting carrier aggregation architecture that includes a secondary antenna and a receiver chip. The secondary signal splitting carrier aggregation architecture reuses a second diversity/simultaneous hybrid dual receiver path.
The primary signal splitting carrier aggregation architecture and the secondary signal splitting carrier aggregation architecture may not require four antennas, a power splitter, an external low noise amplifier or die-to-die signal routing. The transceiver chip may include a transmitter, a first primary receiver and a first secondary receiver. The receiver chip may include a second primary receiver and a second secondary receiver. Each receiver may include multiple low noise amplifiers for a first band and multiple low noise amplifiers for a second band. Each low noise amplifier may include a first stage amplifier and a second stage amplifier.
The first stage amplifier may be a transconductance stage and the second stage amplifier may be a cascode stage. In one configuration, the first band may be a low band and the second band may be a mid band. In another configuration, the first band may be a low band and the second band may be a high band. In yet another configuration, the first band may be a mid band and the second band may be a high band.
A first routing may be used from the primary antenna through the first primary receiver to obtain a first primary inphase/quadrature signal. A second routing may be used from the primary antenna through the first secondary receiver to obtain a first secondary inphase/quadrature signal. A third routing may be used from the secondary antenna through the second primary receiver to obtain a second primary inphase/quadrature signal. A fourth routing may be used from the secondary antenna through the second secondary receiver to obtain a second secondary inphase/quadrature signal.
The primary signal splitting carrier aggregation architecture and the secondary signal splitting carrier aggregation architecture may be in inter-band operation. The second routing may pass through a first signal splitting stage. The fourth routing may pass through a second signal splitting stage.
The first signal splitting stage may route a signal output from a first stage amplifier in a first band low noise amplifier of the first primary receiver to a second stage amplifier in a second band low noise amplifier of the first secondary receiver. The second signal splitting stage may route a signal output from a first stage amplifier in a first band low noise amplifier of the second primary receiver to a second stage amplifier in a second band low noise amplifier of the second secondary receiver.
The first signal splitting stage may route a signal output from a second stage amplifier in a first band low noise amplifier of the first primary receiver to a mixer in the first secondary receiver. The second signal splitting stage may route a signal output from a second stage amplifier in a first band low noise amplifier of the second primary receiver to a mixer in the second secondary receiver.
The primary signal splitting carrier aggregation architecture and the secondary signal splitting carrier aggregation architecture may be in intra-band operation. The second routing may pass through a first signal splitting stage. The fourth routing may pass through a second signal splitting stage. The first signal splitting stage may split a signal output from a first stage amplifier in a first band low noise amplifier of the first primary receiver, route the signal to a second stage amplifier in the first band low noise amplifier of the first primary receiver and route the signal to a second stage amplifier in a second band low noise amplifier of the first secondary receiver. The second signal splitting stage may split a signal output from a first stage amplifier in a first band low noise amplifier of the second primary receiver, route the signal to a second stage amplifier in the first band low noise amplifier of the second primary receiver and route the signal to a second stage amplifier in a second band low noise amplifier of the second secondary receiver.
The first signal splitting stage may split a signal output from a second stage amplifier in a first band low noise amplifier of the first primary receiver, route the signal to a first mixer of the first primary receiver and route the signal to a second mixer of the second primary receiver. The second signal splitting stage may split a signal output from a second stage amplifier in a first band low noise amplifier of the second primary receiver, route the signal to a first mixer of the second primary receiver and route the signal to a second mixer of the second primary receiver.
A method for receiving a multiple carrier signal using a primary signal splitting carrier aggregation architecture and a secondary signal splitting carrier aggregation architecture is also described. A first signal is received using a primary antenna. The first signal is routed through a first primary receiver on a transceiver chip in the primary signal splitting carrier aggregation architecture to obtain a first primary inphase/quadrature signal. The first signal is routed through a first secondary receiver on the transceiver chip to obtain a first secondary inphase/quadrature signal. A second signal is received using a secondary antenna. The second signal is routed through a second primary receiver on a receiver chip in the secondary signal splitting carrier aggregation architecture to obtain a second primary inphase/quadrature signal. The first signal is routed through a second secondary receiver on the receiver chip to obtain a second secondary inphase/quadrature signal.
An apparatus for receiving a multiple carrier signal using a primary signal splitting carrier aggregation architecture and a secondary signal splitting carrier aggregation architecture is described. The apparatus includes means for receiving a first signal using a primary antenna. The apparatus also includes means for routing the first signal through a first primary receiver on a transceiver chip in the primary signal splitting carrier aggregation architecture to obtain a first primary inphase/quadrature signal. The apparatus further includes means for routing the first signal through a first secondary receiver on the transceiver chip to obtain a first secondary inphase/quadrature signal. The apparatus also includes means for receiving a second signal using a secondary antenna. The apparatus further includes means for routing the second signal through a second primary receiver on a receiver chip in the secondary signal splitting carrier aggregation architecture to obtain a second primary inphase/quadrature signal. The apparatus also includes means for routing the first signal through a second secondary receiver on the receiver chip to obtain a second secondary inphase/quadrature signal.
The 3rd Generation Partnership Project (3GPP) is a collaboration between groups of telecommunications associations that aims to define a globally applicable 3rd generation (3G) mobile phone specification. 3GPP Long Term Evolution (LTE) is a 3GPP project aimed at improving the Universal Mobile Telecommunications System (UMTS) mobile phone standard. The 3GPP may define specifications for the next generation of mobile networks, mobile systems and mobile devices. In 3GPP LTE, a mobile station or device may be referred to as a “user equipment” (UE).
3GPP specifications are based on evolved Global System for Mobile Communications (GSM) specifications, which are generally known as the Universal Mobile Telecommunications System (UMTS). 3GPP standards are structured as releases. Discussion of 3GPP thus frequently refers to the functionality in one release or another. For example, Release 99 specifies the first UMTS third generation (3G) networks, incorporating a CDMA air interface. Release 6 integrates operation with wireless local area networks (LAN) networks and adds High Speed Uplink Packet Access (HSUPA). Release 8 introduces dual downlink carriers and Release 9 extends dual carrier operation to uplink for UMTS.
CDMA2000 is a family of 3rd generation (3G) technology standards that use code division multiple access (CDMA) to send voice, data and signaling between wireless devices. CDMA2000 may include CDMA2000 1X, CDMA2000 EV-DO Rev. 0, CDMA2000 EV-DO Rev. A and CDMA2000 EV-DO Rev. B. 1x or 1xRTT refers to the core CDMA2000 wireless air interface standard. 1x more specifically refers to 1 times Radio Transmission Technology and indicates the same radio frequency (RF) bandwidth as used in IS-95. 1xRTT adds 64 additional traffic channels to the forward link. EV-DO refers to Evolution-Data Optimized. EV-DO is a telecommunications standard for the wireless transmission of data through radio signals.
A wireless communication device 104 may operate in a wireless communication system 100 that includes other wireless devices, such as base stations. A base station is a station that communicates with one or more wireless communication devices 104. A base station may also be referred to as, and may include some or all of the functionality of, an access point, a broadcast transmitter, a Node B, an evolved Node B, etc. Each base station provides communication coverage for a particular geographic area. A base station may provide communication coverage for one or more wireless communication devices 104. The term “cell” can refer to a base station and/or its coverage area, depending on the context in which the term is used.
Communications in a wireless communication system 100 (e.g., a multiple-access system) may be achieved through transmissions over a wireless link. Such a communication link may be established via a single-input and single-output (SISO) or a multiple-input and multiple-output (MIMO) system. A multiple-input and multiple-output (MIMO) system includes transmitter(s) and receiver(s) equipped, respectively, with multiple (NT) transmit antennas and multiple (NR) receive antennas for data transmission. SISO systems are particular instances of a multiple-input and multiple-output (MIMO) system. The multiple-input and multiple-output (MIMO) system can provide improved performance (e.g., higher throughput, greater capacity or improved reliability) if the additional dimensionalities created by the multiple transmit and receive antennas are utilized.
The wireless communication system 100 may utilize both single-input and multiple-output (SIMO) and multiple-input and multiple-output (MIMO). The wireless communication system 100 may be a multiple-access system capable of supporting communication with multiple wireless communication devices 104 by sharing the available system resources (e.g., bandwidth and transmit power). Examples of such multiple-access systems include code division multiple access (CDMA) systems, wideband code division multiple access (W-CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier frequency division multiple access (SC-FDMA) systems, 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) systems and spatial division multiple access (SDMA) systems.
The wireless communication device 104 may utilize signal splitting. In signal splitting, signals are directed to a specific path. One form of signal splitting is current steering. In one configuration of intra-band carrier aggregation, signal splitting refers to taking a signal from the output of a first stage amplifier (such as a transconductance stage (Gm)), splitting the signal and piping the signal into two separate primary and secondary stage amplifiers (such as cascode stages (Cas)) and subsequent primary and diversity mixers for carrier aggregation. In another configuration of intra-band carrier aggregation, signal splitting refers to taking a signal from the output of a second stage amplifier (such as a cascode stage (Cas)), splitting the signal and piping the signal into two separate primary and diversity mixers for carrier aggregation.
In one configuration of inter-band carrier aggregation, signal splitting refers to taking a signal output from a first stage amplifier (such as a transconductance stage (Gm)) and steering (or diverting or pumping) the signal into a second stage amplifier (such as a cascode stage (Cas)) and subsequent mixer in the diversity path to be downconverted using a diversity local oscillator (LO). In another configuration of inter-band carrier aggregation, signal splitting refers to taking a signal output from a second stage amplifier (such as a cascode stage (Cas)) and steering (or diverting or pumping) the signal into a subsequent mixer in the diversity path to be downconverted using a diversity local oscillator (LO). The signal steering herein is current steering.
However, voltage steering may also be used. In one configuration of voltage steering for inter-band carrier aggregation, a signal output from a first stage amplifier (such as a transconductance stage (Gm)) may be diverted to a second stage amplifier (such as a cascode stage (Cas)) and subsequent mixer in the diversity path to be downconverted using a diversity local oscillator (LO). In another configuration of voltage steering for inter-band carrier aggregation, a signal output from a second stage amplifier (such as a cascode stage (Cas)) may be diverted to a subsequent mixer in the diversity path to be downconverted using a diversity local oscillator (LO).
The wireless communication device 104 may include a primary antenna 106 and a secondary antenna 108. The secondary antenna 108 may be referred to as the diversity antenna. A transceiver chip 110 may be coupled to the primary antenna 106. The transceiver chip 110 may include a transmitter, a primary receiver (PRx) and a secondary receiver (SRx). The transceiver chip 110 may output a first PRx inphase/quadrature (I/Q) signal 114 and a first SRx inphase/quadrature (I/Q) signal 116 to a baseband digital modem 122. The configuration of the primary antenna 106 and the transceiver chip 110 may be referred to as a primary signal splitting carrier aggregation architecture 125. The primary signal splitting carrier aggregation architecture 125 is discussed in additional detail below in relation to
In general, the primary signal splitting carrier aggregation architecture 125 may split the received signal into the first PRx inphase/quadrature (I/Q) signal 114 using a low noise amplifier (LNA) in the primary receiver (PRx) and the first SRx inphase/quadrature (I/Q) signal 116 using a routing between a first low noise amplifier (LNA) in the primary receiver (PRx) and a second low noise amplifier (LNA) in the secondary receiver (SRx) of the transceiver chip 110. The routing may couple the output of a stage in the first low noise amplifier (LNA) to the input of a stage in the second low noise amplifier (LNA). There may be many different ways to split the signals. In one configuration, the stage in the first low noise amplifier (LNA) may be a transconductance stage (Gm) and the stage in the second low noise amplifier (LNA) may be a cascode stage (Cas). In another configuration, the first stage may be a transconductance stage (Gm) and the second stage may be a transformer used to split the signal.
A receiver chip 112 may be coupled to the secondary antenna 108. The receiver chip 112 may include both a primary receiver (PRx) and a secondary receiver (SRx). The receiver chip 112 may output a second PRx inphase/quadrature (I/Q) signal 118 and a second SRx inphase/quadrature (I/Q) signal 120 to the baseband digital modem 122. The configuration of the secondary antenna 108 and the receiver chip 112 may be referred to as a secondary signal splitting carrier aggregation architecture 127. The secondary signal splitting carrier aggregation architecture 127 is discussed in additional detail below in relation to
In general, the secondary signal splitting carrier aggregation architecture 127 may split the received signal into the second PRx inphase/quadrature (I/Q) signal 118 using a low noise amplifier (LNA) in the primary receiver (PRx) and the second SRx inphase/quadrature (I/Q) signal 120 using a routing between a first low noise amplifier (LNA) in the primary receiver (PRx) and a second low noise amplifier (LNA) in the secondary receiver (SRx) of the receiver chip 112. There may be many different ways to split the signals. In one configuration, the stage in the first low noise amplifier (LNA) may be a transconductance stage (Gm) and the stage in the second low noise amplifier (LNA) may be a cascode stage (Cas). In another configuration, the first stage may be a transconductance stage (Gm) and the second stage may be a transformer used to split the signal.
The wireless communication device 104 may use a signal splitting carrier aggregation architecture that reuses the diversity/simultaneous hybrid dual receiver (SHDR) path. Carrier aggregation may be achieved by coupling the primary receiver (PRx) signal in a chip (i.e., in the transceiver chip 110 and the receiver chip 112) to the diversity receiver (DRx) path. One advantage of the signal splitting carrier aggregation architecture of the present systems and methods is the ability to operate using only two antennas. Because a wireless communication device 104 with less antennas is cheaper, less bulky and less complicated, a wireless communication device 104 with the minimum number of antennas may be advantageous.
The wireless communication device 104 of the present systems and methods does not require the use of a power splitter. By removing a power splitter from the wireless communication device 104, the wireless communication device 104 may consume less power. Furthermore, the lack of a power splitter may reduce the cost of the wireless communication device 104 and free up die area. The signal splitting carrier aggregation architecture of the present systems and methods may also not require the use of external low noise amplifiers (LNAs). External low noise amplifiers (LNAs) may consume large amounts of power and increase the cost of a wireless communication device 104. Another benefit of the signal splitting carrier aggregation architecture of the present systems and methods is the ability to operate without die-to-die signal routing. Removing die-to-die signal routing may reduce both the complexity and cost of the wireless communication device 104. Removing die-to-die signaling may also allow for optimal placement of antennas on the wireless communication device 104. The signal splitting carrier aggregation architecture may have four synthesizers running.
The baseband digital modem 122 may perform processing on the first PRx inphase/quadrature (I/Q) signal 114, the second PRx inphase/quadrature (I/Q) signal 118, the first SRx inphase/quadrature (I/Q) signal 116 and the second SRx inphase/quadrature (I/Q) signal 120. For example, the baseband digital modem 122 may convert the signals to the digital domain using analog-to-digital converters (ADCs) and perform digital processing on the signals using digital signal processors (DSPs). The baseband digital modem 122 may then output a first carrier signal 124a, a second carrier signal 124b, a third carrier signal 124c and a fourth carrier signal 124d. A carrier signal may refer to the carrier that the signal used.
In one configuration, the first carrier signal 124a and the second carrier signal 124b may be located in the low band while the third carrier signal 124c and the fourth carrier signal 124d are located within the midband. This may be referred to as inter-band operation or Dual-Band 4-Carrier according to Rel-10. Inter-band operation is discussed in additional detail below in relation to
In another configuration, the wireless communication device 104 may operate in simultaneous hybrid dual receiver (SHDR) mode. In simultaneous hybrid dual receiver (SHDR) mode, only the transceiver chip 110 may be used (i.e., the receiver chip 112 may be disabled). The configuration of the transceiver chip 110 operating in inter-band simultaneous hybrid dual receiver (SHDR) mode is discussed below in relation to
In yet another configuration, the wireless communication device 104 may operate in diversity mode. In diversity mode, both the transceiver chip 110 and the receiver chip 112 are tuned to receive the same carrier frequency. The configuration of the transceiver chip 110 operating in diversity mode is discussed below in relation to
The low-pass high-pass diplexer 226 may be coupled to the switch 228. The switch 228 may have two inputs (the signal that includes the bundled low band frequencies and the signal that includes the bundled high band frequencies) and multiple outputs. In one configuration, the switch 228 may have six possible outputs to the four duplexers 230 (representing the six possible configurations of duplexer 230 pairs). The four duplexers 230 may include a first low band (LB1) duplexer 230a, a second low band (LB2) duplexer 230b, a first midband (MB1) duplexer 230c and a second midband (MB2) duplexer 230d.
As discussed above, the transceiver chip 210 may include a transmitter 232, a primary receiver (PRx) 234 and a secondary receiver (SRx) 236. The transmitter 232 may include two low band outputs (LB1_Tx and LB2_Tx) and two midband outputs (MB1_Tx and MB2_Tx). The first low band output (LB1_Tx) may be coupled to the first low band (LB1) duplexer 230a via a power amplifier (PA) 238a. The second low band output (LB2_Tx) may be coupled to the second low band (LB2) duplexer 230b via a power amplifier 238b. The first midband output (MB1_Tx) may be coupled to the first midband (MB1) duplexer 230c via a power amplifier 238c. The second midband output (MB2_Tx) may be coupled to the second midband (MB2) duplexer 230d via a power amplifier 238d.
The primary receiver (PRx) 234 may include a first low band input (LB1_PRx) coupled to the first low band (LB1) duplexer 230a, a second low band input (LB2_PRx) coupled to the second low band (LB2) duplexer 230b, a first midband input (MB1_PRx) coupled to the first midband (MB1) duplexer 230c and a second midband input (MB2_PRx) coupled to the second midband (MB2) duplexer 230d. The first low band input (LB1_PRx) may be coupled to a first low band (LB1) low noise amplifier (LNA) 240a that includes a transconductance stage (Gm) 244a and a cascode stage (Cas) 246a. The second low band input (LB2_PRx) may be coupled to a second low band (LB2) low noise amplifier (LNA) 240b that includes a transconductance stage (Gm) 244b and a cascode stage (Cas) 246b. The first midband input (MB1_PRx) may be coupled to a first midband (MB1) low noise amplifier (LNA) 242a that includes a transconductance stage (Gm) 244c and a cascode stage (Cas) 246c. The second midband input (MB2_PRx) may be coupled to a second midband (MB2) low noise amplifier (LNA) 242a that includes a transconductance stage (Gm) 244d and a cascode stage (Cas) 246d.
The primary receiver (PRx) 234 may also include a downconverter (DnC) 248a. The downconverter (DnC) 248a may be coupled to the output of the first low band (LB1) low noise amplifier (LNA) 240a, the output of the second low band (LB2) low noise amplifier (LNA) 240b, the output of the first midband (MB1) low noise amplifier (LNA) 242a and the output of the second midband (MB2) low noise amplifier (LNA) 242b.
The primary receiver (PRx) 234 may include a phase locked loop (PLL) 254a, a voltage controlled oscillator (VCO) 252a and a Div stage 250a that are used to generate the downconverting frequency for the downconverter (DnC) 248a. The output of the downconverter (DnC) 248a may be coupled to a primary receiver (PRx) baseband filter (BBF) 256. The primary receiver (PRx) baseband filter (BBF) 256 may then output the first PRx inphase/quadrature (I/Q) signal 214.
The secondary receiver (SRx) 236 may include a first low band input (LB1_SRx), a second low band input (LB2_SRx), a first midband input (MB1_SRx) and a second midband input (MB2_SRx) that are disabled. The first low band input (LB1_SRx) may be coupled to a first low band (LB1) low noise amplifier (LNA) 240c that includes a transconductance stage (Gm) 244e and a cascode stage (Cas) 246e. The second low band input (LB2_SRx) may be coupled to a second low band (LB2) low noise amplifier (LNA) 240d that includes a transconductance stage (Gm) 244f and a cascode stage (Cas) 246f. The first midband input (MB1_SRx) may be coupled to a first midband (MB1) low noise amplifier (LNA) 242c that includes a transconductance stage (Gm) 244g and a cascode stage (Cas) 246g. The second midband input (MB2_SRx) may be coupled to a second midband (MB2) low noise amplifier (LNA) 242d that includes a transconductance stage (Gm) 244h and a cascode stage (Cas) 246h. In one configuration, the first low band (LB1) low noise amplifier (LNA) 240c, the second low band (LB2) low noise amplifier (LNA) 240d, the first midband (MB1) low noise amplifier (LNA) 242c and the second midband (MB2) low noise amplifier (LNA) 242d of the secondary receiver (SRx) 236 may each be disabled. However, portions within some of the low noise amplifiers (LNAs) 240c-d, 242c-d may still be used (e.g., the transconductance stage (Gm) 244 and the Cascode stage (Cas) 246) to allow the reuse of the diversity/simultaneous hybrid dual receiver (SHDR) receiver path (i.e., for the primary signal splitting carrier aggregation architecture 225).
The secondary receiver (SRx) 236 may also include a downconverter (DnC) 248b. The downconverter (DnC) 248b may be coupled to the output of the first low band (LB1) low noise amplifier (LNA) 240c, the output of the second low band (LB2) low noise amplifier (LNA) 240d, the output of the first midband (MB1) low noise amplifier (LNA) 242c and the output of the second midband (MB2) low noise amplifier (LNA) 242d. The secondary receiver (SRx) 236 may further include a phase locked loop (PLL) 254b, a voltage controlled oscillator (VCO) 252b and a Div stage 250b that are used to generate the downconverting frequency for the downconverter (DnC) 248b.
The output of the downconverter (DnC) 248b may be coupled to a secondary receiver (SRx) baseband filter (BBF) 258. The secondary receiver (SRx) baseband filter (BBF) 258 may then output the first SRx inphase/quadrature (I/Q) signal 216. In one configuration, the secondary receiver (SRx) 236 may not include the secondary receiver (SRx) voltage controlled oscillator (VCO) 252b and the phase locked loop (PLL) 254b or the secondary receiver (SRx) voltage controlled oscillator (VCO) 252b and the phase locked loop (PLL) 254b may be disabled. Instead, the transceiver chip 210 may pump the same voltage controlled oscillator (VCO) signal 251 used in the primary receiver (PRx) 234 to the secondary receiver (SRx) 236.
The low-pass high-pass diplexer 326 may be coupled to the switch 328. The switch 328 may have two inputs (the signal that includes the bundled low band frequencies and the signal that includes the bundled high band frequencies) and multiple outputs. In one configuration, the switch 328 may have six possible outputs to the four surface acoustic wave (SAW) filters 360, 362 (representing the four possible configurations of surface acoustic wave (SAW) filter 360, 362 pairs). The four surface acoustic wave (SAW) filters 360, 362 may include a first low band (LB1) surface acoustic wave (SAW) filter 360a, a second low band (LB2) surface acoustic wave (SAW) filter 360b, a first midband (MB1) surface acoustic wave (SAW) filter 362a and a second midband (MB2) surface acoustic wave (SAW) filter 362b.
The receiver chip 312 may include a primary receiver (PRx) 334 and a secondary receiver (SRx) 336. The primary receiver (PRx) 334 may include a first low band input (LB1_PRx) coupled to the first low band (LB1) surface acoustic wave (SAW) filter 360a, a second low band input (LB2_PRx) coupled to the second low band (LB2) surface acoustic wave (SAW) filter 360b, a first midband input (MB1_PRx) coupled to the first midband (MB1) surface acoustic wave (SAW) filter 362a and a second midband input (MB2_PRx) coupled to the second midband (MB2) surface acoustic wave (SAW) filter 362b. The first low band input (LB1_PRx) may be coupled to a first low band (LB1) low noise amplifier (LNA) 340a that includes a transconductance stage (Gm) 344a and a cascode stage (Cas) 346a. The second low band input (LB2_PRx) may be coupled to a second low band (LB2) low noise amplifier (LNA) 340b that includes a transconductance stage (Gm) 344b and a cascode stage (Cas) 346b. The first midband input (MB1_PRx) may be coupled to a first midband (MB1) low noise amplifier (LNA) 342a that includes a transconductance stage (Gm) 344c and a cascode stage (Cas) 346c. The second midband input (MB2_PRx) may be coupled to a second midband (MB2) low noise amplifier (LNA) 342b that includes a transconductance stage (Gm) 344d and a cascode stage (Cas) 346d.
The primary receiver (PRx) 334 may also include a downconverter (DnC) 348a. The downconverter (DnC) 348a may be coupled to the output of the first low band (LB1) low noise amplifier (LNA) 340a, the output of the second low band (LB2) low noise amplifier (LNA) 340b, the output of the first midband (MB1) low noise amplifier (LNA) 342a and the output of the second midband (MB2) low noise amplifier (LNA) 342b.
The primary receiver (PRx) 334 may include a phase locked loop (PLL) 354a, a voltage controlled oscillator (VCO) 352a and a Div stage 350a that are used to generate the downconverting frequency for the downconverter (DnC) 348a. The output of the downconverter (DnC) 348a may be coupled to a primary receiver (PRx) baseband filter (BBF) 356. The primary receiver (PRx) baseband filter (BBF) 356 may then output the second PRx inphase/quadrature (I/Q) signal 318.
The secondary receiver (SRx) 336 may include a first low band input (LB1_SRx), a second low band input (LB2_SRx), a first midband input (MB1_SRx) and a second midband input (MB2_SRx) that are disabled. The first low band input (LB1_SRx) may be coupled to a first low band (LB1) low noise amplifier (LNA) 340c that includes a transconductance stage (Gm) 344e and a cascode stage (Cas) 346e. The second low band input (LB2_SRx) may be coupled to a second low band (LB2) low noise amplifier (LNA) 340d that includes a transconductance stage (Gm) 344f and a cascode stage (Cas) 346f. The first midband input (MB1_SRx) may be coupled to a first midband (MB1) low noise amplifier (LNA) 342c that includes a transconductance stage (Gm) 344g and a cascode stage (Cas) 346g. The second midband input (MB2_SRx) may be coupled to a second midband (MB2) low noise amplifier (LNA) 342d that includes a transconductance stage (Gm) 344h and a cascode stage (Cas) 346h. In one configuration, the first low band (LB1) low noise amplifier (LNA) 340c, the second low band (LB2) low noise amplifier (LNA) 340d, the first midband (MB1) low noise amplifier (LNA) 342c and the second midband (MB2) low noise amplifier (LNA) 342d may each be disabled. However, portions within some of the low noise amplifiers (LNAs) 340c-d, 342c-d may still be used (e.g., the transconductance stage (Gm) 344 and the cascode stage (Cas) 346) to allow the reuse of the diversity/simultaneous hybrid dual receiver (SHDR) receiver path (i.e., for the secondary signal splitting carrier aggregation architecture 327).
The secondary receiver (SRx) 336 may also include a downconverter (DnC) 348b. The downconverter (DnC) 348b may be coupled to the output of the first low band (LB1) low noise amplifier (LNA) 340c, the output of the second low band (LB2) low noise amplifier (LNA) 340d, the output of the first midband (MB1) low noise amplifier (LNA) 342c and the output of the second midband (MB2) low noise amplifier (LNA) 342d. The secondary receiver (SRx) 336 may further include a phase locked loop (PLL) 354b, a voltage controlled oscillator (VCO) 352b and a Div stage 350b that are used to generate the downconverting frequency for the downconverter (DnC) 348b. The output of the downconverter (DnC) 348b may be coupled to a secondary receiver (SRx) baseband filter (BBF) 358. The secondary receiver (SRx) baseband filter (BBF) 358 may then output the second SRx inphase/quadrature (I/Q) signal 320. In one configuration, the secondary receiver (SRx) 336 may not include the secondary receiver (SRx) voltage controlled oscillator (VCO) 352b and the phase locked loop (PLL) 354b or the secondary receiver (SRx) voltage controlled oscillator (VCO) 352b and the phase locked loop (PLL) 354b may be disabled. Instead, the receiver chip 312 may pump the same voltage controlled oscillator (VCO) signal 351 used in the primary receiver (PRx) 334 to the secondary receiver (SRx) 336.
The wireless communication device 104 may receive 408 a second signal using a secondary antenna 108. The wireless communication device 104 may route 410 the second signal through a primary receiver (PRx) 334 on a receiver chip 112 to obtain a second PRx inphase/quadrature (I/Q) signal 118. The wireless communication device 104 may also route 412 the second signal through a secondary receiver (SRx) 336 on the receiver chip 112 to obtain a second SRx inphase/quadrature (I/Q) signal 120.
The routing 535 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 is also shown. The first SRx inphase/quadrature (I/Q) signal 216 may include two carriers from a second band (e.g., the midband) for this configuration. The routing 535 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 may pass through a signal splitting stage 533. The signal splitting stage 533 may allow the primary signal splitting carrier aggregation architecture 225 to reuse the diversity/simultaneous hybrid dual receiver (SHDR) receiver path. The signal splitting stage 533 may take the signal from a low noise amplifier (LNA) (e.g., the first midband (MB1) low noise amplifier (LNA) 242a) in the primary receiver (PRx) 234 after the transconductance stage (Gm) 244c and route the signal to a stage (e.g., the cascode stage (Cas) 246g) of a low noise amplifier (LNA) (e.g., the first midband (MB1) low noise amplifier (LNA) 242c) in the secondary receiver (SRx) 236. In another configuration (not shown), the signal splitting stage 533 may take the signal input to the first midband (MB1) low noise amplifier (LNA) 242a in the primary receiver (PRx) 234 and route the signal to the transconductance stage (Gm) 244g of the first midband (MB1) low noise amplifier (LNA) 242c in the secondary receiver (SRx) 236. The signal splitting stage 533 is discussed in additional detail below in relation to
The routing 637 from the secondary antenna 308 through the secondary receiver (SRx) 336 to obtain the second SRx inphase/quadrature (I/Q) signal 320 is also shown. The second SRx inphase/quadrature (I/Q) signal 320 may include two carriers from the midband for this configuration. The routing 637 from the secondary antenna 308 through the secondary receiver (SRx) 336 to obtain the second SRx inphase/quadrature (I/Q) signal 320 may pass through a signal splitting stage 633. The signal splitting stage 633 may allow the secondary signal splitting carrier aggregation architecture 327 to reuse the diversity/simultaneous hybrid dual receiver (SHDR) receiver path. The signal splitting stage 633 may take the signal from the first midband (MB1) low noise amplifier (LNA) 342a in the primary receiver (PRx) 334 after the transconductance stage (Gm) 344c and route the signal to the cascode stage (Cas) 346g of the first midband (MB1) low noise amplifier (LNA) 342c in the secondary receiver (SRx) 336. In another configuration (not shown), the signal splitting stage 633 may take the signal input to the first midband (MB1) low noise amplifier (LNA) 342b in the primary receiver (PRx) 334 and route the signal to the transconductance stage (Gm) 344g of the first midband (MB1) low noise amplifier (LNA) 342c in the secondary receiver (SRx) 336. The signal splitting stage 633 is discussed in additional detail below in relation to
The routing 739 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 is also shown. The first SRx inphase/quadrature (I/Q) signal 216 may include the other two carriers from the low band for this configuration. The routing 739 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 may pass through a signal splitting stage 733. As discussed above, the signal splitting stage 733 may allow the primary signal splitting carrier aggregation architecture 225 to reuse the diversity/simultaneous hybrid dual receiver (SHDR) receiver path. The signal splitting stage 733 may take the signal from the first low band (LB1) low noise amplifier (LNA) 240a in the primary receiver (PRx) 234 after the transconductance stage (Gm) 244a and route the signal to the cascode stage (Cas) 246e of the first low band (LB1) low noise amplifier (LNA) 240c in the secondary receiver (SRx) 236. In another configuration (not shown), the signal splitting stage 733 may take the signal input to the first low band (LB1) low noise amplifier (LNA) 240a in the primary receiver (PRx) 234 and route the signal to the transconductance stage (Gm) 244e of the first low band (LB1) low noise amplifier (LNA) 240c in the secondary receiver (SRx) 236. The signal splitting stage 733 is discussed in additional detail below in relation to
The routing 881 from the secondary antenna 308 through the secondary receiver (SRx) 336 to obtain the second SRx inphase/quadrature (I/Q) signal 320 is also shown. The second SRx inphase/quadrature (I/Q) signal 320 may include the other two carriers from the low band for this configuration. The routing 881 from the secondary antenna 308 through the secondary receiver (SRx) 336 to obtain the second SRx inphase/quadrature (I/Q) signal 320 may pass through a signal splitting stage 833. As discussed above, the signal splitting stage 833 may allow the secondary signal splitting carrier aggregation architecture 327 to reuse the diversity/simultaneous hybrid dual receiver (SHDR) receiver path. In another configuration (not shown), the signal splitting stage 833 may take the signal input to the first low band (LB1) low noise amplifier (LNA) 340a in the primary receiver (PRx) 334 and route the signal to the transconductance stage (Gm) 344e of the first low band (LB1) low noise amplifier (LNA) 340c in the secondary receiver (SRx) 336. The signal splitting stage 833 is discussed in additional detail below in relation to
The routing 943 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 is also shown. The first SRx inphase/quadrature (I/Q) signal 216 may include the midband carrier for this configuration. The routing 943 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 may pass through a signal splitting stage 933. The signal splitting stage 933 may take the signal from the first midband (MB1) low noise amplifier (LNA) 242a in the primary receiver (PRx) 234 after the transconductance stage (Gm) 244c and route the signal to the cascode stage (Cas) 246g of the first midband (MB1) low noise amplifier (LNA) 242c in the secondary receiver (SRx) 236. In another configuration (not shown), the signal splitting stage 933 may take the signal input to the first midband (MB1) low noise amplifier (LNA) 242a in the primary receiver (PRx) 234 and route the signal to the transconductance stage (Gm) 244g of the first midband (MB1) low noise amplifier (LNA) 242c in the secondary receiver (SRx) 236. The signal splitting stage 933 is discussed in additional detail below in relation to
The routing 1045 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 is also shown. The first SRx inphase/quadrature (I/Q) signal 216 may include the other low band carrier for this configuration. The routing 1045 from the primary antenna 206 through the secondary receiver (SRx) 236 to obtain the first SRx inphase/quadrature (I/Q) signal 216 may pass through a signal splitting stage 1033. The signal splitting stage 1033 may take the signal from the first low band (LB1) low noise amplifier (LNA) 240a in the primary receiver (PRx) 234 after the transconductance stage (Gm) 244a and route the signal to the cascode stage (Cas) 246e of the first low band (LB1) low noise amplifier (LNA) 240c in the secondary receiver (SRx) 236. In another configuration (not shown), the signal splitting stage 1033 may take the signal input to the first low band (LB1) low noise amplifier (LNA) 240a in the primary receiver (PRx) 234 and route the signal to the transconductance stage (Gm) 244e of the first low band (LB1) low noise amplifier (LNA) 240c in the secondary receiver (SRx) 236. The signal splitting stage 1033 is discussed in additional detail below in relation to
The outputs of the first transconductance stage (Gm) 1344a may be input to the first cascode stage (Cas) 1346a. The outputs of the first cascode stage (Cas) 1346a may then be mixed via the passive mixers 1348a-b to obtain the primary receiver (PRx) inphase signal PRx_I_CH 1360a-b and the primary receiver (PRx) quadrature signal PRx_Q_CH 1360c-d of a primary receiver (PRx) signal. In the signal splitting stage 1333, the signal splitting occurs after the first transconductance stage (Gm) 1344a. Thus, the outputs of the first transconductance stage (Gm) 1344a may be input to the inputs of the second cascode stage (Cas) 1346b. The outputs of the second cascode stage (Cas) 1346b may then be mixed via the passive mixers 1348c-d to obtain the secondary receiver (SRx) inphase signal SRx_I_CH 1360e-f and the secondary receiver (SRx) quadrature signal SRx_Q_CH 1360g-h of a secondary receiver (SRx) signal.
Switches may be used between the primary receiver (PRx) and the secondary receiver (SRx) to allow a clean standalone operation. The low noise amplifier (LNA) topology may drive the signal splitting sensing point.
The outputs of the upper first stage amplifier 1444 may be input to the upper second stage amplifier 1446. The outputs of the upper second stage amplifier 1446 may then be mixed via the passive mixers 1448a-b to obtain the primary receiver (PRx) inphase signal PRx_I_CH 1460a-b and the primary receiver (PRx) quadrature signal PRx_Q_CH 1460c-d of a primary receiver (PRx) signal. In the signal splitting stage 1433, the signal splitting occurs after the upper second stage amplifier 1446. Thus, the outputs of the upper second stage amplifier 1446 may be input to the passive mixers 1448c-d of the secondary receiver (SRx) to obtain the secondary receiver (SRx) inphase signal SRx_I_CH 1460e-f and the secondary receiver (SRx) quadrature signal SRx_Q_CH 1460g-h of a secondary receiver (SRx) signal.
The wireless communication device 2104 also includes memory 2105. The memory 2105 may be any electronic component capable of storing electronic information. The memory 2105 may be embodied as random access memory (RAM), read-only memory (ROM), magnetic disk storage media, optical storage media, flash memory devices in RAM, on-board memory included with the processor, EPROM memory, EEPROM memory, registers and so forth, including combinations thereof.
Data 2107a and instructions 2109a may be stored in the memory 2105. The instructions 2109a may be executable by the processor 2103 to implement the methods disclosed herein. Executing the instructions 2109a may involve the use of the data 2107a that is stored in the memory 2105. When the processor 2103 executes the instructions 2109, various portions of the instructions 2109b may be loaded onto the processor 2103, and various pieces of data 2107b may be loaded onto the processor 2103.
The wireless communication device 2104 may also include a transmitter 2111 and a receiver 2113 to allow transmission and reception of signals to and from the wireless communication device 2104 via a first antenna 2117a and a second antenna 2117b. The transmitter 2111 and receiver 2113 may be collectively referred to as a transceiver 2115. The wireless communication device 2104 may also include (not shown) multiple transmitters, additional antennas, multiple receivers and/or multiple transceivers.
The wireless communication device 2104 may include a digital signal processor (DSP) 2121. The wireless communication device 2104 may also include a communications interface 2123. The communications interface 2123 may allow a user to interact with the wireless communication device 2104.
The various components of the wireless communication device 2104 may be coupled together by one or more buses, which may include a power bus, a control signal bus, a status signal bus, a data bus, etc. For the sake of clarity, the various buses are illustrated in
The term “determining” encompasses a wide variety of actions and, therefore, “determining” can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, “determining” can include resolving, selecting, choosing, establishing and the like.
The phrase “based on” does not mean “based only on,” unless expressly specified otherwise. In other words, the phrase “based on” describes both “based only on” and “based at least on.”
The term “processor” should be interpreted broadly to encompass a general purpose processor, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a controller, a microcontroller, a state machine and so forth. Under some circumstances, a “processor” may refer to an application specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), etc. The term “processor” may refer to a combination of processing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The term “memory” should be interpreted broadly to encompass any electronic component capable of storing electronic information. The term memory may refer to various types of processor-readable media such as random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable PROM (EEPROM), flash memory, magnetic or optical data storage, registers, etc. Memory is said to be in electronic communication with a processor if the processor can read information from and/or write information to the memory. Memory that is integral to a processor is in electronic communication with the processor.
The terms “instructions” and “code” should be interpreted broadly to include any type of computer-readable statement(s). For example, the terms “instructions” and “code” may refer to one or more programs, routines, sub-routines, functions, procedures, etc. “Instructions” and “code” may comprise a single computer-readable statement or many computer-readable statements.
The functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions on a computer-readable medium. The terms “computer-readable medium” or “computer-program product” refers to any available medium that can be accessed by a computer. By way of example, and not limitation, a computer-readable medium may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
Software or instructions may also be transmitted over a transmission medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio and microwave are included in the definition of transmission medium.
The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is required for proper operation of the method that is being described, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein, such as those illustrated by
It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the systems, methods and apparatus described herein without departing from the scope of the claims.
This application is related to and claims priority from U.S. Provisional Patent Application Ser. No. 61/501,381 filed Jun. 27, 2011, for “CURRENT STEERING CARRIER AGGREGATION RECEIVER ARCHITECTURE.”
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