Patent Application
20130064252
This application is based upon and claims the benefit of priority from Japanese patent application No. 2011-200789, filed on Sep. 14, 2011, the disclosure of which is incorporated herein in its entirety by reference.
The present invention relates to a signal transmission/reception circuit including a signal transmission circuit and a signal reception circuit connected with each other by a plurality of signal lines, and in particular, to a signal transmission/reception circuit which transmits and receives data with the addition of error checking and correcting codes to the data.
A signal transmission/reception circuit which transmits and receives data, in which a signal transmission side transmits data with the addition of error checking and correcting codes to the data and a signal reception side checks and corrects errors in the received data using the error checking and correcting codes, has been known (for example, see JP 62-501047 A (Patent Document 1)).
On the other hand, in a video signal transmission device which performs serial transmission by multiplexing digital sound signals with video signals, a technique of adding an error checking and correcting code to each predetermined number of pieces of data of a digital sound signal and then reordering the bits, has been known (for example, see JP 5-219488 A (Patent-Document 2)). Specifically, the video signal transmission device disclosed in Patent Document 2 performs writing on a bit-by-bit basis serially into a memory of m×n cells in a row direction, and then performs reading by changing the direction to a column direction.
Patent Document 1: JP 62-501047 A
Patent Document 2: JP 5-219488 A
When data is transmitted between LSIs, the probability of occurrence of errors due to simultaneous switching noise is higher than the probability of soft errors. Simultaneous switching noise is noise generated in a power supply line when a plurality of drivers are switched simultaneously in the same logical direction (for example, in a direction from 0 to 1). When simultaneous switching noise is generated in a power supply line, errors may occur simultaneously in a plurality of signal lines which are receiving power supply from the power supply line. As such, as shown in the signal format of
Meanwhile, as disclosed in Patent Document 2, in the case of performing writing on a bit-by-bit basis serially into a memory of m×n cells in a line direction for a given number of code words, and then performing reading by changing the direction to a column direction, if “m” and “n” are set to be the same as the number of bits of a code word, the signal format as shown in
An exemplary object of the present invention is to provide a signal transmission/reception circuit capable of solving the above-described problem, that is, a problem that it is difficult to ensure error correction capability with respect to both simultaneous switching errors and multiple errors on a particular signal line.
A signal transmission and reception circuit, according to an exemplary aspect of the present invention, includes a signal transmission circuit and a signal reception circuit connected with each other by a first signal line group and a second signal line group.
The signal transmission circuit includes:
a code word generation section that generates a code word by adding an error checking and correcting code to an input word; and
a conversion section that divides a plurality of code words generated by the code word generation section into bit strings each including information bits having the number of bits which is the same as the number of bits of the word and code bits having the number of bits which is the same as the number of bits of the error checking and correcting code, and for each of the bit strings, outputs the information bits of the bit string to the first signal line group and outputs the code bits of the bit string to the second signal line group, wherein when dividing the code words into the bit strings, the conversion section divides the code words in such a manner as to satisfy a condition that a plurality of bits of the same code word are not output at the same time within the range of the first signal line group and the second signal line group or the range of a partial signal line group included in the first signal line group and the second signal line group, and that the respective bits of the error checking and correcting code of the same code word are output to different signal lines of the second signal line group, respectively, and
the signal reception circuit includes:
an inversion section that reorders the bit strings received from the first signal line group and the second signal line group to reproduce the code words in each of which the error checking and correcting code is added to the word; and
an error correction section that performs error correction of the word with use of the error checking and correcting code included in the code word reproduced by the inversion section, and outputs the word to the outside in the word unit.
Further, a signal transmission circuit, according to another exemplary aspect of the present invention, is a signal transmission circuit connected with a first signal line group and a second signal line group, including:
a code word generation section that generates a code word by adding an error checking and correcting code to an input word; and
a conversion section that divides a plurality of code words generated by the code word generation section into bit strings each including information bits having the number of bits which is the same as the number of bits of the word and code bits having the number of bits which is the same as the number of bits of the error checking and correcting code, and for each of the bit strings, outputs the information bits of the bit string to the first signal line group and outputs the code bits of the bit string to the second signal line group, wherein when dividing the code words into the bit strings, the conversion section divides the code words in such a manner as to satisfy a condition that a plurality of bits of the same code word are not output at the same time within the range of the first signal line group and the second signal line group or the range of a partial signal line group included in the first signal line group and the second signal line group, and that the respective bits of the error checking and correcting code of the same code word are output to different signal lines of the second signal line group, respectively.
Further, a signal reception circuit, according to another exemplary aspect of the present invention, is a signal reception circuit that receives bit strings transmitted from the signal transmission circuit according to the above-described aspect via a first signal line group and a second signal line group, including:
an inversion section that reorders the bit strings received from the first signal line group and the second signal line group to reproduce code words in each of which an error checking and correcting code is added to a word; and
an error correction section that performs error correction of the word with use of the error checking and correcting code included in the code word reproduced by the inversion section, and outputs the word to the outside in the word unit.
Further, a signal transmission and reception method, according to another exemplary aspect of the present invention, is a method implemented by a signal transmission and reception circuit including a signal transmission circuit and a signal reception circuit connected with each other by a first signal line group and a second signal line group, the signal transmission circuit including a code word generation section and a conversion section, the signal reception circuit including an inversion section and an error correction section. The method includes:
by the code word generation section, generating a code word by adding an error checking and correcting code to an input word;
by the conversion section, dividing a plurality of code words generated by the code word generation section into bit strings each including information bits having the number of bits which is the same as the number of bits of the word and code bits having the number of bits which is the same as the number of bits of the error checking and correcting code, and for each of the bit strings, outputting the information bits of the bit string to the first signal line group and outputting the code bits of the bit string to the second signal line group, the dividing the code words into the bit strings being performed in such a manner as to satisfy a condition that a plurality of bits of the same code word are not output at the same time within the range of the first signal line group and the second signal line group or the range of a partial signal line group included in the first signal line group and the second signal line group, and that the respective bits of an error checking and correcting code of the same code word are output to different signal lines of the second signal line group, respectively;
by the inversion section, reordering the bit strings received from the first signal line group and the second signal line group to reproduce the code words in each of which the error checking and correcting code is added to the word; and
by the error correction section, performing error correction of the word with use of the error checking and correcting code included in the code word reproduced by the inversion section, and outputs the word to the outside in the word unit.
As the present invention has the configuration described above, it is possible to ensure error correction capability with respect to both simultaneous switching errors and multiple errors which occur on a particular signal line.
Next, exemplary embodiments of the present invention will be described in detail with reference to the drawings.
Referring to
The signal transmission circuit 110 has a function of generating a code word by adding, to an input word, an ECC code for correcting an error in the word, and a function of dividing the generated code words into a plurality of bit strings of the same number of pieces and the same number of bits as those of the code words and transmitting them to the signal reception circuit 120 via the signal line group 130. In this step, the signal transmission circuit 110 outputs them in such a manner that a plurality of bits of the same code word are not output to a particular signal line group of the signal line group 130 in parallel at the same time, and that the respective bits of the ECC code of the same code word are output to different signal lines of the signal line group 132, respectively.
In this example, a particular signal line group means a group of signal lines in which the power source of the drive circuits, which drives the signal lines, is the same. Accordingly, in the case of a single power source, the entire signal line group 130 forms one particular signal line group. If the signal line group 131 and the signal line group 132 are respectively connected with drive circuits which are driven by different power sources, each of the signal line group 131 and the signal line group 132 forms one particular signal line group. Further, if the signal line group 131 includes a signal line group connected with drive circuits driven by one power source and a signal line group connected with drive circuits driven by another power source, the signal lines connected with the drive circuits driven by the same power source in the signal line group 131 form one particular signal line group. Generally, in an LSI (Large Scale Integration) and an FPGA (Field Programmable Gate Array), power-supply noise when signals are output is generated almost independently on a power supply basis which is determined by the power supply lines on the chip of the LSI/FPGA, that is, on a power bank basis. As such, there is no need to consider simultaneous switching noise between different power banks. However, this does not prevent such a consideration.
The signal transmission circuit 110 of the present embodiment includes a code word generation section 111 and a conversion section 112.
The code word generation section 111 has a function of generating a code word by adding an ECC code to an input word.
The conversion section 112 has a function of dividing a plurality of code words, generated by the code word generation section 111, into bit strings each including information bits having the same number of bits as that of a word and code bits having the same number of bits as that of an ECC code, and outputting them in units of bit strings to the signal line group 130. The conversion section 112 outputs the information bits of a bit string to the signal line group 131, and outputs the code bits of the bit string to the signal line group 132. Further, the conversion section 112 divides the code words into bits strings in such a manner as to satisfy a condition that a plurality of bits of the same code word (preferably, any 2 bits of the same code word) are not output at the same time within the range of the signal line group 130 or within the range of a partial signal line group constituting the signal line group 130, and that the respective bits of the ECC code of the same code word are output to different signal lines of the signal line group 132, respectively.
The signal reception circuit 120 has a function of receiving a plurality of bit strings from the signal transmission circuit 110 via the signal line group 130, and outputting them to the outside in units of original words. In the present embodiment, the signal reception circuit 120 includes an inversion section 121 and an error correction section 122.
The inversion section 121 has a function of reordering a plurality of bit strings received from the signal line group 130 to reproduce code words each including a word and an ECC code for correcting an error in the word.
The error correction section 122 has a function of performing error correction of a word with use of an ECC code included in a code word reproduced by the inversion section 121, and outputting the word to the outside in the word unit.
In the present embodiment, as an ECC code, a hamming code or an extended hamming code may be used. The required number of bits in that case is as follows:
Further, in the present embodiment, as an ECC code, a code enabling multiple bit correction (for example, BCH code) or a code enabling block correction (for example, Read-Solomon code) may be used.
Next, operation of the present embodiment will be described.
When words are serially input to the code word generation section 111 of the signal transmission circuit 110 from the outside, the code word generation section 111 generates code words in each of which an ECC code is added to an input word, and outputs them to the conversion section 112. The conversion section 112 divides the code words generated by the conversion section 112 into bit strings each including information bits having the same number of bits as that of the word and code bits having the same number of bits as that of the ECC code, and outputs them to the signal line group 130 in units of bit strings. In this step, the conversion section 112 outputs the information bits of a bit string to the signal line group 131, and outputs the code bits of the bit string to the signal line group 132. When dividing code words into bit strings, the conversion section 112 divides them in such a manner as to satisfy a condition that a plurality of bits of the same code word (preferably, any 2 bits of the same code word) are not output at the same time within the range of the signal line group 130 or within the range of a partial signal line group constituting the signal line group 130, and that the respective bits of the ECC code of the same code word are output to different signal lines of the signal line group 132, respectively.
On the other hand, the inversion section 121 of the signal reception circuit 120 reorders the bit strings received from the signal line group 130 to reproduce the original code words, and outputs them to the error correction section 122. The error correction section 122 performs error correction of each of the words with use of the ECC code included in the code word reproduced by the inversion section 121, and outputs the word to the outside in the word unit.
As described above, according to the signal transmission/reception circuit 100 of the present embodiment, it is possible to ensure error correction capability with respect to both simultaneous switching errors and multiple errors which occur on a particular signal line. This is because as a plurality of bits of the same code word are not output at the same time on a particular signal line group of the signal line group 130, that is, on a plurality of signal lines in which the drive circuits driving the signal lines use the same power source, even if simultaneous switching errors occur, the probability that errors occur in a plurality of bits of the same code word can be reduced. Further, as the respective bits of the ECC code of the same code word are not output to the same signal line, even if multiple errors occur on a particular signal line, the probability that errors occur in a plurality of bits of the ECC code of the same code word can be reduced.
Referring to
The code word generation section 211 inputs 4 bits constituting a word in synchronization with the clock, generates a 3-bit ECC code from the 4 bits by means of a well-known method, and outputs, to the conversion section 212, a code word constituted of a total of 7 bits including the 4 bits a1, a2, a3, and a4 constituting the input word and the 3 bits c1, c2, and c3 constituting the generated ECC code.
The conversion section 212 includes an FF array 213 having a plurality of cells. Each cell is formed of one flip flop. Hereinafter, it is defined that the horizontal direction of a sheet is a row, the vertical direction thereof is a column, and a cell in the ith row and the jth column is expressed as Ci,j. The FF array 213 is configured such that one cell C1,1 is arrayed in the 1st row, 2 cells C2,1 and C2,2 are arrayed in the 2nd row, the number of cells is incremented by 1 in each of the following rows, and 7 cells C7,1, C7,2, C7,3, C7,4, C7,5, C7,6 and C7,7 are arrayed in the 7th row which is the last row. The conversion section 212 receives respective bits of code words in synchronization with the clock. The respective bits of each code word, input to the conversion section 212, are input to the cells C1,1, C2,1, C3,1, C4,1, C5,1, C6,1, and C7,1 in the first column of the respective rows of the FF array 213. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells C1,1, C2,2, C3,3, C4,4, C5,5, C6,6, and C7,7 in the last column are output to the signal line groups 131 and 132. This means that the respective rows of the FF array 213 constitute shift registers having the different number of stages, respectively.
Next, operation of the signal transmission circuit 210 according to the present embodiment will be described.
The code word generation section 211 of the signal transmission circuit 210 inputs the words, input in the order as shown in
The conversion section 212 serially inputs the 7 bits of the code word, output from the code word generation section 211, to the FF array 213 in synchronization with the clock. Further, the conversion section 212 outputs a bit string, output from the FF array 213, to the signal line groups 131 and 132. In this step, the 4 bits output from the 1st to 4th rows of the FF array 213 (the respective bits are bits of different words) are output to the signal line 131, and the 3 bits output from the 5th to 7th rows (the respective bits are ECC code bits of different code words) are output to the signal line 132.
Referring to
It should be noted that in the present embodiment, as the parallelism of transmission is degraded substantially in the first 6 clocks after the start of communication and the last 6 clocks, the present embodiment is suitable for a device in which word signals flow constantly and continuously.
Referring to
The inversion section 311 includes an FF array 313 having a plurality of cells. Each cell is formed of one flip flop. The FF array 313 is configured such that 7 cells C1,1, C1,2, C1,3, C1,4, C1,5, C1,6 and C1,7 are arrayed in the 1st row, 6 cells C2,1, C2,2, C2,3, C2,4, C2,5, and C2,6 are arrayed in the 2nd row, the number of cells is decremented by 1 in each of the following rows, and one cell C1,1 is arrayed in the 7th row which is the last row. The inversion section 311 receives respective bits of code words in synchronization with the clock. The respective bits of the code words, input to the inversion section 311, are input to the cells C1,1, C2,1, C3,1, C4,1, C5,1, C6,1, and C7,1 in the first column of the respective rows of the FF array 313. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells C1,7, C2,6, C3,5, C4,4, C5,3, C6,2, and C7,1 in the last column are output to the error correction section 312 as one code word. This means that the respective rows of the FF array 313 constitute shift registers having the different number of stages, respectively.
The error correction section 312 performs error correction of a word using an ECC code included in a code word reproduced by the inversion section 311, and outputs the word to the outside in the word unit. Specifically, the error correction section 312 performs well-known calculation using a total of 7 bits, including the information bits and the ECC code of the input code word, to obtain a 3-bit syndrome, determines presence or absence of an error from the 3-bit syndrome, and if there is an error in any 1 bit of the 4-bit information bits, performs error correction using the 3-bit syndrome.
Next, operation of the signal reception circuit 310 according to the present embodiment will be described.
To the signal reception circuit 310, time series signals as shown in
Each time a new code word is input, the error correction section 312 performs error checking of the code word. Then, if detecting an error of 1 bit, the error correction section 312 corrects the error, and outputs the word in which the error has been corrected.
According to the present embodiment, it is possible to provide a signal reception circuit which can be used in combination with the signal transmission circuit of the second exemplary embodiment.
Referring to
The code word generation section 411 receives 4 bits constituting a word in synchronization with the clock, generates a 3-bit ECC code from the 4 bits, and outputs, to the conversion section 412, a code word constituted of a total of 7 bits including the 4 bits a1, a2, a3, and a4 constituting the input word and the 3 bits c1, c2, and c3 constituting the generated ECC code.
The conversion section 412 includes an FF array 413, a reordering section 414, and an FF array 415.
The FF array 413 includes 7 (=code word length)×7 (=code word length) cells. Each cell is formed of one flip flop. The conversion section 412 receives respective bits constituting code words from the code word generation section 411 in synchronization with the clock. The respective bits of each code word, input to the conversion section 412, are input to the cells C1,1, C2,1, C3,1, C4,1, C5,1, C6,1, and C7,1 in the first column of the FF array 413. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells C1,7, C2,7, C3,7, C4,7, C5,7, C6,7, and C7,7 in the last column are discarded. As such, each row of the FF array 413 constitutes a shift register. Further, the pieces of bit information stored in the cells of the FF array 413 can be read in parallel. In the present embodiment, every 7 clocks, a total of 49 (=code word length×code word length) bits are read from the entire cells by the reordering section 414.
The FF array 415 includes 7 (=code word length)×7 (=code word length) cells. Each cell is formed of one flip flop. To the cells of the FF array 415, bit information can be written in parallel. The pieces of bit information written in the respective cells of the FF array 415 may be shifted in the row direction. When the FF array 415 is shifted by one to the right, the pieces of bit information stored in the respective columns are moved to the cells in the next column, the information bits stored in the cells C1,7, C2,7, C3,7, and C4,7 in the last column are output to the signal line 131, and the code bits stored in the cells C5,7, C6,7, and C7,7 in the last column are output to the signal line 132.
The reordering section 414 reorders the 49 bits of the 7 code words read from the FF array 413, and stores them in the FF array 415. When reordering, the reordering section 414 reorders the bits in such a manner that a combination of any 2 bits of the same code word on the FF array 413 are neither a combination of bits to be stored in cells in the same row of the FF array 415 nor a combination of bits to be stored in cells in the same column of the FF array 415. Specifically, in the present embodiment, the reordering section 414 reorders the bits from an array A to an array B as shown in
Next, operation of the signal transmission circuit 410 according to the present embodiment will be described.
To the signal transmission circuit 410, time series signals as shown in
The conversion section 412 inputs code words, output from the code word generation section 411, to the FF array 413 in synchronization with the clock. Then, when 7 pieces of continuous code words are input to the FF array 413, a total of 49 bits, read from the FF array 413, are reordered by the reordering section 414, and are stored in the FF array 415. Then, the conversion section 412 applies a right shift to the FF array 415 in synchronization with the clock. Thereby, a bit string, output from the FF array 415, is output to the signal lines 131 and 132.
Further, in the present embodiment, the information bits of 7 words and the entire bits of the ECC codes for those words can be transmitted in the unit of 7×7 bits. As such, the present embodiment is particularly suitable for transmission of burst data.
Referring to
The inversion section 511 includes an FF array 513, a reordering section 514, and an FF array 515.
The FF array 513 includes 7 (=code word length)×7 (=code word length) pieces of cells. Each cell is formed of one flip flop. The inversion section 511 receives respective bits, constituting code words, from the signal line groups 131 and 132 in synchronization with the clock. The respective bits of the code words, input to the inversion section 511, are input to the cells C1,1, C2,1, C3,1, C4,1, C5,1, C6,1, and C7,1 in the first column of the respective rows of the FF array 513. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells C1,7, C2,7, C3,7, C4,7, C5,7, C6,7, and C7,7 in the last column are discarded. As such, each row of the FF array 513 constitutes a shift register. Further, the pieces of bit information stored in the cells of the FF array 513 can be read in parallel. In the present embodiment, every 7 clocks, a total of 49 (=code word length×code word length) bits are read from the entire cells by the reordering section 514.
The FF array 515 includes 7 (=code word length)×7 (=code word length) pieces of cells. Each cell is formed of one flip flop. To the cells of the FF array 515, bit information can be written in parallel. The pieces of bit information written in the respective cells of the FF array 515 may be shifted in the row direction. When the FF array 515 is shifted by one to the right, the pieces of bit information stored in the respective columns are moved to the cells in the next column, and a total of 7 bits stored in the cells C1,7, C2,7, C3,7, C4,7, C5,7, C6,7, and C7,7, in the last column are output to the error correction section 512 as one code word.
The reordering section 514 reorders the 49 bits read from the FF array 513, and stores them in the FF array 515. When reordering, the reordering section 514 reorders the bits in such a manner that the bits of the same code word on the FF array 513 are stored in cells in the same column of the FF array 515. Specifically, in the present embodiment, the reordering section 514 reorders the bits from the array B to the array A as shown in
The error correction section 512 performs error correction of a word using the ECC code included in the code word reproduced by the inversion section 511, and outputs the word to the outside in the word unit.
Next, operation of the signal reception circuit 510 according to the present embodiment will be described.
To the signal reception circuit 510, time series signals as shown in
Each time a new code word is input, the error correction section 512 performs error checking of the code word. Then, if detecting an error of 1 bit, the error correction section 512 corrects the error, and outputs the word in which the error has been corrected.
According to the present embodiment, it is possible to provide a signal reception circuit which can be used in combination with the signal transmission circuit of the fourth exemplary embodiment.
Referring to
The code word generation section 611 receives 4 bits constituting a word in synchronization with the clock, generates a 3-bit ECC code from the 4 bits by means of a well-known method, and outputs, to the conversion section 612, a code word constituted of a total of 7 bits including the 4 bits a1, a2, a3, and a4 constituting the input word and the 3 bits c1, c2, and c3 constituting the generated ECC code.
The conversion section 612 includes an FF array 613 associated with the signal line group 131-1, an FF array 614 associated with the signal line group 131-2, and an FF array 615 associated with the signal line group 132.
Each of the FF arrays 613 to 615 includes a plurality of cells. Each cell is formed of one flip flop. Each of the FF arrays 613 and 614 is configured such that one cell C1,1 is arrayed in the 1st row and 2 cells C2,1 and C2,2 are arrayed in the 2nd row. The FF array 615 is configured such that one cell C1,1 is arrayed in the 1st row, 2 cells C2,1 and C2,2 are arrayed in the 2nd row, and 3 cells C3,1, C3,2 and C3,3 are arrayed in the 3rd row. The conversion section 612 receives respective bits of code words in synchronization with the clock. The respective bits of each code word, input to the conversion section 612, are input to the cells in the first columns of the respective rows of the FF arrays 613 to 615. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells in the last columns are output to the signal line groups 131-1, 131-2, and 132. This means that the respective rows of the FF arrays 613 to 615 constitute shift registers having the different number of stages, respectively.
Next, operation of the signal transmission circuit 610 according to the present embodiment will be described.
The code word generation section 611 of the signal transmission circuit 610 receives the words input in the order as shown in
The conversion section 612 serially inputs the 7 bits of the code word, output from the code word generation section 611, to the FF arrays 613 to 615 in synchronization with the clock. Further, the conversion section 612 outputs a bit string, output from the FF arrays 613 to 615, to the signal line groups 131-1, 131-2, and 132. In this step, 2 bits output from the 1st and 2nd rows of the FF array 613 (the respective bits are bits of different words) are output to the signal line group 131-1, 2 bits output from the 1st and 2nd rows of the FF array 614 (the respective bits are bits of different words) are output to the signal line group 131-2, and 3 bits output from the 1st to 3rd rows of the FF array 615 (the respective bits are ECC code bits of different code words) are output to the signal line group 132.
It should be noted that in the present embodiment, as the parallelism of transmission is degraded substantially in the first 2 clocks after the start of communication and the last 2 clocks, the present embodiment is suitable for a device in which word signals flow constantly and continuously.
Referring to
The inversion section 711 includes an FF array 713 associated with the signal line group 131-1, an FF array 714 associated with the signal line group 131-2, and an FF array 715 associated with the signal line group 132.
Each of the FF arrays 713 to 715 includes a plurality of cells. Each cell is formed of one flip flop. Each of the FF arrays 713 and 714 is configured such that 3 cells C3,1, C3,2 and C3,3 are arrayed in the 1st row and 2 cells C2,1 and C2,2 are arrayed in the 2nd row. The FF array 715 is configured such that 3 cells C3,1, C3,2 and C3,3 are arrayed in the 1st row, 2 cells C2,1 and C2,2 are arrayed in the 2nd row, and one cell C1,1 is arrayed in the 3rd row. The inversion section 711 receives respective bits of code words from the signal line groups 131-1, 131-2, and 132 in synchronization with the clock. The respective bits of each code word, input to the inversion section 711, are input to the cells in the 1st columns of the respective rows of the FF arrays 713 to 715. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells in the last columns are output to the error correction section 712 as one code word. This means that the respective rows of the FF arrays 713 to 715 constitute shift registers having the different number of stages, respectively.
The error correction section 712 performs error correction of the word using the ECC code included in the code word input from the inversion section 711, and outputs the word to the outside in the word unit. Specifically, the error correction section 712 performs well-known calculation using a total of 7 bits including the information bits and the ECC code of the input code word to obtain a 3-bit syndrome, determines presence or absence of an error from the 3-bit syndrome, and if there is an error in any 1 bit of the 4-bit information bits, performs error correction using the 3-bit syndrome.
Next, operation of the signal reception circuit 710 according to the present embodiment will be described.
To the signal reception circuit 710, time series signals as shown in
Each time a new code word is input, the error correction section 712 performs error checking of the code word. Then, if detecting an error of 1 bit, the error correction section 712 corrects the error, and outputs the word in which the error has been corrected.
According to the present embodiment, it is possible to provide a signal reception circuit which can be used in combination with the signal transmission circuit of the sixth exemplary embodiment.
Referring to
The code word generation section 811 receives 4 bits constituting a word in synchronization with the clock, generates a 3-bit ECC code from the 4 bits, and outputs, to the conversion section 812, a code word constituted of a total of 7 bits including the 4 bits a1, a2, a3, and a4 constituting the input word and the 3 bits c1, c2, and c3 constituting the generated ECC code.
The conversion section 812 includes an FF array 813, a reordering section 814, and an FF array 815.
The FF array 813 is formed of three FF arrays 813-1 to 813-3. Each of the FF arrays 813-1 to 813-3 includes a plurality of cells. Each cell is formed of one flip flop. Each of the FF arrays 813-1 and 813-2 includes 2×5 cells. The FF array 813-3 includes 3×5 cells. The conversion section 812 receives respective bits constituting code words in synchronization with the clock. The respective bits of each code word, input to the conversion section 812, are input to the cells in the first columns of the respective rows of the FF arrays 813-1 to 813-3. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells in the last columns are discarded. As such, each row of the FF arrays 813-1 to 813-3 constitutes a shift register. Further, the pieces of bit information stored in the cells of the FF arrays 813-1 to 813-3 can be read in parallel. In the present embodiment, every 5 clocks, a total of 35 bits are read from the entire cells of the FF arrays 813-1 to 813-3 by the reordering section 814.
The FF array 815 is formed of three FF arrays 815-1 to 815-3. Each of the FF arrays 815-1 to 815-3 includes a plurality of cells. Each cell is formed of one flip flop. The FF arrays 815-1 is associated with the signal line group 131-1, and includes 2×5 cells. The FF arrays 815-2 is associated with the signal line group 131-2, and includes 2×5 cells. The FF array 815-3 is associated with the signal line group 132, and includes 3×5 cells. To the cells of each of the FF arrays 815-1 to 815-3, bit information can be written in parallel. The pieces of bit information written in the respective cells of the FF arrays 815-1 to 815-3 may be shifted in the row direction. When each of the FF arrays 815-1 to 815-3 is shifted by one to the right, the pieces of bit information stored in the respective columns are moved to the cells in the next column, and the information bits stored in the cells in the last columns are output to the signal line groups 131-1, 131-2, and 132.
For each of a set of the FF array 813-1 and the FF array 815-1, a set of the FF array 813-2 and the FF array 815-2, and a set of the FF array 813-3 and the FF array 815-3, the reordering section 814 reorders the bits read from the FF array 813, and stores them in the FF array 815. When reordering, the reordering section 814 reorders the bits in such a manner that a combination of any 2 bits of the same code word on the FF array 813 are neither a combination of bits to be stored in cells in the same row of the FF array 815 nor a combination of bits to be stored in cells in the same column or adjacent columns of the FF array 815. Specifically, in the present embodiment, the reordering section 414 reorders arrays A1 to A3 into arrays B1 to B3 as shown in
Next, operation of the signal transmission circuit 810 according to the present embodiment will be described.
To the signal transmission circuit 810, time series signals as shown in
The conversion section 812 inputs code words, output from the code word generation section 811, to the FF array 813 in synchronization with the clock. Then, when 5 pieces of continuous code words are input to the FF array 813, a total of 35 bits, read from the FF array 813, are reordered by the reordering section 814, and are stored in the FF array 815. Then, the conversion section 812 applies a right shift to the FF array 815 in synchronization with the clock. Thereby, a bit string, output from the FF array 815, is output to the signal lines 131-1, 131-2, and 132.
Further, in the present embodiment, for each power bank, the bits constituting the same code word are not output continuously but are output every other bit. As such, even if an error occurs in two continuing words due to huge simultaneous switching noise, as the respective bits belong to different code words, the error can be corrected. While in the present invention outputting is performed every other bit, it is needless to say that the effect can be enhanced with a coding format in which outputting is performed every two bits or every three bits.
Further, in the present embodiment, the information bits of 5 words and the entire bits of the ECC codes of those words can be transmitted in the unit of 5×7 bits. As such, the present embodiment is particularly suitable for transmission of burst data.
Referring to
The inversion section 911 includes an FF array 913, a reordering section 914, and an FF array 915.
The FF array 913 is formed of three FF arrays 913-1 to 913-3. Each of the FF arrays 913-1 to 913-3 includes a plurality of cells. Each cell is formed of one flip flop. The FF array 913-1 is associated with the signal line group 131-1, and includes 2×5 cells. The FF array 913-2 is associated with the signal line group 131-2, and includes 2×5 cells. The FF array 913-3 is associated with the signal line group 132, and includes 3×5 cells. The inversion section 911 receives respective bits constituting code words from the signal lines 131-1, 131-2, and 132 in synchronization with the clock. The respective bits of code words, input to the inversion section 911, are input to the cells in the first columns of the respective rows of the FF arrays 913-1 to 913-3. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells in the last columns are discarded. As such, each row of the FF arrays 913-1 to 913-3 constitutes a shift register. Further, the pieces of bit information stored in the cells of the FF arrays 913-1 to 913-3 can be read in parallel. In the present embodiment, every 5 clocks, a total of 35 bits are read from the entire cells of the FF arrays 913-1 to 913-3 by the reordering section 914.
The FF array 915 is formed of three FF arrays 915-1 to 915-3. Each of the FF arrays 915-1 to 915-3 includes a plurality of cells. Each cell is formed of one flip flop. Each of the FF arrays 915-1 and 915-2 includes 2×5 cells. The FF array 915-3 includes 3×5 cells. To the cells of each of the FF arrays 915-1 to 915-3, bit information can be written in parallel. The pieces of bit information written in the respective cells of the FF arrays 915-1 to 915-3 may be shifted in the row direction. When each of the FF arrays 915-1 to 915-3 is shifted by one to the right, the pieces of bit information stored in the respective columns are moved to the cells in the next column, and the information bits stored in the cells in the last columns are output to the error correction section 912 as one code word.
For each of a set of the FF array 913-1 and the FF array 915-1, a set of the FF array 913-2 and the FF array 915-2, and a set of the FF array 913-3 and the FF array 915-3, the reordering section 914 reorders the bits read from the FF array 913, and stores them in the FF array 915. When reordering, the reordering section 914 reorders the bits in such a manner that the bits in the same code word on the FF array 913 are stored in cells in the same column of the FF array 915. Specifically, in the present embodiment, the reordering section 514 reorders the arrays B1 to B3 into the arrays A1 to A3 as shown in
Next, operation of the signal reception circuit 910 according to the present embodiment will be described.
To the signal reception circuit 910, time series signals as shown in
Each time a new code word is input, the error correction section 912 performs error checking of the code word. Then, if detecting an error of 1 bit, the error correction section 912 corrects the error, and outputs the word in which the error has been corrected.
According to the present embodiment, it is possible to provide a signal reception circuit which can be used in combination with the signal transmission circuit of the eighth exemplary embodiment.
Referring to
The code word generation section 1011 receives 4 bits constituting a word in synchronization with the clock, generates a 3-bit ECC code from the 4 bits, and outputs, to the conversion section 1012, a code word constituted of a total of 7 bits including the 4 bits a1, a2, a3, and a4 constituting the input word and the 3 bits c1, c2, and c3 constituting the generated ECC code.
The conversion section 1012 includes an FF array 1013, a reordering section 1014, and an FF array 1015.
The FF array 1013 includes 7×4 pieces of cells. Each cell is formed of one flip flop. The conversion section 1012 receives respective bits constituting code words from the code word generation section 1011 in synchronization with the clock. The respective bits of each code word, input to the conversion section 1012, are input to the cells C1,1, C2,1, C3,1, C4,1, C5,1, C6,1, and C7,1 in the first column of the respective rows of the FF array 1013. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells C1,4, C2,4, C3,4, C4,4, C5,4, C6,4, and C7,4 in the last column are discarded. As such, each row of the FF array 1013 constitutes a shift register. Further, the pieces of bit information stored in the cells of the FF array 1013 can be read in parallel. In the present embodiment, every 4 clocks, a total of 28 bits are read from the entire cells by the reordering section 1014.
The FF array 1015 includes 7×4 pieces of cells. Each cell is formed of one flip flop. To the cells of the FF array 1015, bit information can be written in parallel. The pieces of bit information written in the respective cells of the FF array 1015 may be shifted in the row direction. When the FF array 1015 is shifted by one to the right, the pieces of bit information stored in the respective columns are moved to the cells in the next column, the information bits stored in the cells C1,4, C2,4, C3,4, and C4,4 in the last column are output to the signal line 131, and the code bits stored in the cells C5,4, C6,4, and C7,4, in the last column are output to the signal line 132.
The reordering section 1014 reorders the 28 bits of the 4 code words read from the FF array 1013, and stores them in the FF array 1015. When reordering, by each power bank, the reordering section 1014 reorders the bits in such a manner that a combination of any 2 bits in the same code word on the FF array 1013 are not a combination of bits to be stored in cells in the same column of the FF array 1015. Specifically, in the present embodiment, the reordering section 414 reorders an array A into an array B as shown in
Next, operation of the signal transmission circuit 1010 according to the present embodiment will be described.
To the signal transmission circuit 1010, time series signals as shown in
The conversion section 1012 inputs code words, output from the code word generation section 1011, to the FF array 1013 in synchronization with the clock. Then, when 4 pieces of continuous code words are input to the FF array 1013, a total of 28 bits, read from the FF array 1013, are reordered by the reordering section 1014, and are stored in the FF array 1015. Then, the conversion section 1012 applies a right shift to the FF array 1015 in synchronization with the clock. Thereby, a bit string, output from the FF array 1015, is output to the signal line groups 131 and 132.
Further, in the present embodiment, the bits output to the same signal line are mere 1 bit per code word. Accordingly, it is possible to ensure error correction capability with respect to multiple errors on a particular signal line.
Further, in the present embodiment, the information bits of 4 words and the entire bits of the ECC codes for those words can be transmitted in the unit of 28 bits. As such, the present embodiment is particularly suitable for transmission of burst data.
Referring to
The inversion section 1111 includes an FF array 1113, a reordering section 1114, and an FF array 1115.
The FF array 1113 includes 7×4 pieces of cells. Each cell is formed of one flip flop. The inversion section 1111 receives bit strings from the signal line groups 131 and 132 in synchronization with the clock. A bit string, input to the inversion section 1111, is input to the cells C1,1, C2,1, C3,1, C4,1, C5,1, C6,1, and C7,1 in the first column of the respective rows of the FF array 1113. In this step, the bit information stored in each cell is moved to a cell in the next column, and the pieces of bit information stored in the cells C1,4, C2,4, C3,4, C4,4, C5,4, C6,4, and C7,4 in the last column are discarded. As such, each row of the FF array 1113 constitutes a shift register. Further, the pieces of bit information stored in the cells of the FF array 1113 can be read in parallel. In the present embodiment, every 4 clocks, a total of 28 bits are read from the entire cells by the reordering section 1114.
The FF array 1115 includes 7×4 pieces of cells. Each cell is formed of one flip flop. To the cells of the FF array 1115, bit information can be written in parallel. The pieces of bit information written in the respective cells of the FF array 1115 may be shifted in the row direction. When the FF array 1115 is shifted by one to the right, the pieces of bit information stored in the respective columns are moved to the cells in the next column, and the bit string stored in the cells C1,4, C2,4, C3,4, C4,4, C5,4, C6,4, and C7,4, in the last column are output to the error correction section 1112 as one code word.
The reordering section 1114 reorders the 28 bits of the 4 code words read from the FF array 1113, and stores them in the FF array 1115. When reordering, the reordering section 1114 reorders the bits in such a manner that the bits of the same code word on the FF array 1113 are stored in cells in the same column of the FF array 1115. Specifically, in the present embodiment, the reordering section 1114 reorders the array B into the array A as shown in
Next, operation of the signal reception circuit 1110 according to the present embodiment will be described.
To the signal reception circuit 1110, time series signals as shown in
Each time a new code word is input, the error correction section 1112 performs error checking of the code word. Then, if detecting an error of 1 bit, the error correction section 1112 corrects the error, and outputs the word in which the error has been corrected.
According to the present embodiment, it is possible to provide a signal reception circuit which can be used in combination with the signal transmission circuit of the tenth exemplary embodiment.
Referring to
The signal transmission-side LSI 1210 includes a digital logic section 1211 and a signal transmission section 1212. The signal reception-side LSI 1220 includes a digital logic section 1221 and a signal reception section 1222. Each of the digital logic sections 1211 and 1221 is formed of an MPU (Micro-Processing Unit) or the like. When the digital logic section 1211 transmits data to the digital logic section 1221, the digital logic section 1211 outputs data in word units to the signal transmission section 1212.
The signal transmission section 1212 has a function of serially receiving a plurality of words from the digital logic section 1211, from the words, generating a plurality of code words each formed of information bits, having the same number of bits as those of the word, and an ECC code, and transmitting them to the signal reception circuit 1220 via the signal line groups 1230 and 1240. The signal transmission section 1212 may be formed of the signal transmission circuit according to the first, second, fourth, sixth, eighth, or the tenth exemplary embodiment described above.
The signal reception section 1222 has a function of receiving a plurality of code words from the signal transmission circuit 1210 via the signal line groups 1230 and 1240, and for each of the received code words, performing error correction of the information bits using the ECC code, and outputting the data constituted of the information bits in which the errors have been corrected to the digital logic section 1221 in word units. The signal reception section 1222 may be formed of the signal reception circuit according to the first, third, fifth, seventh, ninth, and eleventh exemplary embodiment described above.
Referring to
The signal transmission section 1350 has a function of serially receiving a plurality of words from the digital logic section 1330, generating, from the words, a plurality of code words each formed of information bits, having the same number of bits as those of the word, and an ECC code, and transmitting them to the DDR controller 1340 via signal line groups 1371 and 1381. The signal transmission section 1350 may be formed of the signal transmission circuit according to the first, second, fourth, sixth, eighth, or the tenth exemplary embodiment described above.
The signal reception section 1360 has a function of receiving a plurality of code words from the DDR controller 1340 via signal line groups 1372 and 1382, and for each of the received code words, performing error correction of the information bits using the ECC code, and outputting the data constituted of the information bits in which the errors have been corrected to the digital logic section 1330 in word units. The signal reception section 1360 may be formed of the signal reception circuit according to the first, third, fifth, seventh, ninth, and eleventh exemplary embodiment described above.
While the present invention has been described with reference to the exemplary embodiments, the present invention is not limited to these exemplary embodiments, and various additions and changes may be made therein. Further, in order to simplify the description, while the respective exemplary embodiments have been described based on an example of adding a 3-bit ECC code to a 4-bit word, the number of bits of a word is not limited to 4 bits. Any number of bits, including 8 bits, 16 bits, 32 bits, and 64 bits may be acceptable. Further, an ECC code may also have any number of bits, according to the number of bits of the word and the error checking and correcting capability.
The present invention is applicable to the overall field of transmitting and receiving signals in parallel data by adding ECC codes, between LSIs, between an LSI and a RAM, or the like.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-200789 | Sep 2011 | JP | national |
