Patent Application
20250240017
The present disclosure relates to a signal transmitting apparatus.
A signal transmitting apparatus is provided which transmits an output signal based on an input signal from an output terminal.
An embodiment of the present disclosure will be specifically described below with reference to drawings. In the referenced drawings, the same parts are identified with the same reference symbols, and the repeated description of the same parts is omitted in principle. In the present specification, for simplification of description, a sign or a symbol indicating information, a signal, a physical quantity, a functional unit, a circuit, an element, a part or the like is written, and thus the name of the information, the signal, the physical quantity, the functional unit, the circuit, the element, the part or the like corresponding to the sign or the symbol may be omitted or written in short. For example, although a bus connection terminal BUS which will be described later and is represented by “BUS” (see
A description will first be given of some terms used in the description of the embodiment of the present disclosure. Lines refer to wiring through which electrical signals are propagated or applied. A ground refers to a reference conductive portion having a potential of 0 V (zero volt) as a reference or refers to a potential of 0 V itself. The reference conductive portion may be formed of a conductor such as metal. A potential of 0 V may also be referred to as a ground potential. In the embodiment of the present disclosure, a voltage shown without provision of a specific reference indicates a potential relative to the ground.
A level refers to the level of a potential, and a high level has a higher potential than a low level for any signal or voltage of interest. For any signal or voltage of interest, that the signal or voltage is at a high level strictly means that the level of the signal or voltage is at a high level, and that the signal or voltage is at a low level strictly means that the level of the signal or voltage is at a low level. The level of a signal may be referred to as a signal level, and the level of a voltage may be referred to as a voltage level.
In any signal or voltage of interest, a switch from a low level to a high level is referred to as an up edge. A timing at which the up edge occurs is referred to as an up edge timing. The up edge may be replaced by a rising edge. In any signal or voltage of interest, a switch from a high level to a low level is referred to as a down edge. A timing at which the down edge occurs is referred to as a down edge timing. The down edge may be replaced by a falling edge.
For any transistor configured as an FET (field-effect transistor) including a MOSFET, an on state refers to a state where the drain and the source of the transistor are conductive, and an off state refers to a state (blocked state) where the drain and the source of the transistor are nonconductive. The same is true for transistors which are not classified as FETs. Unless otherwise specified, the MOSFET is understood to be an enhancement type MOSFET. The MOSFET is an abbreviation for “metal-oxide-semiconductor field-effect transistor”. Unless otherwise specified, in any MOSFET, a back gate may be considered to be shorted to the source.
For any signal which has a high or low signal level, a period during which the signal level is high is referred to as a high level period, and a period during which the signal level is low is referred to as a low level period. The same is true for any voltage which has a high or low voltage level.
Unless otherwise specified, connection between a plurality of parts, such as a circuit element, wiring (line), and a node, which form a circuit is understood to refer to electrical connection.
A power supply voltage VDD is supplied from an unillustrated voltage source to the power supply terminal VIN. The power supply voltage VDD has a predetermined positive direct-current voltage value. The transceiver 10 is driven based on the power supply voltage VDD. The ground terminal GND is connected to the ground. The bus connection terminal BUS is connected to one end of the bus line 51, and the other end of the bus line 51 is connected to the other side device 30. In other words, the bus connection terminal BUS is connected to the other side device 30 via the bus line 51. The other side device 30 also includes a terminal which receives the power supply voltage VDD and a terminal which is connected to the ground and is driven based on the power supply voltage VDD.
The bus line 51 is connected to the application end 50 of the power supply voltage VDD via the pull-up resistor 52 and the backcurrent prevention diode 53. The application end 50 is a terminal to which the power supply voltage VDD is applied. The backcurrent prevention diode 53 has a forward direction from the application end 50 toward the bus line 51 and the bus connection terminal BUS. The backcurrent prevention diode 53 blocks the flow of current from the bus line 51 to the application end 50. More specifically, the anode of the backcurrent prevention diode 53 is connected to the application end 50, the cathode of the backcurrent prevention diode 53 is connected to one end of the pull-up resistor 52 and the other end of the pull-up resistor 52 is connected to the bus line 51.
However, the positions of the pull-up resistor 52 and the backcurrent prevention diode 53 can be reversed from those shown in
The capacitor 54 is connected between the bus line 51 and the ground. In other words, one end of the capacitor 54 is connected to the bus line 51, and the other end of the capacitor 54 is connected to the ground. The capacitor 54 may be formed with a plurality of capacitors separated from each other. The capacitor 54 may be omitted.
The reception data output terminal RXD is connected to one end of the data line 61, and the other end of the data line 61 is connected to the microcomputer 20. The transmission data input terminal TXD is connected to one end of the data line 62, and the other end of the data line 62 is connected to the microcomputer 20. In other words, the terminals RXD and TXD are connected to the microcomputer 20 via the data lines 61 and 62. The data line 61 is connected to the application end of a power supply voltage VCC via the pull-up resistor 63. The power supply voltage VCC has a predetermined positive direct-current voltage value. It does not matter whether the power supply voltages VCC and VDD match. The microcomputer 20 includes a terminal which receives the power supply voltage VCC and a terminal which is connected to the ground and is driven based on the power supply voltage VCC.
The transceiver 10 includes a reception circuit RX and a transmission circuit TX. The reception circuit RX is connected to the reception data output terminal RXD and the bus connection terminal BUS. The transmission circuit TX is connected to the transmission data input terminal TXD and the bus connection terminal BUS.
The transceiver 10 and the other side device 30 perform bidirectional communication with a half-duplex system via the bus line 51. The bidirectional communication which is assumed in the present embodiment is serial communication (that is, serial communication using the bus line 51 which is one wire) using a single wire system. In the bidirectional communication of the half-duplex system, the transceiver 10 may function as a master, and the other side device 30 may function as a slave, or the other side device 30 may function as a master, and the transceiver 10 may function as a slave. The bidirectional communication between the transceiver 10 and the other side device 30 may be, for example, bidirectional communication which conforms to a LIN (Local Interconnect Network) standard or a CXPI (Clock Extension Peripheral Interface) standard.
In the bidirectional communication of the half-duplex system, one of the transceiver 10 and the other side device 30 is operated as a transmission-side device, and the other is operated as a reception-side device.
When the transceiver 10 functions as the reception-side device, the other side device 30 transmits a signal (hereinafter referred to as the signal SR) via the bus line 51, and the reception circuit RX receives, at the bus connection terminal BUS, the signal SR transmitted from the other side device 30. The reception circuit RX transmits the received signal SR from the terminal RXD via the data line 61 to the microcomputer 20. When the transceiver 10 functions as the reception-side device, the bus connection terminal BUS functions as an input terminal (signal reception terminal) which receives a signal transmitted from the other side device 30.
When the transceiver 10 functions as the transmission-side device, the microcomputer 20 transmits a signal (hereinafter referred to as the signal ST) to the transceiver 10 via the data line 62. The signal ST transmitted from the microcomputer 20 is received by the terminal TXD. When the transceiver 10 functions as the transmission-side device, the transmission circuit TX transmits the signal ST received from the microcomputer 20 to the other side device 30 via the bus line 51. The other side device 30 may be formed with a group of a transceiver and a microcomputer equivalent to the transceiver 10 and the microcomputer 20, and in this case, the signal ST received from the transceiver 10 is transmitted from the transceiver in the other side device 30 to the microcomputer in the other side device 30. When the transceiver 10 functions as the transmission-side device, the bus connection terminal BUS functions as an output terminal (signal transmission terminal) at which the signal to be transmitted from the transceiver 10 appears.
The transmission of a signal via the bus line 51 is realized by controlling the level of the bus line 51 such that the level of the bus line 51 is high or low. The level of the bus line 51 is the same as the level of the bus connection terminal BUS. The level of the bus line 51 is equal to or greater than 0 V and equal or less than the power supply voltage VDD. When the bus line 51 has a level which is equal to or greater than a voltage (VDD×kH), the level of the bus line 51 is high, and when the bus line 51 has a level which is equal to or less than a voltage (VDD×kL), the level of the bus line 51 is low. Here, “1>kH>0.5>kL>0” holds true, and for example, (kH, kL)=(0.7, 0.3). The voltages of the bus line 51 and the bus connection terminal BUS are represented by a symbol “VBUS”.
Unless otherwise specified, the operation and the configuration when the transceiver 10 functions as the transmission-side device will be described below. For the transmission circuit TX, the voltage VBUS corresponds to an output voltage (the output voltage of the transmission circuit TX). Hence, the voltage VBUS when attention is focused on the configuration and the operation of the transmission circuit TX can be referred to as the output voltage in the following description. A signal indicated by the output voltage VBUS can be referred to as the output signal. When the level of the bus line 51 is caused to transition between a high level and a low level in the transmission of a signal via the bus line 51, the transmission circuit TX in the transceiver 10 has the function of controlling the slew rate of the output voltage VBUS to reduce radiation noise.
The output transistor 111 is an N-channel MOSFET. The output transistor 111 is provided between the bus connection terminal BUS which functions as the output terminal and the ground, and the transmission circuit TX uses the output transistor 111 of an open drain configuration to transmit a signal. However, the backcurrent prevention diode 113 for blocking the flow of current from the ground to the bus line 51 via the output transistor 111 and the bus connection terminal BUS is provided between the output transistor 111 and the bus connection terminal BUS. Specifically, the drain of the output transistor 111 is connected to the cathode of the backcurrent prevention diode 113, and the anode of the backcurrent prevention diode 113 is connected to the bus connection terminal BUS. The source of the output transistor 111 is connected to the ground. The gate voltage of the output transistor 111 (that is, the voltage applied to the gate of the output transistor 111) is represented by a symbol “VG”. The gate threshold voltage of the output transistor 111 is represented by a symbol “VG_TH”. The gate threshold voltage VG_TH has a positive voltage value which depends on the characteristic of the output transistor 111. When the gate voltage VG of the output transistor 111 is less than the gate threshold voltage VG_TH, the output transistor 111 is in an off state, and when the gate voltage VG of the output transistor 111 is equal to or greater than the gate threshold voltage VG_TH, the output transistor 111 is in an on state.
A variation in which the backcurrent prevention diode 113 is not provided in the transmission circuit TX can be adopted, and when the variation is adopted, the drain of the output transistor 111 is directly connected to the bus connection terminal BUS.
The capacitor 112 is connected between the gate of the output transistor 111 and the bus connection terminal BUS. Specifically, one end of the capacitor 112 is connected to the gate of the output transistor 111, and the other end of the capacitor 112 is connected to the bus connection terminal BUS.
The charge-discharge circuit 120 charges or discharges the gate of the output transistor 111 according to a control input signal SIN. The charge-discharge circuit 120 charges the gate of the output transistor 111 to be able to control the output transistor 111 such that the output transistor 111 is in an on state and discharges the gate of the output transistor 111 to be able to control the output transistor 111 such that the output transistor 111 is in an off state. The control input signal SIN is a binary signal which has a high level or a low level. The control input signal SIN of a high level substantially has the potential of an internal power supply voltage VREG, and the control input signal SIN of a low level substantially has a ground potential. By a regulator (not shown) in the transceiver 10, the internal power supply voltage VREG which is a positive direct-current voltage is generated from the power supply voltage VDD. The charge-discharge circuit 120 includes a charging circuit 121 and a discharging circuit 122.
The charging circuit 121 supplies a charge current to the gate of the output transistor 111 during a period in which the control input signal SIN is high to increase the gate voltage VG of the output transistor 111. However, the gate voltage VG has an upper limit, and thus the gate voltage VG is prevented from being increased beyond an upper limit voltage. The upper limit voltage of the gate voltage VG is the internal power supply voltage VREG or a predetermined voltage which is lower than the internal power supply voltage VREG. The upper limit voltage of the gate voltage VG is higher than the gate threshold voltage VG_TH of the output transistor 111. In a process in which the gate voltage VG is increased from a sufficiently low voltage (for example, 0 V), when the gate voltage VG reaches the gate threshold voltage VG_TH, the output transistor 111 is switched from an off state to an on state. Specifically, in the process in which the gate voltage VG is increased from the sufficiently low voltage (for example, 0 V), when the gate voltage VG becomes equal to or greater than the gate threshold voltage VG_TH, the resistance value of the channel of the output transistor 111 is sharply decreased, and thus the resistance value of the channel of the output transistor 111 is sufficiently lower than the resistance value of the pull-up resistor 52, with the result that the voltage VBUS is substantially decreased to 0 V. The resistance value of the channel of the output transistor 111 refers to a resistance value between the drain and the source of the output transistor 111.
The discharging circuit 122 draws a discharge current from the gate of the output transistor 111 during a period in which the control input signal SIN is low to decrease the gate voltage VG of the output transistor 111. However, the gate voltage VG has a lower limit, and thus the gate voltage VG is prevented from being decreased below a lower limit voltage. The lower limit voltage of the gate voltage VG is 0 V. In a process in which the gate voltage VG is decreased from a voltage higher than the gate threshold voltage VG_TH, when the gate voltage VG is decreased below the gate threshold voltage VG_TH, the output transistor 111 is switched from an on state to an off state. Specifically, in the process in which the gate voltage VG is decreased from the voltage higher than the gate threshold voltage VG_TH, when the gate voltage VG becomes less than the gate threshold voltage VG_TH, the resistance value of the channel of the output transistor 111 is sharply increased, and thus the resistance value of the channel of the output transistor 111 is sufficiently increased beyond the resistance value of the pull-up resistor 52, with the result that the output voltage VBUS is increased to around the power supply voltage VDD.
In the configuration example of
During the period in which the control input signal SIN is high, the switch 121b is on whereas the switch 122b is off. Hence, during the period in which the control input signal SIN is high, the current IC (hereinafter referred to as the charge current IC) for increasing the gate voltage VG is supplied from the charge current source 121a to the gate of the output transistor 111 via the switch 121b and the node 123. During the period in which the control input signal SIN is low, the exchange of charge between the gate of the output transistor 111 and the charging circuit 121 is not performed.
During the period in which the control input signal SIN is low, the switch 121b is off whereas the switch 122b is on. Hence, during the period in which the control input signal SIN is low, the current ID (hereinafter referred to as the discharge current ID) for lowing the gate voltage VG is drawn from the gate of the output transistor 111 to the discharge current source 122a via the node 123 and the switch 122b. During the period in which the control input signal SIN is high, the exchange of charge between the gate of the output transistor 111 and the discharging circuit 122 is not performed.
The control input signal supply circuit 130 generates the control input signal SIN based on the signal ST received from the microcomputer 20 and supplies the control input signal SIN to the charge-discharge circuit 120. The control input signal supply circuit 130 generates the control input signal SIN through waveform shaping of the signal ST or the like.
As long as the charge current IC can be supplied to the gate of the output transistor 111 during the period in which the control input signal SIN is high, the configuration of the charging circuit 121 is not limited. During the period in which the control input signal SIN is low, the charging circuit 121 may stop the generation of the charge current IC. In any case, during the period in which the control input signal SIN is low, the charge current IC flowing from the charging circuit 121 to the gate of the output transistor 111 is zero. Likewise, as long as the discharge current ID can be drawn from the gate of the output transistor 111 during the period in which the control input signal SIN is low, the configuration of the discharging circuit 122 is not limited. During the period in which the control input signal SIN is high, the discharging circuit 122 may stop the generation of the discharge current ID. In any case, during the period in which the control input signal SIN is high, the discharge current ID flowing from the gate of the output transistor 111 to the discharging circuit 122 is zero.
The gate voltage restriction circuit 140 is connected to the gate of the output transistor 111 and the ground. The gate voltage restriction circuit 140 includes two diodes 141 and 142. The anode of the diode 141 is connected to the gate of the output transistor 111, the cathode of the diode 141 is connected to the anode of the diode 142 and the cathode of the diode 142 is connected to the ground. The gate voltage restriction circuit 140 has the function of suppressing an event in which the gate voltage VG is equal to or greater than a predetermined restriction voltage VLIM, and as long as the gate voltage restriction circuit 140 has the function, the gate voltage restriction circuit 140 is not limited. The restriction voltage VLIM here is higher than the gate threshold voltage VG_TH, and in the configuration example of
In a process in which the gate voltage VG is increased based on the charge current IC to switch the output transistor 111 from an off state to an on state, the output voltage VBUS is decreased, and the decrease in the output voltage VBUS is fed back to the gate of the output transistor 111 via the capacitor 112. By contrast, in a process in which the gate voltage VG is decreased based on the discharge current ID to switch the output transistor 111 from an on state to an off state, the output voltage VBUS is increased, and the increase in the output voltage VBUS is fed back to the gate of the output transistor 111 via the capacitor 112. Hence, for the charge-discharge circuit 120, the capacitance value of the capacitor 112 appears equivalently larger than the actual capacitance value of the capacitor 112 due to the mirror effect. In other words, the capacitor 112 functions as a mirror capacitance.
As shown in
The adjustment circuit 131 generates and outputs the control input signal SIN based on the original input signal SORG. Here, the adjustment circuit 131 adjusts the low level range of the control input signal SIN according to the power supply voltage VDD. In any signal or voltage of interest, the length of the low level period and the length of the high level period of the signal or voltage of interest are referred to as the low level range and the high level range, respectively. Hence, for example, the low level range of the control input signal SIN indicates the length of the low level period of the control input signal SIN, and the high level range of the output voltage VBUS indicates the length of the high level period of the output voltage VBUS.
As shown in
The slew rate of the output voltage VBUS includes an up slew rate which is a slew rate when the output voltage VBUS is increased, and a down slew rate which is a slew rate when the output voltage VBUS is decreased. The up slew rate refers to the maximum value or the average value of the rate of change of the output voltage VBUS when the output voltage VBUS is increased. The down slew rate refers to the maximum value or the average value of the rate of change of the output voltage VBUS when the output voltage VBUS is decreased. In the following description, the up slew rate and the down slew rate are collectively referred to as the output slew rate. In the following description, the output slew rate is understood to refer to one of the up slew rate and the down slew rate or to refer to both the up slew rate and the down slew rate.
Although a decrease in the output slew rate contributes to a reduction in radiation noise, the transceiver 10 which is operated as the transmission-side device needs to satisfy the following output signal condition. The output signal condition here may be, for example, a condition which is defined in the LIN standard or the CXPI standard.
The output signal condition which needs to be satisfied by the transceiver 10 will be described with reference to
When the down edge occurs in the original input signal SORG at the time point t1, a down edge also occurs in the control input signal SIN, and thus the discharge current ID starts to be drawn from the gate of the output transistor 111. When the gate voltage VG is decreased to the gate threshold voltage VG_TH by the discharge current ID, based on an increase in the resistance value of the channel of the output transistor 111, the output voltage VBUS starts to be increased from 0 V or a voltage close to 0 V. Thereafter, at the time point t2, the output voltage VBUS reaches a voltage (VDD×kREF). The voltage (VDD×kREF) is the kREF times the power supply voltage VDD. Here, kREF has a positive predetermined value which is determined by a standard (for example, the LIN standard or the CXPI standard) applied to the communication system 1 and is less than 1, and kREF may be the same as the coefficient kH described previously. Here, it is assumed that “kREF=kH=0.7”. The output voltage VBUS is increased after the time point t2.
Then, at the time point t3, the up edge occurs in the original input signal SORG. When the up edge occurs in the original input signal SORG at the time point t3, an up edge also occurs in the control input signal SIN, and thus the discharging of the gate of the output transistor 111 is stopped, and instead, the gate of the output transistor 111 starts to be charged. When the gate voltage VG is increased to the gate threshold voltage VG_TH by the charge current IC, based on a decrease in the resistance value of the channel of the output transistor 111, the output voltage VBUS starts to be decreased from a voltage exceeding the voltage (VDD×kREF). Thereafter, at the time point t4, the output voltage VBUS is decreased to the voltage (VDD×kREF). The output voltage VBUS is decreased after the time point t4.
A length between the time point t2 and the time point t4 is represented by a time TB (a time period TB). The time TB corresponds to the high level range of the output voltage VBUS. The output signal condition is that the ratio of the time TB to the time TA, that is, the ratio (TB/TA) is equal to or greater than a predetermined threshold value RTH. When “TB/TA≥RTH”, the output signal condition is satisfied, and when “TB/TA<RTH”, the output signal condition is not satisfied. The threshold value RTH has a positive predetermined value which is determined by a standard (for example, the LIN standard or the CXPI standard) applied to the communication system 1 and is less than 1, and for example, “RTH=0.8”.
The forward voltage of the backcurrent prevention diode 53 is represented by a symbol “Vf”. During the period in which the original input signal SORG is low, the output voltage VBUS is not increased beyond a voltage (VDD−Vf).
On the other hand, in the communication system 1, the power supply voltage VDD has a voltage within a power supply voltage range from a minimum voltage VDDMIN to a maximum voltage VDDMAX. The minimum voltage VDDMIN and the maximum voltage VDDMAX have a positive predetermined voltage value which satisfies “0<VDDMIN<VDDMAX”. As long as the power supply voltage VDD is within the power supply voltage range, it is required that the output signal condition is constantly satisfied. If the output slew rate is constantly set large enough, the output signal condition is easily satisfied, but an increase in the output slew rate causes an increase in radiation noise.
Hence, in order to satisfy the output signal condition in the entire power supply voltage range while minimizing radiation noise, in the transceiver 10, the output slew rate is set according to the power supply voltage VDD. The up slew rate depends on the charge current IC, and the down slew rate depends on the discharge current ID. Hence, the charge-discharge circuit 120 sets, according to the power supply voltage VDD, the values of the charge current IC and the discharge current ID such that they are variable, and thereby sets, according to the power supply voltage VDD, the output slew rate such that the output slew rate is variable. Specifically, the charging circuit 121 increases the charge current IC as the power supply voltage VDD is increased, and the discharging circuit 122 increases the discharge current ID as the power supply voltage VDD is increased. Typically, for example, as shown in
A relationship between the output voltage VBUS and the power supply voltage VDD will be described with reference to
Here, the effect of the backcurrent prevention diode 53 on an output signal waveform (that is, the waveform of the output voltage VBUS) will be described.
A description will be further given using specific numerical examples. As described above, here, it is assumed that “KREF=0.7”. It is further assumed that (VDDMAX, VDDMIN, Vf)=(27 V, 5 V, 0.7 V).
In a case where “VDD=VDDMAX”, “(VDDMAX−Vf)=26.3 V”, “VDD×kREF=VDDMAX×0.7=18.9 V” and “18.9/26.3≈0.719”. Hence, in a case where “VDD=VDDMAX”, in the reference method, the output voltage VBUS needs to be increased from 0 V by about 0.719 times the voltage (VDD−Vf) so that the output voltage VBUS reaches the voltage (VDD×kREF) after down edges occur in the original input signal SORG and the control input signal SIN. In a case where “VDD=VDDMIN”, “(VDDMIN−Vf)=4.3 V”, “VDD×kREF=VDDMIN×0.7=3.5 V” and “3.5/4.3≈0.814”. Hence, in a case where “VDD=VDDMIN”, in the reference method, the output voltage VBUS needs to be increased from 0 V by about 0.814 times the voltage (VDD−Vf) so that the output voltage VBUS reaches the voltage (VDD×kREF) after down edges occur in the original input signal SORG and the control input signal SIN.
In the reference method, a time necessary to increase the output voltage VBUS by about 0.814 times the voltage (VDD−Vf) is longer than a time necessary to increase the output voltage VBUS by about 0.719 times the voltage (VDD−Vf). Consequently, in the reference method, “TB_MAX>TB_MIN”. This means that, for example, if it is assumed that the original input signal SORG is a periodic rectangular wave signal, the H duty of the output voltage VBUS is changed depending on the power supply voltage VDD. When the original input signal SORG is a periodic rectangular wave signal, the output voltage VBUS is also periodic, and the H duty of the output voltage VBUS indicates the ratio of the high level range of the output voltage VBUS which occupies one period of the output voltage VBUS.
It is not desirable that the high level range of the output voltage VBUS be changed depending on the power supply voltage VDD. It is often required to suppress the amount of change in the high level range of the output voltage VBUS relative to a change in the power supply voltage VDD to a predetermined amount or less. An improvement method for meeting this requirement is applied to the transceiver 10.
The improvement method will be described with reference to
By the adjustment described above, for the power supply voltage VDD, the low level range of the control input signal SIN is caused to differ from the low level range of the original input signal SORG. This corresponds to causing the duty of the control input signal SIN to differ from the duty of the original input signal SORG according to the power supply voltage VDD when the original input signal SORG is a periodic signal.
Specifically, during the period in which the original input signal SORG is high, the adjustment circuit 131 sets the level of the control input signal SIN to a high level constantly (hence, without depending on the power supply voltage VDD). While the adjustment circuit 131 causes a down edge to occur in the control input signal SIN when a down edge occurs in the original input signal SORG, that is, during a period after the timing of the down edge of the original input signal SORG until the timing of the down edge of the control input signal SIN, the adjustment circuit 131 inserts a delay time TDLY according to the power supply voltage VDD. However, the delay time TDLY is not inserted when “VDD=VDDMIN”.
In other words, when “VDD=VDDMIN”, the adjustment circuit 131 causes the high level period of the original input signal SORG to coincide with the high level period of the control input signal SIN, and causes the low level period of the original input signal SORG to coincide with the low level period of the control input signal SIN. Hence, in a case where “VDD=VDDMIN”, when the level of the original input signal SORG transitions from a high level to a low level, the adjustment circuit 131 immediately causes the level of the control input signal SIN to transition from a high level to a low level without providing the delay time TDLY.
On the other hand, in a case where “VDD>VDDMIN”, when the level of the original input signal SORG transitions from a high level to a low level, the adjustment circuit 131 causes the level of the control input signal SIN to transition from a high level to a low level after the delay time TDLY.
When the level of the original input signal SORG transitions from a low level to a high level, the adjustment circuit 131 immediately causes the level of the control input signal SIN to transition from a low level to a high level without depending on the power supply voltage VDD.
When “VDD>VDDMIN”, for example, the delay time TDLY corresponding to “TDLY=α×(VDD−VDDMIN)” may be set (a has a predetermined positive value). When “VDD>VDDMIN”, the delay time TDLY may be increased non-linearly as the power supply voltage VDD is increased.
In a state where the low level range of the original input signal SORG is a predetermined range, when “VDD=VDDMIN”, the adjustment circuit 131 in the improvement method sets the low level range of the control input signal SIN larger than that when “VDD=VDDMAX” by the delay time TDLY_MAX. Hence, in the improvement method, a difference between the high level range (TB_MIN) of the output voltage VBUS when “VDD=VDDMIN” and the high level range (TB_MAX) of the output voltage VBUS when “VDD=VDDMAX” is smaller than that in the reference method, and is ideally zero. This means that the H duty of the output voltage VBUS is not affected by the power supply voltage VDD or is unlikely to be affected by the power supply voltage VDD.
In the reference method corresponding to
Although in the example of
Supplementary items, applied technology, variation technology or the like for the above embodiment will be described.
The communication system 1 can be installed in a vehicle such as an automobile. In the vehicle such as an automobile, as a communication system which performs bidirectional communication conforming to the LIN standard or the CXPI standard, the communication system 1 can be used. More specifically, for example, communication between the transceiver 10 and the other side device 30 can be used as communication of signals for realizing body control of power windows, mirrors, electric seats, door locks or the like provided in an automobile.
However, the communication system 1 is not limited to being used in a vehicle. The communication system 1 can be applied to any application in which relatively low speed communication is performed.
The transceiver 10 includes a signal transmitting apparatus which generates an output signal corresponding to the original input signal SORG at the bus connection terminal BUS functioning as an output terminal (in other words, which transmits the output signal from the bus connection terminal BUS). The constituent elements of the signal transmitting apparatus include the transmission circuit TX and can further include the bus connection terminal BUS. A semiconductor device which includes the functions of the transceiver 10 and the microcomputer 20 may be formed, and in this case, the signal transmitting apparatus is provided in the semiconductor device. The control input signal supply circuit 130 (in particular, the adjustment circuit 131) functions as a signal generation circuit which generates the control input signal SIN from the original input signal SORG.
For any signal or voltage, the relationship between a high level and a low level which has been described above may be reversed without departing from the spirit of the above description. Hence, for example, a variation may be adopted in which the high level in the original input signal SORG is associated with the low level in the control input signal SIN, and the low level in the original input signal SORG is associated with the high level in the control input signal SIN. The adjustment circuit 131 of the variation generates a down edge in the control input signal SIN when an up edge occurs in the original input signal SORG and generates an up edge in the control input signal SIN when a down edge occurs in the original input signal SORG.
The type of channel of the FET (field-effect transistor) described in the embodiment is an example. The type of channel of any FET can be changed between the P-channel type and the N-channel type without departing from the spirit of the above description.
As long as no disadvantage occurs, any of the transistors described above may be any type of transistor. For example, as long as no disadvantage occurs, any of the transistors which is described above as the MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor. Any of the transistors includes a first electrode, a second electrode and a control electrode. In the FET, one of the first and second electrodes is the drain, the other is the source and the control electrode is the gate. In the IGBT, one of the first and second electrodes is the collector, the other is the emitter and the control electrode is the gate. In the bipolar transistor which does not belong to the IGBT, one of the first and second electrodes is the collector, the other is the emitter and the control electrode is the base.
The embodiment of the present disclosure can be changed variously as necessary within the scope of the technical ideas indicated in the scope of claims. The above embodiment is merely an example of the embodiment of the present disclosure, and the meanings of the terms in the present disclosure or the constituent elements are not limited to those described in the above embodiment. Specific numerical values indicated in the above description are merely examples and can naturally be changed to various numerical values.
Additional notes are provided for the present disclosure the specific configuration examples of which are shown in the embodiment described above.
A signal transmitting apparatus (10) according to an aspect of the present disclosure includes: an output terminal (BUS) configured to be connected to an application end (50) of a power supply voltage (VDD) via a pull-up resistor (52) and a backcurrent prevention diode (53); an output transistor (111) provided between the output terminal and a ground; a capacitor (112) connected between a gate of the output transistor and the output terminal; a signal generation circuit (130) configured to generate a control input signal (SIN) based on an original input signal (SORG); and a charge-discharge circuit (120) configured to charge or discharge the gate of the output transistor according to the control input signal, the output transistor is turned on or off through the charging or the discharging of the gate of the output transistor to generate an output signal (VBUS) corresponding to the original input signal and the control input signal at the output terminal, the backcurrent prevention diode has a forward direction from the application end of the power supply voltage toward the output terminal, the charge-discharge circuit charges the gate of the output transistor to turn on the output transistor when the control input signal has a first level (for example, a high level), discharges the gate of the output transistor to turn off the output transistor when the control input signal has a second level (for example, a low level) and sets values of a charge current (IC) and a discharge current (ID) for the gate of the output transistor according to the power supply voltage and the signal generation circuit adjusts, according to the power supply voltage, a range in which the control input signal has the second level (first configuration).
There is a concern that the presence of the backcurrent prevention diode may cause a variation in the high level range of the output signal depending on the power supply voltage even if the original input signal is constant. In the configuration described above, the range in which the control input signal has the second level is adjusted according to the power supply voltage, and thus it is possible to suppress the variation. In other words, it is possible to reduce the dependance of the output signal on the power supply voltage.
Preferably, in the signal transmitting apparatus according to the first configuration described above, the signal generation circuit causes a level of the control input signal to transition from the first level to the second level in response to a transition of a level of the original input signal from a third level (for example, a high level) to a fourth level (for example, a low level), and causes the level of the control input signal to transition from the second level to the first level in response to a transition of the level of the original input signal from the fourth level to the third level, and in a state where a range in which the original input signal has the fourth level is a predetermined range, when the power supply voltage has a predetermined first voltage value (for example, a voltage VDDMIN), the signal generation circuit sets the range in which the control input signal has the second level larger than when the power supply voltage has a predetermined second voltage value (for example, a VDDMAX) higher than the first voltage value (second configuration).
In this way, it is possible to suppress a variation in the high level range of the output signal which depends on the power supply voltage.
Preferably, in the signal transmitting apparatus according to the first configuration described above, the signal generation circuit causes a level of the control input signal to transition from the first level to the second level in response to a transition of a level of the original input signal from a third level (for example, a high level) to a fourth level (for example, a low level), and causes the level of the control input signal to transition from the second level to the first level in response to a transition of the level of the original input signal from the fourth level to the third level, and the signal generation circuit is configured to set the level of the control input signal to the first level (for example, a high level) when the original input signal has the third level (for example, a high level) and to be able to insert a delay time (TDLY) corresponding to the power supply voltage when the level of the original input signal transitions from the third level to the fourth level to cause the level of the control input signal to transition from the first level to the second level, that is, during a period after the former transition until the latter transition (third configuration).
In this way, it is possible to suppress a variation in the high level range of the output signal which depends on the power supply voltage.
Preferably, in the signal transmitting apparatus according to the third configuration described above, the signal generation circuit causes the level of the control input signal to transition from the first level (for example, a high level) to the second level without providing the delay time when the power supply voltage has a predetermined first voltage value (for example, a VDDMIN), and the level of the original input signal transitions from the third level (for example, a high level) to the fourth level, and causes the level of the control input signal to transition from the first level to the second level after the delay time when the power supply voltage has a predetermined second voltage value (for example, a VDDMAX) higher than the first voltage value, and the level of the original input signal transitions from the third level to the fourth level (fourth configuration).
Preferably, in the signal transmitting apparatus according to any one of the first to fourth configurations described above, the charge-discharge circuit increases the charge current and the discharge current for the gate of the output transistor as the power supply voltage is increased (fifth configuration).
In this way, the slew rate of the output signal can be increased as the power supply voltage is increased, and consequently, it is possible to suppress the dependence of the high level range or the low level range of the output signal on the power supply voltage.
Preferably, in the signal transmitting apparatus according to any one of the first to fifth configurations described above, the charge-discharge circuit includes: a charging circuit (121) configured to supply the charge current to the gate of the output transistor during a period in which the control input signal has the first level; and a discharging circuit (122) configured to draw the discharge current from the gate of the output transistor during a period in which the control input signal has the second level (sixth configuration).
Preferably, in the signal transmitting apparatus according to any one of the first to sixth configurations described above, a drain of the output transistor is connected to the output terminal via another backcurrent prevention diode (113) that has a forward direction from the output terminal toward the ground, or is directly connected to the output terminal (seventh configuration).
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-143092 | Sep 2022 | JP | national |
This application is a continuation under 35 U.S.C. § 120 of International Patent Application No. PCT/JP2023/023589 filed on Jun. 26, 2023, which is incorporated herein by reference, and which claimed priority to Japanese Patent Application No. 2022-143092 filed on Sep. 8, 2022. The present application likewise claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2022-143092 filed on Sep. 8, 2022, the entire content of which is also incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/023589 | Jun 2023 | WO |
| Child | 19073761 | US |
