Patent Application
20250219634
The present disclosure relates to a signal transmitting apparatus.
There is a signal transmitting apparatus that transmits an output signal from an output terminal. One type of the signal transmitting apparatus needs to satisfy both a required performance related to an output signal slew rate and a required performance related to radiation noise.
Hereinafter, an example of an embodiment of the present disclosure is specifically described with reference to the drawings. In the drawings that are referred to, the same part is denoted by the same numeral or symbol, and overlapping description of the same part is omitted as a rule. Note that in this specification, for simple description, a name of information, a signal, a physical quantity, a functional unit, a circuit, an element, a component, or the like may be omitted or abbreviated by referring to a numeral or symbol representing the same. For instance, a bus connection terminal BUS represented by “BUS” described later (see
First, some terms used for describing the embodiment of the present disclosure are described below. A line means a wiring through which an electric signal is transmitted or to which the same is applied. A ground means a reference conductive part having a potential of zero volts (0 V) to be a reference, or it means the potential of 0 V itself. The reference conductive part may be formed using a conductor such as metal. The potential of 0 V may be referred to as a ground potential. In the embodiment of the present disclosure, a voltage without a specific reference means a potential with respect to the ground.
A level means a potential level, and for an arbitrary noted signal or voltage, a high level has a higher potential than a low level. For an arbitrary noted signal or voltage, if the signal or voltage is at high level, it means that the level of the signal or voltage is at high level in a precise sense, and if the signal or voltage is at low level, it means that the level of the signal or voltage is at low level in a precise sense. A level of a signal may be referred to as a signal level, and a level of a voltage may be referred to as a voltage level.
For an arbitrary noted signal or voltage, switching from low level to high level is referred to as an up edge. The up edge may be read as a rising edge. Similarly, in an arbitrary noted signal or voltage, switching from high level to low level is referred to as a down edge. The down edge may be read as a falling edge.
For an arbitrary transistor constituted as a field effect transistor (FET) including a MOSFET, ON state means a conducting state between drain and source of the transistor, while OFF state means a non-conducting state (cut-off state) between drain and source of the transistor. The same is true also for a transistor that is not classified into FET. A MOSFET is understood as an enhancement-type MOSFET unless otherwise noted. MOSFET is an abbreviation of “metal-oxide semiconductor field effect transistor”. In addition, for an arbitrary MOSFET, it may be considered that the backgate is connected to the source unless otherwise noted.
For an arbitrary signal having a signal level of high level or low level, the period while the signal level is high level is referred to as a high level period, while the period while the signal level is low level is referred to as a low level period. The same is true for an arbitrary voltage having a voltage level of high level or low level.
A connection between a plurality of parts constituting a circuit, such as arbitrary circuit elements, wirings (lines), or nodes, should be understood to mean an electrical connection unless otherwise noted.
A power supply voltage VDD is supplied to the power supply terminal VIN from a voltage source that is not illustrated. The power supply voltage VDD has a predetermined positive DC voltage value. The transceiver 10 is driven on the basis of the power supply voltage VDD. The ground terminal GND is connected to the ground. The bus connection terminal BUS is connected to one end of the bus line 51, and the other end of the bus line 51 is connected to the other side device 30. In other words, the bus connection terminal BUS is connected to the other side device 30 via the bus line 51. Note that the other side device 30 also has a terminal for receiving the power supply voltage VDD and a terminal that is connected the ground and is driven on the basis of the power supply voltage VDD.
The bus line 51 is connected to an application terminal 50 of the power supply voltage VDD via the pull-up resister 52 and the backcurrent prevention diode 53. The application terminal 50 is a terminal to which the power supply voltage VDD is applied. The backcurrent prevention diode 53 has a forward direction from the application terminal 50 to the bus line 51 and the bus connection terminal BUS. The backcurrent prevention diode 53 blocks current flow from the bus line 51 to the application terminal 50. More specifically, the anode of the backcurrent prevention diode 53 is connected to the application terminal 50 while the cathode of the backcurrent prevention diode 53 is connected to one end of the pull-up resister 52, and the other end of the pull-up resister 52 is connected to the bus line 51.
However, disposed positions of the pull-up resister 52 and the backcurrent prevention diode 53 may be opposite to those illustrated in
The capacitor 54 is connected between the bus line 51 and the ground. In other words, one end of the capacitor 54 is connected to the bus line 51, and the other end of the capacitor 54 is connected to the ground. Note that the capacitor 54 may be constituted of a plurality of capacitors that are separated from each other. The capacitor 54 may be omitted.
The reception data output terminal RXD is connected to one end of the data line 61, and the other end of the data line 61 is connected to the microcomputer 20. The transmission data input terminal TXD is connected to one end of the data line 62, and the other end of the data line 62 is connected to the microcomputer 20. In other words, the terminals RXD and TXD are connected to the microcomputer 20 via the data lines 61 and 62. The data line 61 is connected to an application terminal of a power supply voltage VCC via the pull-up resister 63. The power supply voltage VCC has a predetermined positive DC voltage value. It does not matter whether or not the power supply voltages VCC and VDD have the same value. The microcomputer 20 has a terminal for receiving the power supply voltage VCC and a terminal connected to the ground and is driven on the basis of the power supply voltage VCC.
The transceiver 10 includes a receiving circuit RX and a transmitting circuit TX. The receiving circuit RX is connected to the reception data output terminal RXD and the bus connection terminal BUS. The transmitting circuit TX is connected to the transmission data input terminal TXD and the bus connection terminal BUS.
The transceiver 10 and the other side device 30 perform bidirectional communication with each other by a half-duplex system via the bus line 51. The bidirectional communication supposed in this embodiment is a serial communication by a single wire protocol (i.e., a serial communication using the bus line 51 as a single wire). In the bidirectional communication by the half-duplex system, it may be possible that the transceiver 10 works as a master while the other side device 30 works as a slave, or it may be possible that the other side device 30 works as a master while the transceiver 10 works as a slave. The bidirectional communication between the transceiver 10 and the other side device 30 may be, for example, bidirectional communication conforming the LIN (Local Interconnect Network) standard or the CXPI (Clock Extension Peripheral Interface) standard.
In the bidirectional communication by the half-duplex system, either one of the transceiver 10 and the other side device 30 works as a transmission side device, and the other works as a reception side device.
When the transceiver 10 works as a reception side device, the other side device 30 transmits a signal (hereinafter, referred to as a signal SR) via the bus line 51, and the receiving circuit RX receives the signal SR transmitted from the other side device 30, at the bus connection terminal BUS. The receiving circuit RX transfers the received signal SR from terminal RXD to the microcomputer 20 via the data line 61. When the transceiver 10 works as a reception side device, the bus connection terminal BUS works as an input terminal (a signal reception terminal) that receives the signal transmitted from the other side device 30.
When the transceiver 10 works as a transmission side device, the microcomputer 20 transmits a signal (hereinafter, referred to as a signal ST) to the transceiver 10 via the data line 62. The signal ST from the microcomputer 20 is received at the terminal TXD. When the transceiver 10 works as a transmission side device, the transmitting circuit TX transmits the signal ST received from the microcomputer 20 to the other side device 30 via the bus line 51. The other side device 30 may be constituted of a transceiver and a microcomputer, which are similar to the transceiver 10 and the microcomputer 20, and in this case the signal ST received from the transceiver 10 is transferred from the transceiver of the other side device 30 to the microcomputer of the other side device 30. When the transceiver 10 works as a transmission side device, the bus connection terminal BUS works as an output terminal (a signal transmission terminal) at which the signal appears to be transmitted from the transceiver 10.
The signal transmission via the bus line 51 is realized by controlling the level of the bus line 51 to be high level or low level. The level of the bus line 51 is the same as the level of the bus connection terminal BUS. The level of the bus line 51 is 0 V or more and less than or equal to the level of the power supply voltage VDD. When the bus line 51 has a level of voltage (VDD×kH) or more, the level of the bus line 51 corresponds to high level. When the bus line 51 has a level of voltage (VDD×kL) or less, the level of the bus line 51 corresponds to low level. Here “1>kH>0.5>kL>0” holds, and (kH, kL)=(0.7, 0.3) holds, for example. The voltage of the bus line 51 and the bus connection terminal BUS is represented by a symbol “VBUS”.
Hereinafter, an operation and a structure where the transceiver 10 works as a transmission side device is described unless otherwise noted. For the transmitting circuit TX, the voltage VBUS corresponds to an output voltage (an output voltage of the transmitting circuit TX). Therefore, the voltage VBUS when a structure or an operation of the transmitting circuit TX is noted can be referred to as the output voltage in the following description. The signal indicated by the output voltage VBUS can be referred to as an output signal. The transmitting circuit TX of the transceiver 10 has a function of controlling a slew rate of the output voltage VBUS in order to reduce radiation noise, when changing the level of the bus line 51 between high level and low level, in signal transmission via the bus line 51.
The output transistor 111 is an N-channel type MOSFET. The output transistor 111 is disposed between the bus connection terminal BUS that works as an output terminal and the ground, and the transmitting circuit TX performs signal transmission by using the output transistor 111 having an open drain structure. However, the backcurrent prevention diode 113 is disposed between the output transistor 111 and the bus connection terminal BUS, in order to block current flow from the ground to the bus line 51 via the output transistor 111 and the bus connection terminal BUS. Specifically, the drain of the output transistor 111 is connected to the cathode of the backcurrent prevention diode 113, and the anode of the backcurrent prevention diode 113 is connected to the bus connection terminal BUS. The source of the output transistor 111 is connected to the ground. A gate voltage of the output transistor 111 (i.e., a voltage applied to the gate of the output transistor 111) is represented by a symbol “VG”. A gate threshold voltage of the output transistor 111 is represented by a symbol “VG_TH”. The gate threshold voltage VG_TH has a positive voltage value depending on characteristics of the output transistor 111. When the gate voltage VG of the output transistor 111 is less than the gate threshold voltage VG_TH, the output transistor 111 is in OFF state. When the gate voltage VG of the output transistor 111 is the gate threshold voltage VG_TH or more, the output transistor 111 is in ON state.
Note that the transmitting circuit TX may be modified so that the backcurrent prevention diode 113 is not disposed, and when this modification is adopted, the drain of the output transistor 111 is directly connected to the bus connection terminal BUS.
The capacitor 112 is connected between the gate of the output transistor 111 and the bus connection terminal BUS. In other words, one end of the capacitor 112 is connected to the gate of the output transistor 111, and the other end of the capacitor 112 is connected to the bus connection terminal BUS.
The charge-discharge circuit 120 charges or discharges the gate of the output transistor 111 in accordance with a control input signal SIN. The charge-discharge circuit 120 can control the output transistor 111 to be ON state by charging the gate of the output transistor 111 and can control the output transistor 111 to be OFF state by discharging the gate of the output transistor 111. The control input signal SIN is a binary signal having a signal level of high level or low level. The control input signal SIN of high level has substantially a potential of an internal power supply voltage VREG, and the control input signal SIN of low level has substantially the ground potential. The internal power supply voltage VREG that is a positive DC voltage is generated from the power supply voltage VDD by a regulator (not shown) in the transceiver 10. The charge-discharge circuit 120 includes a charging circuit 121 and a discharging circuit 122.
During the high level period of the control input signal SIN, the charging circuit 121 supplies a charge current to the gate of the output transistor 111, so as to increase the gate voltage VG of the output transistor 111. However, the gate voltage VG has an upper limit, and the gate voltage VG does not increase over the upper limit voltage. The upper limit voltage of the gate voltage VG is the internal power supply voltage VREG or is a predetermined voltage lower than the internal power supply voltage VREG. The upper limit voltage of the gate voltage VG is higher than the gate threshold voltage VG_TH of the output transistor 111. During the period while the gate voltage VG increases from a sufficiently low voltage (e.g., 0 V), when the gate voltage VG reaches the gate threshold voltage VG_TH, the output transistor 111 switches from OFF state to ON state. Specifically, during the period while the gate voltage VG increases from a sufficiently low voltage (e.g., 0 V), when the gate voltage VG becomes the gate threshold voltage VG_TH or higher, a channel resistance value of the output transistor 111 is rapidly decreased, and when the channel resistance value of the output transistor 111 becomes sufficiently smaller than the resistance value of the pull-up resister 52, the voltage VBUS is decreased to substantially 0 V. The channel resistance value of the output transistor 111 means a resistance value between drain and source of the output transistor 111.
During the low level period of the control input signal SIN, the discharging circuit 122 draws a discharge current from the gate of the output transistor 111, so as to decrease the gate voltage VG of the output transistor 111. However, the gate voltage VG has a lower limit, and the gate voltage VG does not decrease under the lower limit voltage. The lower limit voltage of the gate voltage VG is 0 V. During the period while the gate voltage VG decreases from a voltage higher than the gate threshold voltage VG_TH, when the gate voltage VG becomes below the gate threshold voltage VG_TH, the output transistor 111 switches from ON state to OFF state. Specifically, during the period while the gate voltage VG decreases from a voltage higher than the gate threshold voltage VG_TH, when the gate voltage VG becomes lower than the gate threshold voltage VG_TH, the channel resistance value of the output transistor 111 is rapidly increased, and when the channel resistance value of the output transistor 111 becomes sufficiently larger than the resistance value of the pull-up resister 52, the output voltage VBUS increases to near the power supply voltage VDD.
In the structural example of
During the high level period of the control input signal SIN, the switch 121b is turned on while the switch 122b is turned off. Therefore, during the high level period of the control input signal SIN, the current IC for increasing the gate voltage VG (hereinafter, referred to as a charge current IC) is supplied from the charging current source 121a to the gate of the output transistor 111 via the switch 121b and the node 123. During the low level period of the control input signal SIN, there is no charge exchange between the gate of the output transistor 111 and the charging circuit 121.
During the low level period of the control input signal SIN, the switch 121b is turned off while the switch 122b is turned on. Therefore, during the low level period of the control input signal SIN, the current ID for decreasing the gate voltage VG (hereinafter, referred to as a discharge current ID) is drawn from the gate of the output transistor 111 to the discharging current source 122a via the node 123 and the switch 122b. During the high level period of the control input signal SIN, there is no charge exchange between the gate of the output transistor 111 and the discharging circuit 122.
The control input signal supply circuit 130 generates the control input signal SIN on the basis of the signal ST received from the microcomputer 20 and supplies the control input signal SIN to the charge-discharge circuit 120. The control input signal supply circuit 130 may generate, for example, a binary signal obtained by shaping a waveform of the signal ST, as the control input signal SIN.
Note that the charging circuit 121 may have any structure, as long as it can supply the charge current IC to the gate of the output transistor 111 during the high level period of the control input signal SIN. During the low level period of the control input signal SIN, the charging circuit 121 may stop generation of the charge current IC. In any case, during the low level period of the control input signal SIN, the charge current IC from the charging circuit 121 to the gate of the output transistor 111 is zero. Similarly, the discharging circuit 122 may have any structure, as long as it can draw the discharge current ID from the gate of the output transistor 111 during the low level period of the control input signal SIN. During the high level period of the control input signal SIN, the discharging circuit 122 may stop generation of the discharge current ID. In any case, during the high level period of the control input signal SIN, the discharge current ID from the gate of the output transistor 111 to the discharging circuit 122 is zero.
The gate voltage limit circuit 140 is connected to the gate of the output transistor 111 and the ground. The gate voltage limit circuit 140 has two diodes 141 and 142. The anode of the diode 141 is connected to the gate of the output transistor 111 while the cathode of the diode 141 is connected to the anode of the diode 142, and the cathode of the diode 142 is connected to the ground. The gate voltage limit circuit 140 has a function of suppressing the gate voltage VG from being a predetermined limit voltage VLIM or more and may be any circuit as long as it has the function. Here, the limit voltage VLIM is higher than the gate threshold voltage VG_TH and corresponds to the sum of forward voltages of the diodes 141 and 142 in the structural example of
During the period while the output transistor 111 switches from OFF state to ON state due to an increase in the gate voltage VG based on the charge current IC, the output voltage VBUS is decreased, and the decrease in the output voltage VBUS is fed back to the gate of the output transistor 111 via the capacitor 112. On the contrary, during the period while the output transistor 111 switches from ON state to OFF state due to a decrease in the gate voltage VG based on the discharge current ID, the output voltage VBUS is increased, and the increase in the output voltage VBUS is fed back to the gate of the output transistor 111 via the capacitor 112. For this reason, with respect to the charge-discharge circuit 120, a capacitance value of the capacitor 112 looks larger than the actual capacitance value of the capacitor 112 in an equivalent manner, due to a mirror effect. In other words, the capacitor 112 functions as a mirror capacitor.
As the slew rate of the output voltage VBUS, there are an up slew rate when the output voltage VBUS is increased, and a down slew rate when the output voltage VBUS is decreased. The up slew rate indicates a maximum value or an average value of change rates of the output voltage VBUS when the output voltage VBUS is increased. The down slew rate indicates a maximum value or an average value of change rates of the output voltage VBUS when the output voltage VBUS is decreased. Hereinafter, the up slew rate and the down slew rate are collectively referred to as output slew rates. In the following description, it is understood that the output slew rate indicates either one of the up slew rate and the down slew rate, or indicates both the up slew rate and down slew rate.
A decrease in the output slew rate contributes to reduction of radiation noise, while the transceiver 10 operating as a transmission side device needs to satisfy the following output signal condition. The output signal condition may be a condition defined in the LIN standard or the CXPI standard, for example.
With reference to
The charge-discharge circuit 120 charges the gate of the output transistor 111 so as to control the output transistor 111 to ON state, during the period while the control input signal SIN has the output low indication level, while it discharges the gate of the output transistor 111 so as to control the output transistor 111 to OFF state, during the period while the control input signal SIN has the output high indication level. In the example of this embodiment, the output low indication level of the control input signal SIN is high level, and the output high indication level of the control input signal SIN is low level, but it is possible to modify so that the output low indication level of the control input signal SIN is low level while the output high indication level thereof is high level.
A length of the low level period of the control input signal SIN (i.e., the period while the control input signal SIN has the output high indication level) is referred to as a time period TA. The low level period and the high level period of the control input signal SIN appear alternately and repeatedly, and among the low level periods of the control input signal SIN, a certain noted low level period has a length that is referred to as the time period TA. Specifically, it is supposed that a down edge occurs in the control input signal SIN at a time point t1, and after that an up edge occurs in the control input signal SIN at a time point t3. In this case, the time period from the time point t1 to the time point t3 is the time period TA. Note that a time point t2 is after the time point t1 and before the time point t3 as illustrated in
The drawing of discharge current ID from the gate of the output transistor 111 is started at the time point t1. When the gate voltage VG is decreased to the gate threshold voltage VG_TH by the discharge current ID, the output voltage VBUS starts to increase from 0 V or a voltage close to 0 V, on the basis of the increase in the channel resistance value of the output transistor 111. After that, the output voltage VBUS reaches a voltage (VDD×kREF) at the time point t2. The voltage (VDD×kREF) is kREF times the power supply voltage VDD. Here, kREF has a positive predetermined value less than one, which is defined by the standard applied to the communication system 1 (e.g., the LIN standard or the CXPI standard), and may have the same value as the above coefficient kH. Here, “kREF=kH=0.7” holds. The output voltage VBUS increase also after the time point t2.
Further, when an up edge occurs in the control input signal SIN at the time point t3, discharging of the gate of the output transistor 111 is stopped, and instead, charging of the gate of the output transistor 111 is started. When the gate voltage VG is increased to the gate threshold voltage VG_TH by the charge current IC, the output voltage VBUS starts to decrease from a voltage higher than the voltage (VDD×kREF), on the basis of a decrease in the channel resistance value of the output transistor 111. After that, the output voltage VBUS is decreased to the voltage (VDD×kREF) at the time point t4. The output voltage VBUS decreases also after the time point t4.
The length between the time points t2 and t4 is referred to as a time period TB. The output signal condition is a condition that a ratio of the time period TB to the time period TA, i.e., a ratio (TB/TA) is a predetermined threshold value RTH or more. If “TB/TA≥RTH” holds, the output signal condition is satisfied. If “TB/TA<RTH” holds, the output signal condition is not satisfied. The threshold value RTH has a positive predetermined value less than one, which is defined by the standard applied to the communication system 1 (e.g., the LIN standard or the CXPI standard), and “RTH=0.8” holds, for example.
A forward voltage of the backcurrent prevention diode 53 is denoted by a symbol “Vf”. During the low level period of the control input signal SIN, the output voltage VBUS does not increase over the voltage (VDD-Vf).
Note that the signal ST also alternately has the output high indication level and the output low indication level, and the control input signal supply circuit 130 sets the level of the control input signal SIN to the output high indication level when receiving the signal ST of the output high indication level, while it sets the level of the control input signal SIN to the output low indication level when receiving the signal ST of the output low indication level. For this reason, the time period TA may be understood to correspond to the length of the period while the signal ST has the output high indication level. As described above, the control input signal SIN may be a binary signal obtained by shaping the waveform of the signal ST from the microcomputer 20, and the control input signal SIN may be a signal equivalent to the signal ST. It may also be possible to understand that the signal ST itself is the control input signal SIN.
On the other hand, in the communication system 1, the power supply voltage VDD has a voltage within a power supply voltage range from a minimum voltage VDDMIN to a maximum voltage VDDMAX. The minimum voltage VDDMIN and the maximum voltage VDDMAX have positive predetermined voltage values that satisfy “0<VDDMIN<VDDMAX”. It is always necessary to satisfy the output signal condition as long as the power supply voltage VDD is within the power supply voltage range. If the output slew rate is set to be always sufficiently large, the output signal condition is easily satisfied, but an increase in the output slew rate causes an increase in radiation noise.
The transceiver 10 is also required to satisfy a radiation noise condition conforming the standard applied to the communication system 1 (e.g., the LIN standard or the CXPI standard). If the amount of radiation noise from the communication system 1 when the transceiver 10 is operated as a transmission side device is a specified value or less in a predetermined noise test environment, the radiation noise condition for the transceiver 10 is satisfied. Usually, a radiation noise test is performed, in which the amount of radiation noise from the communication system 1 when the transceiver 10 is operated as a transmission side device is measured, in a predetermined noise test environment, and it is determined whether or not the radiation noise condition is satisfied on the basis of the measured value. Here, the power supply voltage VDD in the noise test environment is a test voltage VDDTYP having a typical value within the power supply voltage range. The test voltage VDDTYP is higher than the minimum voltage VDDMIN and is lower than the maximum voltage VDDMAX. For instance, VDDTYP=(VDDMIN+VDDMAX)/2 may hold.
As a method for aiming to satisfy both the output signal condition and the radiation noise condition, a method is studied that allows the output slew rate to be proportional to the power supply voltage VDD (a reference method).
In the reference method, the charge current IC and the discharge current ID are allowed to be proportional to the power supply voltage VDD as illustrated in
Here, it is basically harder to satisfy the output signal condition as the power supply voltage VDD is lower. In order to satisfy the output signal condition, it is necessary to increase the ratio (TB/TA), and it is because the ratio (TB/TA) tends to be smaller as a ratio of a forward voltage Vf (a forward voltage Vf of the backcurrent prevention diode 53) in the power supply voltage VDD is larger.
In the case where “VDD=VDDMAX” holds, “(VDDMAX−Vf)=26.3 V”, “VDD×kREF=VDDMAX×0.7=18.9 V”, and “18.9/26.3≈0.719” hold. Therefore, in the case where “VDD=VDDMAX” holds, in order that the output voltage VBUS might reach the voltage (VDD×kREF) after the down edge of the control input signal SIN, it is necessary that the output voltage VBUS be increased from 0 V by approximately 0.719 times the voltage (VDD-Vf). In the case where “VDD=VDDMIN” holds, “(VDDMIN-Vf)=4.3 V”, “VDD×kREF=VDDMIN×0.7=3.5 V” and “3.5/4.3≈0.814” hold. Therefore, in the case where “VDD=VDDMIN” holds, in order that the output voltage VBUS might reach the voltage (VDD×kREF) after the down edge of the control input signal SIN, it is necessary that the output voltage VBUS be increased from 0 V by approximately 0.814 times the voltage (VDD-Vf).
In the reference method, the time necessary for the output voltage VBUS to increase by approximately 0.814 times the voltage (VDD-Vf) is longer than the time necessary for the output voltage VBUS to increase by approximately 0.719 times the voltage (VDD-Vf). As a result, in the reference method, the output signal condition is hardly satisfied when the power supply voltage VDD is identical or similar to the minimum voltage VDDMIN (on the contrary, if the output slew rate is increased so as to satisfy the output signal condition, the radiation noise condition is hardly satisfied).
Therefore, the transceiver 10 according to this embodiment adopts an improved method different from the reference method. In the transceiver 10 according to the improved method, the charge current IC and the discharge current ID are changed nonlinearly in accordance with the power supply voltage VDD.
A voltage VDDMID illustrated in
Specifically, if the power supply voltage VDD is the boundary voltage VDDMID or less, the charge-discharge circuit 120 sets and maintains the value of the adjustment target current (the value of the charge current IC and the value of the discharge current ID) to a predetermined reference current value VALREF. If the power supply voltage VDD is higher than the boundary voltage VDDMID, the charge-discharge circuit 120 increases the value of the adjustment target current (the value of the charge current IC and the value of the discharge current ID) to be larger than the reference current value VALREF, and increases the he value of the adjustment target current along with an increase in the power supply voltage VDD.
For instance, the value of the adjustment target current when “VDD>VDDMID” holds is denoted by a symbol “VAL”, and then “VAL=kp×(VDD-VDDMID)+VALREF” may hold. Here, kp is a coefficient having a predetermined positive value. In this way, in the improved method, there is a nonlinear relationship between the power supply voltage VDD and the adjustment target current.
Note that the reference current value VALREF for the charge current IC may be the same as the reference current value VALREF for the discharge current ID, or they may be different from each other. The boundary voltage VDDMID may be the same as the test voltage VDDTYP described above. Alternatively, the boundary voltage VDDMID may be higher than the test voltage VDDTYP though it is close to the test voltage VDDTYP.
According to the improved method, in the environment where “VDD=VDDMIN” holds, the value of the adjustment target current can be larger than that in the reference method (920), and in the noise test environment the value of the adjustment target current can be smaller than that in the reference method (920). For this reason, it is possible to satisfy both the output signal condition and the radiation noise condition (both a required performance related to the output slew rate and a required performance related to the radiation noise). If “VDD>VDDMID” holds, the adjustment target current should be increased in accordance with an increase in the power supply voltage VDD, so that the output signal condition can be satisfied also in the case where “VDD>VDDMID” holds.
The output slew rate is schematically proportional to the adjustment target current, and hence a relationship between the power supply voltage VDD and the output slew rate in the improved method is like the relationship illustrated in
Now, values J1 and J2 are defined as follows. The value J1 is a value obtained by dividing the output slew rate SR1 by the minimum voltage VDDMIN (i.e., J1=SR1/VDDMIN). The value J2 is a value obtained by dividing the output slew rate SR2 by the maximum voltage VDDMAX (i.e., J2=SR2/VDDMAX). The charge-discharge circuit 120 according to the improved method changes the adjustment target current in accordance with the power supply voltage VDD, so that the value J1 is higher than the value J2. “J1>J2” is an inequality expressing a part of the characteristics illustrated in
If “VDDMIN≤VDD≤VDDMID” holds in the characteristics illustrated in
The current generation circuit 200 includes a transistor 201 as a P-channel type MOSFET, a clamper 202 that generates and outputs a clamp voltage VCLMP, resistors 203 to 206, an operational amplifier 207, and a V/I conversion circuit 208.
The power supply voltage VDD is applied to the source of the transistor 201 and one end of the resistor 203. The gate of the transistor 201 and the other end of the resistor 203 are connected to each other and receive the clamp voltage VCLMP supplied from the clamper 202. The clamp voltage VCLMP has a predetermined positive DC voltage value. The boundary voltage VDDMID described above is determined depending on the clamp voltage VCLMP. The drain of the transistor 201 is connected to a node 211 via the resistor 204. A positive constant voltage VCNST is applied to one end of the resistor 205, and the other end of the resistor 205 is connected to the node 211. One end of the resistor 206 is connected to the node 211, and the other end of the resistor 206 is connected to the ground. A voltage applied to the node 211 is referred to as a voltage Va.
The operational amplifier 207 constitutes an impedance conversion circuit that outputs the voltage Va of the node 211 to a node 212 with a low impedance. A voltage applied to the node 212 is referred to as a voltage Vb. The operational amplifier 207 works as a voltage follower, and the voltage Vb is equal to the voltage Va (if error is omitted). Specifically, the non-inverting input terminal of the operational amplifier 207 is connected to the node 211, while the inverting input terminal and the output terminal of the operational amplifier 207 are connected to the node 212. The V/I conversion circuit 208 is connected to the node 212, so as to convert the voltage Vb into the adjustment target current IADJ. The V/I conversion circuit 208 allows the adjustment target current IADJ to have a current value proportional to the value of the voltage Vb.
An operation of the current generation circuit 200 depending on the power supply voltage VDD is described below. When “VDD<VDDMID” holds, a voltage for turning on the transistor 201 is not applied to between gate and source of the transistor 201, and the transistor 201 is maintained in OFF state. Therefore, when “VDD<VDDMID” holds, the voltages Va and Vb have a constant voltage value determined by only a resistance value ratio between the resistors 205 and 206 and the constant voltage VCNST, and as a result, the adjustment target current IADJ has the reference current value VALREF (see
When “VDD>VDDMID” holds, the source potential of the transistor 201 with respect to the gate potential of the transistor 201 is more than or equal to the gate threshold voltage of the transistor 201, and the transistor 201 becomes ON state. When “VDD>VDDMID” holds, a current corresponding to the power supply voltage VDD flows from the application terminal of the power supply voltage VDD into the node 211 via the transistor 201 and the resistor 204, and the voltages Va and Vb are increased by the current through the transistor 201. Therefore, when “VDD>VDDMID” holds, the value of the adjustment target current IADJ becomes larger than the reference current value VALREF, and it increases along with an increase in the power supply voltage VDD.
It is possible to separately dispose the current generation circuit 200, which generates the charge current IC as the adjustment target current IADJ, and the current generation circuit 200, which generates the discharge current ID as the adjustment target current IADJ, in the charge-discharge circuit 120. Alternatively, it is possible to dispose two V/I conversion circuits 208 in the single current generation circuit 200. In this case, the first V/I conversion circuit 208 is connected to the node 212, so as to convert the voltage Vb at the node 212 into the charge current IC, while the second V/I conversion circuit 208 is connected to the node 212, so as to convert the voltage Vb at the node 212 into the discharge current ID.
Supplementary note, applied technology, modified technology, or the like of the above embodiment is described below.
The communication system 1 can be mounted in a vehicle such as an automobile. In a vehicle such as an automobile, the communication system 1 can be used as a system that performs bidirectional communication conforming the LIN standard or the CXPI standard. More specifically, for example, the communication between the transceiver 10 and the other side device 30 can be used for signal communication to realize body control of a power window, a mirror, an electric seat, a door lock, or the like mounted in an automobile.
However, the communication system 1 is not limited to the automotive application. The communication system 1 can be applied to any use in which relatively low speed communication is performed.
The transceiver 10 includes the signal transmitting apparatus, which generates an output signal corresponding to an input signal at the bus connection terminal BUS that works as an output terminal (in other words, which transmits the same from the bus connection terminal BUS). Components of the signal transmitting apparatus includes the transmitting circuit TX, and further can include the bus connection terminal BUS. It is possible to understand that the input signal for the signal transmitting apparatus is the control input signal SIN. Because the control input signal SIN is a signal based on the signal ST from the microcomputer 20, the input signal for the signal transmitting apparatus may be understood to be the signal ST. It is possible to form a semiconductor device that includes functions of the transceiver 10 and the microcomputer 20, and in this case the signal transmitting apparatus is disposed in the semiconductor device.
For an arbitrary signal or voltage, a relationship between high level and low level may be opposite to that described above, without impairing the spirit of the above description.
The type of the channel of the field effect transistor (FET) described in each embodiment is merely an example. Without impairing the spirit of the above description, the type of the channel of an arbitrary FET can be changed between P-channel and N-channel types.
As long as no inconvenience occurs, the arbitrary transistor described above may be any type of transistor. For instance, an arbitrary transistor described above as an MOSFET may be replaced by a junction type FET, an insulated gate bipolar transistor (IGBT), or a bipolar transistor, as long as no inconvenience occurs. An arbitrary transistor has a first electrode, a second electrode and a control electrode. In an FET, one of the first and second electrodes is the drain while the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector while the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not classified into IGBT, one of the first and second electrodes is the collector while the other is the emitter, and the control electrode is the base.
The embodiment of the present disclosure can be appropriately modified variously within the scope of the technical concept recited in the claims. The above embodiment is merely an example of the embodiment of the present disclosure, and meaning of terms of the present disclosure and the structural elements are not limited to those described in the above embodiment. Specific numerical values in the above description are merely examples and can be changed to various values as a matter of course.
Additional remarks are described below for the present disclosure in which the specific structural examples are shown with reference to the above embodiment.
A signal transmitting apparatus (10) according to one aspect of the present disclosure includes: an output terminal (BUS) configured to be connected to an application terminal (50) of a power supply voltage (VDD) via a pull-up resister (52) and a backcurrent prevention diode (53); an output transistor (111) disposed between the output terminal and a ground; a capacitor (112) connected between the gate of the output transistor and the output terminal; and a charge-discharge circuit (120) configured to charge or discharge the gate of the output transistor in accordance with an input signal (SIN). The charge or discharge of the gate of the output transistor causes the output transistor to be turned on or off, so that an output signal (VBUS) corresponding to the input signal is generated at the output terminal, the backcurrent prevention diode has a forward direction from the application terminal of the power supply voltage to the output terminal, and the charge-discharge circuit sets a charge current (IC) and a discharge current (ID) of the gate of the output transistor as an adjustment target current, and changes the adjustment target current nonlinearly in accordance with the power supply voltage (first structure).
Thus, it becomes easy to satisfy both a required performance related to an output slew rate and a required performance related to radiation noise.
The signal transmitting apparatus according to the above first structure may have a structure (second structure), in which, compared with a case where the power supply voltage has a predetermined first voltage value (e.g., VDDMIN or VDDMID), in a case where the power supply voltage has a predetermined second voltage value (e.g., VDDMAX) larger than the first voltage value, the charge-discharge circuit sets the adjustment target current to be larger and allows a nonlinear relationship between the power supply voltage and the adjustment target current.
The signal transmitting apparatus having the above first structure may have a structure (third structure), in which the charge-discharge circuit maintains a value of the adjustment target current at a predetermined reference current value (VALREF) when the power supply voltage is a predetermined boundary voltage (VDDMID) or less, while the charge-discharge circuit sets the value of the adjustment target current larger than the reference current value, and increases the same along with an increase in the power supply voltage, when the power supply voltage is higher than the boundary voltage.
The signal transmitting apparatus having any one of the above first to third structures may have a structure (fourth structure), in which the power supply voltage is within a voltage range from a predetermined minimum voltage (VDDMIN) to a predetermined maximum voltage (VDDMAX), the charge-discharge circuit changes the adjustment target current in accordance with the power supply voltage, so that a first value (J1) is larger than a second value (J2), the first value is a value obtained by dividing a slew rate of the output signal when the power supply voltage is equal to the minimum voltage by the minimum voltage, and the second value is a value obtained by dividing the slew rate of the output signal when the power supply voltage is equal to the maximum voltage by the maximum voltage.
The signal transmitting apparatus having any one of the above first to fourth structures may have a structure (fifth structure), in which the charge-discharge circuit charges the gate of the output transistor so as to turn on the output transistor when the input signal has a first level (e.g., high level), while the charge-discharge circuit discharges the gate of the output transistor so as to turn off the output transistor when the input signal has a second level (e.g., low level), and the charge-discharge circuit includes a charging circuit (121) configured to supply the charge current to the gate of the output transistor during a period while the input signal has the first level, and a discharging circuit (122) configured to draw the discharge current from the gate of the output transistor during a period while the input signal has the second level.
The signal transmitting apparatus having any one of the above first to fifth structures may have a structure (sixth structure), in which the drain of the output transistor is connected to the output terminal via another backcurrent prevention diode (113) having a forward direction from the output terminal to the ground, or the drain of the output transistor is directly connected to the output terminal.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-143090 | Sep 2022 | JP | national |
This application is a continuation under 35 U.S.C. § 120 of International Patent Application No. PCT/JP2023/023588 filed on Jun. 26, 2023, which is incorporated herein by reference, and which claimed priority to Japanese Patent Application No. 2022-143090 filed on Sep. 8, 2022. The present application likewise claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2022-143090 filed on Sep. 8, 2022, the entire contents of which is also incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/023588 | Jun 2023 | WO |
| Child | 19063813 | US |
