Claims
- 1. In a system for simulating or testing an electronic device including a physical model, a method for assuring integrity of a series of device evaluation cycles, comprising:
- a) automatically generating a first signature summation of bits from a first pin of said model in response to application of a first set of patterns to said model;
- b) appending another pattern to said first set of patterns to form a second set of patterns;
- c) automatically generating a second signature summation of bits from said first pin of said model in response to application of said second set of patterns to said model before said another pattern is applied to said model during a next device evaluation cycle; and
- d) comparing said first signature summation of bits to said second signature summation of bits prior to application of said another pattern.
- 2. The method of claim 1 further comprising:
- e) repeating steps a)-d) a predefined number of times if said comparing is not true.
- 3. The method of claim 2 further comprising:
- f) halting steps a)-d) if said predefined number is reached.
- 4. The method of claim 3 wherein each of said patterns includes signature clock generation data for providing generation of said signatures.
- 5. The method of claim 4 wherein said signature clock generation data is derived from simulation signal values.
- 6. The method of claim 4 wherein said clock generation data is included with each of said patterns when said pin is at a stable one or zero logic state.
- 7. In a system for simulating or testing an electronic device including a physical model, the improvement for assuring integrity of a series of device evaluation cycles, comprising:
- a) first means for automatically generating a first signature summation of bits from a first pin of said model in response to application of a first set of patterns to said model;
- b) means connected to said first means for appending another pattern to said first set of patterns to form a second set of patterns;
- c) second means connected to said first means for automatically generating a second signature summation of bits from said first pin of said model in response to application of said second set of patterns to said model before said another pattern is applied to said model during a next model evaluation cycle; and
- d) means connected to said first and second means for comparing said first signature summation of bits to said second signature summation of bits prior to applying said another pattern.
- 8. The system of claim 7 wherein each of said patterns includes signature clock generation data for providing generation of said signatures.
- 9. The system of claim 8 wherein said signature clock generation data is derived from simulation signal values.
- 10. The system of claim 8 wherein said clock generation data is included with each of said patterns when said pin is at a stable one or zero logic state.
Parent Case Info
This is a continuation of application Ser. No. 07/345,322 filed Apr. 28, 1989, now abandoned.
US Referenced Citations (7)
Continuations (1)
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Number |
Date |
Country |
Parent |
345322 |
Apr 1989 |
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