Patent Application
20070294484
The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. The embodiments illustrated herein are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown, wherein:
Embodiments of the invention provide a method, system and computer program product for silent invalid state transition handling in an SMP environment. In accordance with an embodiment of the present invention, whenever a cache line in cache of a local node of an SMP system transitions to an invalid state, the node controller for the local node can notify the node controller for the home node of the cache line. In response, both node controllers can evict the cache line from respective directories. In this way, in a subsequent request for the cache line no latencies will arise from detecting a silent state transition for the requested cache line. Furthermore, the directories for the respective node controllers will not needlessly store entries for the invalid cache line.
In further illustration,
Each node controller 120 can be coupled to a corresponding cache directory 130 and a corresponding shared cache directory 140. The local cache directory 130 can include directory listings for cache lines disposed locally irrespective of whether the corresponding node 160 is a home node or a local node for the cache lines. The shared cache directory 140, in contrast, can include a directory of cache lines disposed locally where the corresponding node 160 is a home node for the cache lines.
Notably, invalid state transition logic 200 can be coupled to each node controller 120. The invalid state transition logic 200 can include program code enabled to receive a notification of an invalid state transition for a particular cache line from a processor 110 in the node 160. The program code further can be enabled to broadcast the state transition to other coupled node controllers 120. Each of the node controllers 120, upon receiving notification of an invalid state transition for a cache line, can eject the cache line from respective ones of the local cache directory 130 and shared cache directory 140 as the case may be.
In more particular illustration of the operation of the invalid state transition logic,
Responsive to receiving the state change notification, in block 220 the node controller can evict the cache line from the local cache directory for the node. Thereafter, in block 230 a notification can be forwarded to the node controller for the home node of the cache line. In this regard, the notification can be forwarded directly to the node controller for the home node of the cache line, or the notification can be broadcast to all node controllers in the SMP system thereby assuring that the home node receives the notification without maintaining an awareness of the identity for any one home node for a cache line.
It is to be noted, however, that a copy of the cache line can be selectively retained by the node controller for a local node rather than relinquishing ownership to the home node where an inadvertent invalid state transition has been detected. In particular, recognizing that particular command types often give rise to the invalid state transition such as a bus read partial (BRP), the detection of the command type can cause the retention of a copy of the cache line without relinquishing ownership to the home node in order to achieve faster processing speed for a subsequent request for the cache line in the local node.
Turning now to
The embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, and the like. Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system.
For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD.
A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.
