Patent Application
20250149001
This application claims priority to Chinese patent application No. 202311474471.1 filed with China National Intellectual Property Administration (CNIPA) on Nov. 7, 2023, the disclosure of which is incorporated herein by reference in its entirety.
Embodiments of the present application relate to the field of display technology, for example, a silicon-based display assembly and a display device.
A silicon-based organic light-emitting diode (OLED) product (for example, a silicon-based OLED micro-display device) is different from a conventional active-matrix organic light-emitting diode (AMOLED) panel device that uses an amorphous silicon thin-film transistor, a microcrystalline silicon thin-film transistor, or a low-temperature polysilicon thin-film transistor as a backplane. The silicon-based OLED product uses a monocrystalline silicon chip as the substrate, has a pixel size that is one-tenth of the pixel size of a conventional display device, and is much more precise than the conventional device. A silicon-based OLED display panel (including a silicon-based OLED chip) may adopt a mature integrated circuit complementary metal oxide semiconductor (CMOS) process. In this manner, not only the active addressing matrix of the display pixels of a display screen OLED is implemented, but also a drive control circuit having multiple functions can be implemented on the silicon-based OLED display panel, thereby reducing the external connection lines of the device, increasing the reliability, and implementing lightweight.
To use different levels of manufacturing processes to prepare the active addressing matrix portion and the drive control circuit portion and implement high-resolution and high-frame-rate driving, the silicon-based OLED product generally chooses to remove the drive control circuit portion from the monocrystalline silicon chip and prepare the drive control circuit portion independently, and then use the drive control circuit portion as a display driver integrated circuit (DDIC) and bond the drive control circuit portion to the monocrystalline silicon chip.
However, in the preceding solution, since the DDIC is not only integrated with the functions for receiving, processing, and compressing high-speed data and high-speed images, but also integrated with an active signal driving portion, the DDIC is limited by the fact that the active signal driving portion needs to be electrically connected to signal lines such as data lines and power lines on the silicon-based OLED chip, that is, the input pad on the DDIC needs to be boned to the input pad on the monocrystalline silicon chip, which is used as signal input and power input. Thus, the DDIC needs to be designed in an elongated shape. However, this shape is not conducive to the design and layout of high-speed functional regions such as image compression, image processing, and image algorithms.
The present application provides a silicon-based display assembly and a display device, so that a high-speed portion that requires an image compression function, an image processing function, and an image algorithm function may be freely designed in shape to implement a relatively square layout, reduce design and manufacturing difficulties, and save costs.
In a first aspect, an embodiment of the present application provides a silicon-based display assembly. The silicon-based display assembly includes a silicon-based panel, a flexible circuit board, and a logic control board.
The silicon-based panel includes a display region, a gate row driver circuit, a source signal driver circuit, and a first bonding region. The display region includes multiple data signal lines and multiple gate scanning lines. The multiple data signal lines are arranged in sequence in a first direction and extend in a second direction. The multiple gate scanning lines are arranged in sequence in the second direction and extend in the first direction. The display region also includes multiple pixel units formed by the intersection of the data signal lines and the gate scanning lines. The gate row driver circuit is configured to provide a gate scanning signal to the gate scanning lines. The source signal driver circuit is configured to provide a data signal to the data signal lines. The first direction and the second direction are two directions arbitrarily intersecting on the plane where the silicon-based panel is located.
The flexible circuit board has an end bonded to the first bonding region.
The logic control board is disposed on the flexible circuit board.
The logic control board is integrated with a timing controller module, an algorithm processing module, a first input interface module, a first output interface module, and a power module. The logic control board is configured to at least perform high-speed data receiving and high-speed data processing.
In a second aspect, an embodiment of the present application provides a display device including the silicon-based display assembly described in the first aspect.
The present application is described below in conjunction with drawings and embodiments.
Terms used in embodiments of the present application are intended only to describe embodiments and not to limit the present application. Nouns of locality such as “above”, “below”, “left” and “right” in the embodiments of the present application are described from angles shown in the drawings and are not to be construed as limiting the embodiments of the present application. Additionally, in the context, when an element is formed “above” or “below” another element, the element can not only be directly formed “above” or “below” the other element but also be indirectly formed “above” or “below” the other element via an intermediate element. Terms such as “first” and “second” are used only for the purpose of description to distinguish between different components and not to indicate any order, quantity, importance, or interdependence.
As used herein, the term “include” and variations thereof are intended to be inclusive, that is, “including, but not limited to”. The term “based on” is “at least partially based on”. The term “one embodiment” indicates “at least one embodiment”.
An embodiment of the present application provides a silicon-based display assembly.
The silicon-based panel 10 includes a display region 110, a gate row driver circuit 120, a source signal driver (SD) circuit 130, and a first bonding region 141. The display region 110 includes multiple data signal lines 111 and multiple gate scanning lines 112. The multiple data signal lines 111 are arranged in sequence in a first direction X and extend in a second direction Y. The multiple gate scanning lines 112 are arranged in sequence in the second direction Y and extend in the first direction X. The display region 110 also includes multiple pixel units 11 formed by the intersection of the data signal lines 111 and the gate scanning lines 112. The gate row driver circuit 120 is configured to provide a gate scanning signal to the gate scanning lines 112. The source signal driver circuit 130 is configured to provide a data signal to the data signal lines 111. The first direction X and the second direction Y are two directions arbitrarily intersecting on the plane where the silicon-based panel 10 is located.
An end of the flexible circuit board 20 is bonded to the first bonding region 141 of the silicon-based panel 10.
The logic control board 30 is disposed on the flexible circuit board 20. The logic control board 30 is integrated with a timing controller (T-CON) module 31, an algorithm processing module 32, a first input interface module 33, a first output interface module (TX) 34, and a power module 35. The logic control board 30 is configured to at least perform high-speed data receiving and high-speed data processing.
The silicon-based panel 10 is configured to integrate an active addressing matrix. Specifically, the silicon-based panel 10 is provided with the display region 110. The display region 110 is a region where the active addressing matrix is integrated and is responsible for implementing a display function by addressing drive. The display region 110 is provided with multiple gate scanning lines 112 extending in the first direction X (for example, a row direction) and multiple data signal lines 111 extending in the second direction Y (for example, a column direction). The data signal lines 111 and the gate scanning lines 112 intersect to define multiple pixel units 11. The multiple pixel units 11 form the active addressing matrix, and the pixel units 11 may be addressed through the gate scanning lines 112 and the data lines 111, thereby driving the pixel units 11 to display. In addition to the display region 110, the silicon-based panel 10 is also provided with the gate row driver circuit 120 and the source signal driver circuit 130 for addressing and driving the display region 110 to display an image. In the figure, for example, gate row driver circuits 120 are located on two sides of the display region 110, and the source signal driver circuit 130 is located on the lower side of the display region 110. In other embodiments, a gate row driver circuit 120 may also be disposed on only one side of the display region. In this embodiment, the gate row driver circuits 120 on two sides may drive gate scanning lines 112 of odd and even rows respectively or may be connected to two ends of the same gate scanning line 112 for synchronous driving. The gate row driver circuit 120 sequentially provides a gate scanning signal to the multiple gate scanning lines 112 to turn on the pixel units 11 of the rows corresponding to the multiple gate scanning lines 112. At the same time, the source signal driver circuit 130 sequentially provides a data signal to the multiple data signal lines 111, so that the multiple pixel units 11 are displayed at target brightness, thereby forming the entire target image.
The process in which the source signal driver circuit 130 and the gate row driver circuit 120 drive the display region 110 to display is essentially that after image data is input from the outside, the image data is converted into a timing signal and a data signal, provided to the gate row driver circuit 120 and the source signal driver circuit 130 respectively, and then transmitted to corresponding signal lines of the display region 110 by the gate row driver circuit 120 and the source signal driver circuit 130.
For the reception and processing functions of the image data input from the outside, in this embodiment of the present application, these functions are concentrated on the logic control board 30. Specifically, in this embodiment of the present application, the logic control board 30 is electrically connected to the silicon-based panel 10 by the encapsulation method of a chip on film (COF) substantially. The logic control board 30 is attached to the flexible circuit board 20 as a chip, and the flexible circuit board 20 is bonded to the first bonding region 141 of the silicon-based panel 10. In this manner, the flexible circuit board 20 receives external image data, is responsible for processing the image data, and then inputs the processed data signal from the flexible circuit board 20 to the silicon-based panel 10 for display and driving. The first bonding region 141 is a region disposed outside the display region 110 of the silicon-based panel 10 and is responsible for being connected to an external structure by an external connection device such as the flexible circuit board 20.
In this embodiment, in addition, when the logic control board 30 is responsible for the high-speed data reception function and high-speed data processing function, the logic control board 30 is responsible for need to be provided with the timing control module 31 and the algorithm processing module 32. The algorithm processing module 32 is configured to perform data processing. The timing control module 31 is responsible for generating a timing control signal. The first input interface module 33 and the first output interface module (TX) 34 are responsible for receiving the image data input from the outside and outputting the timing control signal to the silicon-based panel 10 respectively. The power module 35 is responsible for supplying power to the module on the logic control board 30.
As described above, in this embodiment of the present application, essentially, the functional units required for high-speed data reception, high-speed data processing, high-speed image compression, and high-speed image processing in the silicon-based display assembly are integrated on an independently prepared logic control board 30, and the electrical connection is implemented through a chip on film. At this time, the silicon-based panel 10 and the logic control board 30 may be manufactured as independent chips through production lines of different process capabilities. Specifically, considering that the logic control board 30 needs to perform high-speed data processing, there is a data processing speed requirement. Thus, a relatively high-level process technology, such as 28-nanometer process technology, may be used for preparation to ensure that the chips 30 are prepared in a smaller area and have a higher yield. For the silicon-based panel 10, the area of the silicon-based OLED having high resolution is relatively large, and the corresponding preparation requirement is relatively low. Thus, a relatively low-level process technology, such as 55-nanometer process technology, may be used for preparation to implement the object of reducing costs.
In the technical solution of the preceding embodiment, the silicon-based display assembly is provided with a silicon-based panel, a flexible circuit board, and a logic control board. The silicon-based panel includes a display region, a gate row driver circuit, a source signal driver circuit, and a first bonding region. The display region includes multiple data signal lines and multiple gate scanning lines. The multiple data signal lines are arranged in sequence in the first direction and extend in the second direction. The multiple gate scanning lines are arranged in sequence in the second direction and extend in the first direction. The display region also includes multiple pixel units formed by the intersection of the data signal lines and the gate scanning lines. The gate row driver circuit is configured to provide the gate scanning signal to the gate scanning lines. The source signal driver circuit is configured to provide the data signal to the data signal lines. The first direction and the second direction are two directions arbitrarily intersecting on the plane where the silicon-based panel is located. The flexible circuit board has an end bonded to the first bonding region. The logic control board is disposed on the flexible circuit board. The logic control board is integrated with a timing control module, an algorithm processing module, a first input interface module, a first output interface module, and a power module. The logic control board is configured to at least perform high-speed data receiving and high-speed data processing.
Referring to
In summary, this embodiment of the present application solves the problem that the elongated design of the display driver chip in the silicon-based display assembly is not conducive to the layout of a high-speed portion. Thus, the logic control board that requires image compression, image processing, and image algorithm functions can be no longer limited by the long strip-shaped bonding region on the silicon-based panel and may be freely designed in shape to implement a relatively square layout. In this manner, it is beneficial to reduce design and manufacturing difficulties, simplify the complexity of the manufacturing process, save costs, and reduce the occupied area, which is more applicable to miniaturized and micro-miniaturized display.
The shift register module 131, the line buffer module 132, the level shift module 133, the digital-to-analog conversion module 134, and the data signal operation (OP) amplifier module 135 are electrically connected in sequence. The second input interface module 136 is electrically connected to the shift register module 131. The gamma voltage generation module 137 is electrically connected to the digital-to-analog conversion module 134. The communication protocol of the second input interface module 136 matches the communication protocol of the first output interface module 34.
Since the logic control board 30 is responsible for performing high-speed data receiving and high-speed data processing, the interface module integrated on the logic control board 30 needs to be set as a high-speed interface. For the silicon-based panel 10, the data signal output process of the source signal driver circuit 130 on the silicon-based panel 10 is relatively low in data transmission speed. Thus, in a specific embodiment of the present application, optionally, the first input interface module 33 is a high-speed interface module, and the first output interface module 34 and the second input interface module 136 are low-speed interface modules. More specifically, the high-speed interface module may select interfaces such as a MIPI interface and an eDP interface. A low-speed interface module may select interfaces such as a LVDS interface and a P2P interface. The MIPI interface refers to a mobile industry processor interface (MIPI) alliance interface. The eDP interface refers to an embedded display port (eDP). The LVDS interface refers to a low voltage differential signaling (LVDS) interface. The P2P interface refers to a point-to-point (P2P) signaling interface. Relatively speaking, the transmission rate of the MIPI interface and the transmission rate of the eDP interface are far higher than the transmission rate of the LVDS interface and the transmission rate of the P2P interface, so that the MIPI interface and the eDP interface may be used for transmitting high-speed data to the outside.
The workflow of each module in the source signal driver circuit 130 in
Further referring to
The source signal driver circuit 130 is integrated in the source signal driver chip 40. The source signal driver chip 40 includes a shift register module 131, a line buffer module 132, a level shift module 133, a digital-to-analog conversion module 134, a data signal operation amplifier module 135, a second input interface module 136, and a gamma voltage generation module 137.
The shift register module 131, the line buffer module 132, the level shift module 133, the digital-to-analog conversion module 134, and the data signal operation amplifier module 135 are electrically connected in sequence. The second input interface module 136 is electrically connected to the shift register module 131. The gamma voltage generation module 137 is electrically connected to the digital-to-analog conversion module 134. The communication protocol of the second input interface module 136 matches the communication protocol of the first output interface module 34.
In this embodiment, the silicon-based panel 10 also includes a second bonding region 142. The second bonding region 142 includes multiple pads 1421. The source signal driver chip 40 is bonded to the silicon-based panel 10 through the pads 1421.
Similarly, in the embodiment, optionally, the first input interface module 33 is a high-speed interface module, and the first output interface module 34 and the second input interface module 136 are low-speed interface modules. More specifically, the high-speed interface module may select interfaces such as a LVDS interface and a P2P interface. A low-speed interface module may select interfaces such as a MIPI interface and an eDP interface.
In the preceding embodiment, as shown in
The analog memory region 150 is integrated with an analog memory circuit (AMC) 151. The analog memory circuit (AMC) 151 is configured to store, in a first stage, the data signal generated by the source signal driver circuit 130 and transmitted to the data signal lines 111.
The buffer region 160 is integrated with a buffer circuit 161. The buffer circuit 161 is electrically connected to the analog memory circuit (AMC) 151 and the data signal lines 111. The buffer circuit 161 is configured to be transmitted, in a second stage, the data signal stored in the analog memory circuit (AMC) 151 to the data signal lines 111.
The first stage and the second stage are two non-overlapping stages in the driving process of the pixel units 11.
Further referring to
Each storage unit 1510 includes a first switch 1511, a node stabilization unit 1512, and a memory sub-unit 1513. The first switch 1511 is electrically connected to the memory sub-unit 1513 and the source signal driver circuit 130. The first switch 1511 is electrically connected to the memory sub-unit 1513 at a first node N1. The memory sub-unit 1513 is also electrically connected to the node stabilization unit 1512 at a second node N2 and a third node N3. The node stabilization unit 1512 is also electrically connected to the buffer circuit 161 at the third node N3. A fourth switch 1514 is electrically connected between the third node N3 and the node stabilization unit 1512.
The data driving process of the pixel units 11 includes a first stage t10 and a second stage t20. The first switch 1511 is configured to be turned on in the first stage t10 to control the data signal provided by the source signal driver circuit 130 to write into the first node N1 and store in the memory sub-unit 1513. The node stabilization unit 1512 is configured to be turned on in the first stage t10 to control the voltage of the second node N2 and the voltage of the third node N3 to maintain at a first voltage and control the data signal stored in the memory sub-unit 1513 to provide to the third node N3 in the second stage t20.
In two adjacent pixel units 11 electrically connected to the same data signal line 111, the pixel unit 11 located in a previous row is the pixel unit 11 in the n-th row, and the pixel unit 11 located in a following row is the pixel unit 11 in the (n+1)th row. n is a positive integer. The first memory unit 1510A is configured to control the data signal of the pixel unit 11 in the n-th row to be transmitted to the buffer circuit 161. The second memory unit 1510B is configured to control the data signal of the pixel unit 11 in the (n+1)th row to be transmitted to the buffer circuit 161. The second stage t20 in the data driving process of the pixel unit 11 in the n-th row at least partially overlaps with the first stage t10 in the data driving process of the pixel unit 11 in the (n+1)th row.
Further referring to
The node stabilization unit 1512 includes an operational transconductance amplifier 15121, a second switch 15122, and a third switch 15123. The non-inverting input terminal of the operational transconductance amplifier 15121 is electrically connected to a reference voltage source Vref1. The inverting input terminal of the operational amplifier 121 is electrically connected to the second node N2. The output terminal of the operational transconductance amplifier 15121 is electrically connected to the third node N3. The third switch 15123 is electrically connected between the second node N2 and the third node N3. The second switch 15122 is electrically connected between the first node N1 and the third node N3. The third switch 15123 is configured to be turned on in the first stage t10 to enable the voltage of the second node N2 and the voltage of the third node N3 to be the same. The second switch 15122 is configured to be turned on in the second stage t20 to enable the voltage of the first node N1 and the voltage of the third node N3 to be the same.
Each memory unit 1510 also includes a fourth switch 1514. The fourth switch 1514 of the first memory unit 1510A is configured to be turned on in the second stage in the data driving process of the pixel unit in the n-th row. The fourth switch 1514 of the second memory unit 1510B is configured to be turned on in the second stage in the data driving process of the pixel unit in the (n+1)th row.
Referring to
The second stage t20 includes a first sub-stage t21 and a second sub-stage t22 in succession. The first sub-stage t21 is located between the first stage t10 and the second sub-stage t22. The fifth switch 1612 is configured to be turned off in the first sub-stage t21 and turned on in the second sub-stage t22 to control the signal of the third node N3 to be transmitted to the non-inverting input terminal of the first operational amplifier 1611.
The sixth switch 1613 is electrically connected between a precharge voltage signal terminal Vref2 and the non-inverting input terminal of the first operational amplifier 1611. The sixth switch 1613 is configured to be turned on during a period between the start occasion of the first stage t10 and the end occasion of the first sub-stage t21 to enable the precharge voltage signal vref2 of the precharge voltage signal terminal Vref2 to be provided to the non-inverting input terminal of the first operational amplifier 1611.
Referring to
In the first stage t10_A in the data driving process of the pixel unit 11 in the n-th row, the scanning signal Scan(n) in the n-th row is at logic high level, and the pixel unit 11 in the n-th row is in an off state. At the same time, in the first memory unit 1510A, k1 is at logic high level, the first switch 1511 is turned on, and the data signal provided by the source signal driver circuit 130 is written into the first node N1 and stored in the first capacitor C1; k2 is at logic low level, and the second switch 15122 is turned off, k3 is at logic high level, the third switch 15123 is turned on, and the voltage of the second node N2 is consistent with the voltage at the output terminal of the operational transconductance amplifier 15121 and is stabilized to be the sum of the reference voltage Vref1 at a non-inverting input terminal and the offset voltage Vos of the operational transconductance amplifier 15121, that is, Vref1+Vos; and k4 is at logic low level, and the fourth switch 1514 is turned off.
In the second stage t20_A in the data driving process of the pixel unit 11 in the n-th row, the scanning signal Scan(n) in the n-th row is at logic low level, and the pixel unit 11 in the n-th row is in an on state. At the same time, in the first memory unit 1510A, k1 is at logic low level, and the first switch 1511 is turned off, k2 is at logic high level, the second switch 15122 is turned on, k3 is at logic low level, k4 is at logic high level, the first node N1 is short-circuited with the third node N3, and the data signal stored in the first capacitor C1 in the first stage t10_A is provided to the third node N3; and k5 changes from logic low level to logic high level, k6 changes from logic high level to logic low level, the fifth switch 1612 is switched from the off state to the on state, the sixth switch 1613 is switched from the on state to the off state, and the data signal of the third node N3 is amplified by the first operational amplifier 1611 and then written into the pixel unit 11 in the n-th row.
In the first stage t10_B in the data driving process of the pixel unit 11 in the (n+1)th row, the scanning signal Scan(n+1) in the (n+1)th row is at logic high level, and the pixel unit 11 in the (n+1)th row is in an off state. At the same time, in the second memory unit 1510B, k1′ is at logic high level, the first switch 1511 is turned on, and the data signal provided by the source signal driver circuit 130 is written into the first node N1 and stored in the first capacitor C1; k2′ is at logic low level, and the second switch 15122 is turned off; k3′ is at logic high level, the third switch 15123 is turned on, and the voltage of the second node N2 is consistent with the voltage at the output terminal of the operational transconductance amplifier 15121 and is stabilized to be the sum of the reference voltage Vref1 at the non-inverting input terminal and the offset voltage Vos of the operational transconductance amplifier 15121, that is, Vref1+Vos; and k4′ is at logic low level, and the fourth switch 1514 is turned off.
In the second stage t20_B in the data driving process of the pixel unit 11 in the (n+1) th row, the scanning signal Scan(n+1) in the (n+1)th row is at logic low level, and the pixel unit 11 in the (n+1)th row is in an on state. At the same time, in the second memory unit 1510B, k1′ is at logic low level, and the first switch 1511 is turned off; k2′ is at logic high level, the second switch 15122 is turned on, k3′ is at logic low level, k4′ is at logic high level, the first node N1 is short-circuited with the third node N3, and the data signal stored in the first capacitor C1 in the first stage t10_B is provided to the third node N3; and k5 changes from logic low level to logic high level, k6 changes from logic high level to logic low level, the fifth switch 1612 is switched from the off state to the on state, the sixth switch 1613 is switched from the on state to the off state, and the data signal of the third node N3 is amplified by the first operational amplifier 1611 and then written into the pixel unit 11 in the (n+1)th row.
It can be seen that in this embodiment of the present application, the second stage t20_A of the pixel unit 11 in the n-th row overlaps the first stage t10_B of the pixel unit 11 in the (n+1) th row, so that in the case where a memory unit 1510, that is, the first memory unit 1510A, performs the second stage operation, another memory unit 1510, that is, the second memory unit 1510B performs the first stage operation. In this manner, it can be ensured that data signals may be written into two adjacent rows of pixel units 11 of the data signal line 111 in sequence with a short time interval or even without a time interval, thereby saving the writing time of the data signals and improving the input efficiency.
In addition, in the first part of the time period in the second stage t20_A in the data driving process of the pixel unit 11 in the n-th row and in the first part of the time period in the second stage t20_B in the data driving process of the pixel unit 11 in the (n+1)th row, k5 is at logic low level, k6 is at logic high level, the fifth switch 1612 is turned off; and the sixth switch 1613 is turned on, the precharge voltage signal of the precharge voltage signal terminal Vref2 is amplified by the first operational amplifier 1611 and then used to pre-charge the pixel unit 11 of the n-th row. In this manner, not only the data signal of the previous frame may prevent from affecting the display of the next frame, thereby improving the display effect, but also the writing speed of the data signal may be improved.
Further referring to
Optionally, a time period between an occasion t3 and an occasion t4 may also be set. k1, k2, and k3 are all at logic low level. The first switch 1511, the second switch 15122, and the third switch 15123 are all turned off. Further, the voltage at two terminals of the first capacitor C1 remains unchanged.
Referring to
In this embodiment, the power module 50, the oscillator (OSC) 60, the phase-locked loop (PLL) 70, and the one-time programmable memory (E-FUSE) 80 are also disposed on the silicon-based panel. Since the manufacturing technique of these modules or circuits is consistent or close to the manufacturing technique of the pixel units in the display region, compared with the source signal driving portion and the image data receiving and processing portion which have complex processes and require precision and are manufactured in the form of independent chips, these modules or circuits have lower technique requirements and do not require a manufacturing process with strong technique capabilities to be manufactured, thereby simplifying the technique and saving costs.
The driving architecture provided in this embodiment of the present application is a high-resolution and high-frame-rate driving system architecture and is particularly suitable for a silicon-based micro display panel. The silicon-based micro display panel is suitable for near-eye display such as virtual reality (VR) display and augmented reality (AR) display. The panel size of silicon-based micro display panel is very small, only the size of a coin. The images displayed by the silicon-based micro display panel need to be amplified by an optical magnification system. At the same time, the pixel size of the silicon-based micro display panel is much smaller than the pixel size of a traditional pixel. In the case of near-eye display, the human eye cannot distinguish individual pixels, thus avoiding the influence of screen-door effect, that is, the silicon-based micro display panel requires high resolution. The silicon-based micro display panel also has high-frame-rate requirements. In the near-eye display, the human eye cannot distinguish the pause between two frames, and the smooth, delicate, and clear display effect is provided.
An embodiment of the present application provides a display device.
It is to be noted that the preceding are only optional embodiments of the present application and the technical principles used therein. The present application is not limited to the embodiments described herein. Various apparent modifications, readjustment, combinations, and substitutions can be made without departing from the scope of the present application. Therefore, while the present application is described in detail in connection with the preceding embodiments, the present application is not limited to the preceding embodiments and may include equivalent embodiments without departing from the concept of the present application. The scope of the present application is determined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311474471.1 | Nov 2023 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/135565 | 11/30/2023 | WO |
