The present invention relates to a method of fabricating a semiconductor die with a microlens associated therewith. More particularly, the present invention relates to a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments.
Optoelectronic systems used for optically communicating between device's typically consist of a driver, an optical light emitting device such as a VCSEL, light coupling elements such as mirrors, gratings and optical waveguides for transporting optical signals from one point to another. An assembly of such optoelectronic system comprises fabricating waveguides and coupling elements on top of a substrate such as a printed wiring board (PWB) and then attaching a VCSEL device on top of such a substrate. The optical light emitted from the VCSEL is coupled into a waveguide on the substrate and is guided in-plane from one side of the substrate to other devices. It is very difficult and often impractical to integrate all of the components of the optoelectronic system such as driver and VCSEL onto a PWB substrate especially when the operating frequencies are beyond the GHz range. An alternate substrate such as silicon eases many of the integration complexities and provides a very high speed solution. A high performance computing system can be created by compactly integrating high speed driver and VCSEL components on a silicon substrate and maintaining optical communication through wave guides on the PWB. This scheme requires being able to couple light from one side of the silicon substrate to the other so that it can be coupled to a waveguide on the PWB.
The present invention enables crucial integration of optical and electronic components on a single substrate that is needed for inter chip optical communication through a backplane. This is done by being able to effectively couple light (used for optical communication) from sources mounted on one side of the substrate to waveguiding elements that may be located on the other side of the same substrate or a completely independent substrate.
The object of the present invention is to provide a means of transferring, coupling and or focusing light from an EO device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate.
It is understood that the same elements may also be used to transfer or couple from the waveguiding medium below the semiconductor substrate up through the substrate to a photodiode on top for detection and conversion into electrical signals. Additionally, the same elements described may be used to transfer or couple light from a waveguiding medium at one surface of the substrate to another waveguiding medium on the opposite side of the substrate.
It is an object of this invention that the high alignment accuracies afforded by standard semiconductor fabrication processes are exploited such to obviate the need for active alignment of the optical coupling or light guiding elements.
a-1d are sectional side views of an embodiment showing process steps to fabricate vertical channel guide optical via;
a-2c are sectional side views of an alternate embodiment showing process steps to fabricate vertical channel guide optical via thru a silicon core;
a-3d are sectional side views of an alternate embodiment showing process steps to fabricate electro-optical via;
a-4d.2 are sectional side views of an embodiment showing process steps to fabricate vertical channel guide optical via with directing elements on the backside;
a-5i are sectional side views of an alternate embodiment showing process steps to fabricate vertical channel guide optical via with lens elements;
a-6d are sectional side views of an alternate embodiment showing process steps to fabricate vertical channel guide optical via with a discrete index gradient guiding pillar;
a-7f are sectional side views of an alternate embodiment showing process steps to fabricate vertical channel guide optical via with discrete index gradient layers on a support pillar;
a-10e are sectional views of an alternate embodiment showing attached microlenses;
a-11c illustrates the use of an electro-optical module attached to a print circuit.
Referring to the drawings more particularly by reference numbers, sectional side views of process steps sequence to fabricate vertical channel guide optical via are shown in
While the examples herein disclose silicon as the substrate, other elements/compounds can conveniently form the substrate. For example, in addition to silicon, germanium, indium phosphide, silicon/germanium, gallium arsenide, glass, quartz, sapphire and silicon carbide can be used to form the substrate.
The thru via 10 shown in
The terms “low” and “high” are used to describe the relative index of refraction of material. When a low index of refraction material is adjacent to a relatively high index of refraction material, light approaching the interface from the higher index material side intersecting the interface under the critical angle is internally reflected as defined by Snell's Law. Thus for a ray of light refracted at a surface separating two media, the ratio of the sine of the angle of incidence to the sine of the angle of refraction is constant and is known as the angle of refraction for the two media. In this way, light is guided within “high” index of refraction materials when surrounded by relatively “low” index materials. The “core” of light guiding elements is therefore selected to be formed from materials possessing a high index of refraction, while the “clad”, or surrounding materials, are selected to be low index of refraction materials. In the present invention it happens that the core and the clad materials can be identical; i.e., silicon dioxide or a polymer selected from the group consisting of acrylate polymers, siloxane polymers and vapor deposited polymers.
The emphasis is not on the material per se, but rather the index of refraction possessed by the two materials which are adjacent to each other in the system. In the present invention, the index difference (Δn) between high and low index of refraction material can vary between about 0.01 and about 2, depending on specific system design. For example, a high index core material may have a refractive index of 2, whereas the complimentary low index material may have a refractive index of 1.5.
An optical communication device 15 is aligned with the via, and is attached on top of the vertical guide optical via as shown in
There are light emitting and receiving elements which are aligned to the vertical optical guide. In all of the embodiments disclosed herein, the light emitting element can be a light emitting carbon nanotube, vertical cavity surface emitting laser (VCSEL), LED, edge emitting laser, external laser source, wave guiding element and optical fiber. Suitable light receiving elements are a photodetector and a photoreceiver.
a-2c are sectional side views of an alternate embodiment of the present invention showing process steps to fabricate a vertical channel guide optical via 20 thru silicon core 21.
Several of the embodiments of the present invention employ “annular vias.” As used herein, an “annular via” refers to the volume generated when a rectangle of desired base is rotated about a vertical central axis which central axis is the diameter in the center of a “core” element.
Annular via comprising 20 and 20′ may be etched in silicon 21 as shown in
An optical communication device 26 may be aligned and attached on top of the vertical guide optical via 20, 20′ as shown in
a-3d are sectional side views of an alternate embodiment showing process steps to fabricate an electro-optical via. Annular via 30 is etched in silicon substrate 31 as shown in
As shown in
During the process of forming an electrical connection, the silicon substrate may be temporarily attached to an adhesive substrate such as commercially available sheet adhesives or other substrate. Additional photolithographic processes may be performed on the backside of silicon substrate. These processes may involve defining a pattern, etching the silicon substrate, passivating the silicon substrate backside surface, forming electrical contacts by means of depositing, plating, or screening metals or otherwise electrically conductive material 36 such as solder. An optical communication device 38 may be aligned and attached on top of electro-optical via as shown in
a-4d.2 are sectional side views of an alternate embodiment showing process steps to fabricate a vertical channel guide optical via 40 through silicon core 41 where the back side 42 of via 40 is patterned to introduce refractive (e.g. lens) or diffractive (e.g. grating) elements. Via 40 is formed by known processes in a silicon substrate 41 as shown in
a-5i are sectional side views of an embodiment showing the process steps to fabricate vertical channel guide optical via 50 through silicon substrate core 51 where a lens is incorporated into via 50. There are two processes to form such a structure shown separately in
The key property of the aforementioned materials is that they are resistant to processes used to etch silicon. Many materials can be chosen for this layer 52, including polymers such as polyimide or vapor deposited polymers and inorganic layers such as silicon nitride. Etch resistant material 52 may be optically transparent as well. If this material is not optically transparent, this layer must be removed prior to use (step not shown). Preferably, a silicon nitride layer or silicon oxide layer may be used as the “etch stop” layer depending on the process used in further steps to etch the silicon. Via 50 is then filled to the surface thereof with transparent material 53 as shown in
A planarization step (not shown) may be used to produce a planar surface at the top of the via, but may not be needed because of the use of an optical underfill such as a transparent epoxy. The back side 54 of silicon substrate 51 is then etched to open the bottom side 55 of via 50. This etch may be a dry etch or a wet etch, and must stop on the etch stop layer 52 on the curved surface 56 at the base of via 50 shown in
In the second of these process sequences, via 50 is formed as before by known processes in a silicon substrate core 51. Via 50 is first partially etched in the silicon substrate 51 to desired depth using a known process. A thin layer of etch resistant material 52 is then deposited. The key property of this material is that it resistant to processes used to etch silicon. A silicon nitride layer or silicon oxide layer may be used for this depending on the process used in further steps to etch silicon. These steps are shown before in
The deposition of the second etch resistant layer 520 and transparent material 53 is shown in
An optical communication device 57 is then aligned and attached on top of the vertical guide optical via as shown in
a-6d are sectional side views of an alternate embodiment showing process steps to fabricate a vertical channel guide optical via through a discrete index gradient guiding pillar. Annular via 60 may be etched in a silicon substrate as shown in
a-7f are sectional side views of an alternate embodiment showing process steps to fabricate vertical channel guide optical via thru a discrete index gradient support pillar. Annular via 70 may be etched in a silicon substrate 7l as shown in
Silicon oxynitride is appropriate for use in these layers because of the ability to control the index of the deposited layer over a wide index range of from about 1.45 to about 2.0. Various polymers such as polyimide or siloxane polymers or vapor deposited polymers can also be used. The layers are deposited sequentially with each layer having a decreasing index until the diameter is sufficiently large to capture all of the light generated later during use. A thick silicon dioxide layer may be thermally grown or vapor deposited as the first layer prior to sequentially depositing layers 731, 732, 733, etc. from silicon pillar 72. When the desired radial dimension of the support pillar and guiding layers is attained, the remaining open regions are filled with material 70′ having a low refractive index.
The top layer may be planarized using conventional chemical mechanical polishing tools easily available in most silicon processing lines as shown in
One possible index profile is shown in
Though not exclusively mentioned in these embodiments, electrical wiring levels may be built on the silicon substrate prior to attaching any optical devices. Other form of electrical devices such as ICs, passive devices, or other devices may also be attached on the silicon substrate and interconnected by use of the wiring levels on the substrate. Additionally, the via structures described above may be formed from the top or the bottom side of the silicon substrate, implying the ability to make such structure in both orientations to light transmitting and receiving surfaces.
n(r)=n0+nr1r2
where the center index n0=1.54, the gradient parameter nr1=−10, and where the radius r=0 to 0.125 mm. By changing the nature of the radial gradient it is also possible to focus the light from a VCSEL directly into a waveguide structure.
The structure embodied in
As an example, for a 1.3 micron wavelength VCSEL, with a VCSEL to microlens distance of 500 microns, and with a microlens radius of 360 microns the light from the VCSEL is approximately collimated by the microlens.
The microlens may be fabricated by standard semiconductor fabrication means. For example a gray scale mask may be used to expose a layer of photoresisit on the Si substrate, followed by a RIE process to define the microlens surface.
a-10e show cross sectional views of an alternate embodiment of a semiconductor die with attached microlenses. In
In all of these embodiments, the objective is to take advantage of the precision of the silicon etch process and define feature (such as the thru via) to which the attached microlens array may be referenced. By having these highly accurate reference features the microlens array may be simply and accurately attached to the silicon substrate in a passive manner, leading to a highly accurate, low cost assembly.
a-11c illustrate how the silicon carrier electro-optic module may be used in a system. In
Waveguide structure 114 then channels this light across printed circuit board 1100 to a receiving electro-optic module to be converted back to electrical signaling. The receiving electro-optical has a similar structure as that shown with a phototdetector (PD) in place of the VCSEL. The optical via in embodiments 1 through 10 herein in the electro-optical module fabricated in silicon performs the critical function of conveying the light energy from VCSEL 112 to the waveguide structure 114 to a photodetector on a silimar electro-optical module.
In
In
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art.
This application is a divisional application of U.S. Non-Provisional application Ser. No. 10/675,139, filed Sep. 30, 2003, which issued as U.S. Pat. No. 7,352,066, and claims the benefit of priority pursuant to 35 U.S.C. §120.
Number | Name | Date | Kind |
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6777715 | Geusic et al. | Aug 2004 | B1 |
Number | Date | Country |
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WO 2005031417 | Apr 2005 | WO |
Number | Date | Country | |
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20100322551 A1 | Dec 2010 | US |
Number | Date | Country | |
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Parent | 10675139 | Sep 2003 | US |
Child | 12080266 | US |