Patent Application
20250126817
The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers and methods of manufacture.
A silicon controlled rectifier (SCR) is a solid-state current-controlling device, which can be a unidirectional device (i.e., can conduct current only in one direction) or a bi-directional device. The An SCR is typically a three-terminal, three-junction, and four-layer semiconductor device that is used to perform switching functions in power circuits. That is, the SCR typically includes a switching configuration comprising p-n-p-n layers.
A bi-directional SCR may be used as a primary electrostatic discharge (ESD) protection in a radio frequency (RF) pad. In such devices, though, the depletion regions at the interface of the P-wells and N-wells shrink and expand with a biasing signal voltage. The capacitance of the bi-directional SCR will also fluctuate with the application of the biasing signal voltage. This fluctuation, though, causes large harmonic distortions.
In an aspect of the disclosure, a structure comprises: a plurality of wells of a first conductivity type; a well of a second conductivity type which is different than the first conductivity type; an intrinsic semiconductor region between the well and the plurality of wells; and contacts within the plurality of wells.
In an aspect of the disclosure, a structure comprises: a plurality of P-wells; an N-well between the plurality of P-wells; an intrinsic semiconductor region between each of the P-wells and the N-well; a P+ region at an interface of each of the P-wells and the intrinsic semiconductor region; an N+ type region at an interface between the N-well and the intrinsic semiconductor; and contacts in the plurality of P-wells.
In an aspect of the disclosure, a method comprises: forming a plurality of wells of a first conductivity type; forming a well of a second conductivity type which is different than the first conductivity type; and forming an intrinsic semiconductor region between the well and the plurality of wells.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers (SCR) and methods of manufacture. More specifically, the present disclosure relates to bi-directional SCRs. In embodiments, the bi-directional SCRs may be used in radio frequency electrostatic discharge protection circuits. Advantageously, the SCRs described in the present disclosure reduce harmonic distortions and reduce capacitance of the SCR in semiconductor-on-insulator (SOI) technologies.
In embodiments, the SCRs described herein comprise low-doped regions between P-wells and an N-well. In addition, highly doped P-type regions may be provided at the edges of the P-wells and highly doped N-type regions may be provided at the edges of the N-well. Contacts regions may be provided in the P-wells, which have higher doping concentrations than the highly doped regions. In embodiments, the contact regions may include P-type contact regions and N-type contact regions in different configurations.
The structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material layers as is known in the art.
The handle substrate 12a and the top semiconductor layer 12e may include a semiconductor material such as, for example, Si, SiGe, SiC, SiGeC, a III-V compound semiconductor, an II-VI compound semiconductor or any combinations thereof. In specific embodiments, the handle substrate 12a may preferably be a P-type Si substrate. The buried insulator layer 12b may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride or a combination thereof. In one embodiment, the buried insulator layer 12b may be a buried oxide layer (BOX) formed by a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition CVD (PECVD) or physical vapor deposition (PVD). In another embodiment, the buried insulator layer 12b may be formed using a thermal growth process, e.g., thermal oxidation, or by implanting oxygen atoms into a bulk semiconductor substrate and thereafter annealing the structure.
Typically, each of the handle substrate 12a and the top semiconductor layer 12c comprises a single crystalline semiconductor material, such as, for example, single crystalline silicon. The top semiconductor layer 12c may comprise any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). The top semiconductor layer 12c may be partially depleted. The top semiconductor layer 12c can be formed by a deposition process, e.g., CVD or PECVD, or a smart cut process as is known in the art such that no further explanation is required for a complete understanding of the present invention.
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In embodiments, the highly doped P+ regions 18 and highly doped N+ regions 20 have a higher dopant concentration than the P-wells 14 and the N-well 16. For example, the dopant concentration of the P-wells 14 and N-well 16 may be 1e18 cm−3 to 5e18 cm−3; whereas the dopant concentration of the highly doped P+ regions 18 and highly doped N+ regions 20 may be from about 1e19 cm−3 to 5e19 cm−3 or higher. It should be understood by those of skill in the art that other dopant concentrations are contemplated herein depending on the desired device performance of the SCR. The dopant concentration of the low-doped intrinsic layer 15 may be at the same concentration as the handle substrate 12a, e.g., 1e15 cm−3 to 2e15 cm−3.
Shallow trench isolation structures 28 may be provided in the N-well 16 and P-wells 14, in addition to over the highly doped P+ regions 18, highly doped N+ regions 20 and within or over the low-doped intrinsic layer 15. The shallow trench isolation structures 28 within the P-wells 14 may be used to isolate P+ contacts 22 and N+ contacts 24 within the P-wells 14. In this embodiment, the N+ contacts 24 within the P-wells 14 are closest to the N-well 16. In this embodiment, the top semiconductor layer 12c may be partially depleted semiconductor-on-insulator material.
The shallow trench isolation structures 28 can be formed by conventional lithography, etching and deposition methods known to those of skill in the art. For example, a resist formed over the top semiconductor layer 12c is exposed to energy (light) and developed utilizing a conventional resist developer to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern from the photoresist layer to the top semiconductor layer 12c to form one or more trenches in the top semiconductor layer 12c through the openings of the resist. Following the resist removal by a conventional oxygen ashing process or other known stripants, the insulator material (e.g., SiO2) can be deposited by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual material on the surface of the top semiconductor layer 12c can be removed by conventional chemical mechanical polishing (CMP) processes.
In embodiments, the P+ wells 14, N+ wells 16, P+ contacts 22, N+ contacts 24, highly doped P+ regions 18, and highly doped N+ regions 20 may be formed by ion implantation processes. For example, the wells and contacts may be formed by introducing a concentration of a different dopant types in the top semiconductor layer 12c. In embodiments, respective patterned implantation masks may be used to define selected areas exposed for the implantations. For example, the implantation masks used to select the exposed area for P+ wells 14, N+ wells 16, P+ contacts 22, N+ contacts 24, highly doped P+ regions 18, and highly doped N+ regions 20 may be stripped after implantation, and before the implantation mask used to form other features. The implantation masks may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. Each of the implantation masks has a thickness and stopping power sufficient to block masked areas against receiving a dose of the implanted ions. The P+ wells 14, P+ contacts 22 and highly doped P+ regions 18 may be doped with p-type dopants, e.g., Boron (B), and the N+ wells, N+ contacts 24 and highly doped N+ regions 20 may be doped with n-type dopants, e.g., Arsenic (As), Phosphorus (P) and Sb, among other suitable examples.
Terminals 30, 32 may be formed to the P+ contacts 22 and N+ contacts 24 and, more specifically, to the silicide contacts 26 on the P+ contacts 22 and N+ contacts 24. The terminals 30, 32 may be any back end of the line (BEOL) wiring structures known to those of skill in the art such that no further explanation is required for a complete understanding of the present disclosure. For example, the terminals 30, 32 may be aluminum, tungsten, etc. formed in an interlevel dielectric material using conventional CMOS processes.
The bi-directional silicon controlled rectifiers can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
