The disclosure relates to techniques for fabricating semiconductor devices and, more particularly, to non-volatile memories (NVM), especially those containing a trapping layer, such as nitride read only memory (NROM) or other microelectronic cells or structures.
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET a small amount of voltage is applied to the gate in order to control current flowing between the source and drain. In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a “conductor”).
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary “1”. If no charge is stored on the floating gate, this represents a binary “0”. (These designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single “charge-storing area”—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary “1” or binary “0”). More recently, using a technology referred to as “multi-level cell” (MLC), two or more bits can be stored in and read from the floating gate cell.
Another type of memory cell, called a “nitride, read only memory” (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary “1” or binary “0”) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary “1” or binary “0”) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified. Other memory cells which are explicitly and specifically contemplated within the scope of the present disclosure include SONOS (Silicon Oxide Nitride Oxide Semiconductor), MONOS (Metal Oxide Nitride Semiconductor), and TANOS (Tantalum Nitride Oxide Semiconductor) all of which usually have one bit per cell without MLC technology (rather than the NROM two bits per cell without MLC) as well as split-gate (two separate nitride regions associated with the gate or channel) which usually has two bits per cell without MLC technology, all of which have a trapping layer, which is usually Nitride.
The ONO structure is a stack (or “sandwich”) of bottom (lower) oxide 322, a charge-trapping material such as nitride 324, and a top (upper) oxide 326. The ONO structure may have, for example, an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate between the two diffusion regions 314 and 316, and a gate 328 disposed above the ONO stack 321.
In
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
The memory cell 300 is generally capable of storing at least two bits of data—at least one bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 321. Thus, the NROM memory cell can be considered to comprise two “half cells”, each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term “half cell”, as it may be used herein, is used herein only to refer to the “left” or “right” bit storage area of the ONO stack (nitride layer). The storage areas 321, 323 may variously be referred to as “charge storage areas”, “charge trapping areas”, and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left “bits”.)
Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary “1”, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary “0”. (Again, these designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is.
Generally, one feature of NROM cells is that rather than performing “symmetrical” programming and reading, NROM cells are beneficially programmed and read “asymmetrically”, which means that programming and reading occur in opposite directions. The arrows labeled in
Other similar charge trapping cells, such as MONOS, SONOS, TANOS and others may use “forward read” or symmetrical programming, while some trapping cells (such as split-gate) may use “reverse read” (asymmetrical or “forward read” symmetrical).
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing “symmetrical” programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read “asymmetrically”, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bitlines may be “buried bitline” diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
Notice, for example that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL(n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”. In this example, the memory cells “e” and “f” have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
For example, a thin layer of metal salicide, such as cobalt silicide or titanium silicide or nickel salicide, may be formed atop the gate structure, and atop the source and drain diffusions (or two “agnostic” diffusions of an NROM cell). A dielectric layer may then be disposed over the entire device, to support upper level metalization such as wiring patterns, interconnects, word lines and bitlines which pass between several devices, as well as to external circuitry (not shown). This dielectric layer may be referred to as an inter level dielectric (ILD) layer.
Contacts must be opened through the ILD, to access the metal silicide, and effect contact with the gate (such as 328) and the two diffusions (such as 314 and 316). With reference to the diffusions, it is particularly important that, in the process of creating the contact, the underlying diffusion is not damaged. It is thereby known, and is common practice to first form a capping layer over the device, and said capping layer may act as an etch stop layer when etching the ILD to form the contacts.
The article entitled Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors, by Stephane Orain et al., IEEE Transactions on Electron Devices, Vol. 54, No. 4, April 2007, discusses stress in a nitride contact etch stop layer (CESL).
In some cases mechanical stress can be used advantageously to improve carrier mobility in a semiconductor device such as MOSFET (metal oxide semiconductor field effect transistor). In other cases, intrinsic mechanical stress can be disadvantageous, in the least since it may impose an undesired performance variable on the operation of the device.
NROM is one type of NVM cell commonly using a nitride charge trapping layer with an ONO stack structure. Data may be written in such memory cells by charging or discharging the nitride charge-trapping layer (such as 324,
During device fabrication, a device may be exposed to plasma processing such as etching, ashing and thin film formation. Electrical charges may be induced by such plasma processing, and these charges may cause damage to or threshold voltage differences between memory cells.
During device fabrication, a device may be exposed to high temperatures, such as 1000 deg-C. anneal, which may induce undesirable stresses from the nitride capping layer.
With regard to NVM cells using a nitride charge-trapping layer (such as NROM), the disclosers have found that using SiN liner as a contact etch stop layer (CESL) imposes stress when doing temperature ramp to 1000 deg-C. (temperature ramp is inherent in some of the processing steps following liner formation, some of which may have been mentioned above).
A liner film structure covering the gate of CMOS and memory cells typically uses SiN (or p-SiN) as a contact etch stopping layer (CESL). The liner film structure is one of the deposition process parameters for charging during device fabrication. However, it may be difficult to remove (eliminate) the liner film structure because of its beneficial role in contact etch.
It is known that the CESL liner material (nitride) alters the mechanical stress that builds up on the wafer during the fabrication (due to such steps as rapid thermal anneals that increase the temperature to 1000 deg-C. in few seconds and then back down to room temperature) and that can affect the physical properties of the memory cells
It is believed that such mechanical stress alters the ONO layer's immunity to hot carrier damage during cycling and hence can change (degrade) the NROM cell's ability to store the trapped charge (data).
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at “Non Volatile Memory Technology”, 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety.
Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NVM and related technologies may be found at “Non Volatile Memory Technology”, 2005 published by Saifun Semiconductor; “Microchip Fabrication”, by Peter Van Zant, 5th Edition 2004; “Application-Specific Integrated Circuits” by Michael John Sebastian Smith, 1997; “Semiconductor and Electronic Devices”, by Adir Bar-Lev, 2nd Edition, 1999; “Digital Integrated Circuits” by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd Edition, 2002 and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_sonos_lehigh_univ.pdf, “SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.pdf, “Philips Research—Technologies—Embedded Nonvolatile Memories” found at: http://www.research.philips.com/technologies/ics/nvmemories/index.html, and “Semiconductor Memory: Non-Volatile Memory (NVM)” found at: http://www.ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf, all of which are incorporated by reference herein in their entirety.
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the disclosure most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (®).
MOS short for metal oxide semiconductor.
MOSFET short for metal oxide semiconductor field-effect transistor. MOSFET is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material, and is accordingly called an NMOSFET or a PMOSFET. (The ‘metal’ in the name is an anachronism from early chips where gates were metal; modern chips use polysilicon gates, but are still called MOSFETs).
In addition to the above, some abbreviations that may be used herein, or in a provisional application from which this non-provisional application claims priority, include:
ILD short for inter-layer (or inter-level) dielectric, typically oxide.
IMD short for inter-metal dielectric, typically oxide.
RAC short for retention after cycling
Gm relates to transconductance (analogous to gain)
DVde delta Vde drain erase voltage gate fixed, negative
STI short for shallow trench isolation
Ld short for (channel) length drawn
ANL short for ANneaL
According to the disclosure, generally, an improved nitride liner is provided. Nitride (SiN) liners may be used as part of the IMD (inter metal dielectric) in optionally a copper process. Nitride liners may also be used as a contact etch stopping layer (CESL).
In the main hereinafter, nitride liners used in non-volatile memory (NVM) cells are discussed, and should be considered to be exemplary of other uses for the nitride liners disclosed herein.
According to the disclosure, generally, an improved contact etch stop liner (CESL) is provided, to reduce stress effects in NVM cells using a nitride charge-trapping layer (such as NROM).
The techniques disclosed herein may be applicable to most NVM devices including, but not limited to, NROM (sometimes referred to as Nitride Read Only Memory), SONOS (Semiconductor Oxide Nitride Oxide Semiconductor; Silicon-Oxide-Nitride-Oxide-Silicon), SANOS (Silicon-Aluminum Oxide-Nitride-Oxide-Silicon), MANOS (Metal-Aluminum Oxide-Nitride-Oxide-Silicon), TANOS (Tantalum-Aluminum Oxide-Nitride-Oxide-Silicon) and Floating Gate (FG) devices.
Generally, in one embodiment, SiON (silicon oxy-nitride) is used in lieu of SiN (silicon nitride), for the nitride liner or CESL. When SiON is used, intrinsic stress may be reduced. The SiON may be p-SiON (plasma-enhanced SiON deposition).
Generally, in another embodiment, a nitride (SiN) layer may be processed to be discontinuous, to reduce stress effects. This technique can also be used in conjunction with a silicon oxy-nitride (SiON) CESL.
Generally, in another embodiment, a CESL layer may be eliminated entirely, to reduce stress effects.
According to the disclosure, a non-volatile memory (NVM) cell may comprise: a channel defined between two diffusions in a semiconductor substrate; a charge storage stack or element disposed atop the channel; a gate electrode disposed atop the charge storage stack or element; and a contact etch stop layer (CESL) deposited as a thin film, covering the gate and diffusions; wherein: the CESL comprises silicon oxy-nitride (SiON). The NVM cell may be an NROM cell. The CESL may have a thickness in the range of 10 nm-200 nm, such as 20 nm-70 nm. The CESL may also cover the gate electrode. The CESL may extend as a continuous layer over the two diffusions and the gate electrode. The CESL may extend as a discontinuous layer over the two diffusions and the gate electrode and comprises a material selected from the group consisting of silicon oxy-nitride (SiON) and silicon nitride (SiN). The CESL may comprise separate segments over the two diffusions.
Reference will be made in detail to embodiments of the disclosure, examples of which may be illustrated in the accompanying drawing figures (FIGs). The figures are intended to be illustrative, not limiting. Although the disclosure is generally described in the context of these embodiments, it should be understood that it is not intended to limit the disclosure to these particular embodiments.
Certain elements in selected ones of the figures may be illustrated not-to-scale, for illustrative clarity. The cross-sectional views, if any, presented herein may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a true cross-sectional view, for illustrative clarity. In some cases, hidden lines may be drawn as dashed lines (this is conventional), but in other cases they may be drawn as solid lines.
If shading or cross-hatching is used, it is intended to be of use in distinguishing one element from another (such as a cross-hatched element from a neighboring un-shaded element. It should be understood that it is not intended to limit the disclosure due to shading or cross-hatching in the drawing figures.
Elements of the figures may (or may not) be numbered as follows. The most significant digits (hundreds) of the reference number correspond to the figure number. For example, elements of
Throughout the descriptions set forth in this disclosure, lowercase numbers or letters may be used, instead of subscripts. For example Vg could be written Vg. Generally, lowercase is preferred to maintain uniform font size. Regarding the use of subscripts (in the drawings, as well as throughout the text of this document), sometimes a character (letter or numeral) is written as a subscript—smaller, and lower than the character (typically a letter) preceding it, such as “Vs” (source voltage) or “H2O” (water). For consistency of font size, such acronyms may be written in regular font, without subscripting, using uppercase and lowercase—for example “Vs” and “H20”.
Conventional electronic components may be labeled with conventional schematic-style references comprising a letter (such as A, C, Q, R) indicating the type of electronic component (such as amplifier, capacitor, transistor, resistor, respectively) followed by a number indicating the iteration of that element (such as “1” meaning a first of typically several of a given type of electronic component). Components such as resistors and capacitors typically have two terminals, which may be referred to herein as “ends”. In some instances, “signals” are referred to, and reference numerals may point to lines that carry said signals. In the schematic diagrams, the various electronic components are connected to one another, as shown. Usually, lines in a schematic diagram which cross over one another and where there is a dot at the intersection of the two lines are connected with one another, else (if there is no dot at the intersection) they are typically not connected with one another.
Although various features of the disclosure may be described in the context of a single embodiment, the features may also be provided separately or in any suitable combination. Conversely, although the disclosure may be described herein in the context of separate embodiments for clarity, the disclosure may also be implemented in a single embodiment. Furthermore, it should be understood that the disclosure can be carried out or practiced in various ways, and that the disclosure can be implemented in embodiments other than the exemplary ones described hereinbelow. The descriptions, examples, methods and materials presented in the in the description, as well as in the claims, should not be construed as limiting, but rather as illustrative.
Generally, a charge storage stack 521 (compare 321), which may be an ONO stack, is disposed atop a channel 520 (compare 320) which is defined (located) between two (source or drain) diffusions 514 and 516 (compare 314 and 316) in a substrate 512 (compare 312). A gate electrode 528 (compare 328) is formed atop the ONO stack 521. Sidewall spacers 529 may be formed on opposite sides of the gate electrode 528. Further process steps, and structures resulting from the process steps will now be described, which generally involve structures 530 overlying the basic memory cell to provide for interconnect.
A layer of thin metal (cobalt or titanium or nickel) 532 may be deposited atop the diffusions 514 and 516, such as having a thickness in the range of 20 nm-200 nm. The metal is then silicided using a conventional salicidation process. (No patterning is necessary. Silicidation is self-aligned to the exposed silicon/poly-silicon.) The layer 532 also covers the gate 528, where it is labeled “534”. This layer 532 is generally for the purpose of reducing the sheet resistance of the diffusion and poly-silicon areas.
Next, a thin film cover liner 536 is deposited on the surface of the substrate 512, covering the entire NVM cell 500 (and neighboring cells on the wafer), including covering the gate electrode 528 and the two diffusions 514 and 516.
The cover liner 536 is deposited as a continuous layer, and may have a thickness in the range of 10 nm-200 nm.
Whereas a cover liner is typically (in the prior art) silicon nitride (SiN), according to an embodiment of the disclosure the cover liner 536 is formed as a continuous layer of silicon oxy-nitride (SiON), and may have a thickness in the range of 10 nm-200 nm such as 20 nm-70 nm.
SiON, as the chemical formulation implies, has oxygen incorporated into the silicon nitride film during the deposition process. Optionally, the oxygen is included by reacting N2O, NH3 and SiH4 in an N2 ambient. SiON exhibits less stress than Nitride and its contact etch stop properties can be tailored to correspond to that of silicon nitride. Besides its use as a passivation layer (it can be modified to allow or block UV transmission) it may also be used as gate oxide material (where it helps prevent boron out diffusion).
It may be noted that, when a thin film of SiON is applied as a liner structure, RAC characteristics may dramatically be improved, due to reduced stress and optionally protection from plasma induced charges.
Next, an inter-layer dielectric (ILD) layer 538 is disposed over the cover liner 536. The ILD layer 538 may be oxide (SiO2), deposited by a conventional oxide deposition process to a thickness in the range of 700 nm-1200 nm.
Next, contact openings (or “vias”) 540 are formed through the ILD layer 538, such as by using a conventional contact etch process. This process etches the ILD material, and proceeds down to the oxy-nitride cover liner 536, which functions as a “contact etch stop layer” (CESL). The dashed line towards the bottom of the opening 540 illustrates that the contact etch step stops on the CESL 536. A subsequent conventional etch step, such as using a dry plasma reactive ion etch, may be performed to etch through the CESL 536 at the bottom of the opening 540 and to etch stop on metal silicide or silicon. This is a conventional process. In this manner, the openings 540 (two shown) extend downward, completely through the ILD layer, to the diffusions 514 and 516 (or to the salicide 532 on the two diffusions).
Next, the opening 540 may be filled (plugged) with a conductive material which may be metal, such as tungsten, or with poly (polysilicon) using a conventional deposition process, with excess metal or poly overfilling the opening 540 being polished off, such as by using a conventional chemical-mechanical polishing process, or by an etch-back process or other similar processes. The conductive contact material is not specifically shown (it fills the opening 540), for illustrative clarity.
A conventional SiN contact etch stop layer (CESL) may develop stresses from subsequent high-temperature processes that adversely impact cell performance. For example, in a case where the liner (CESL) is deposited before the CMOS source/drain implant, the device may be subsequently subjected to a 1000 deg-C. implant anneal step. In other cases, such as when the liner is deposited during the BEOL (back end of line), a nitride liner may be deposited before every metal (such as copper) layer (there may be several metal layers).
Next, a metal layer 542 may be deposited atop the ILD 538, and patterned, using conventional deposition and lithography processes, for the purpose of connecting the cell 500 to other cells (not shown, see
Finally, a thick layer 544 of either oxide or nitride or oxy-nitride, or other passivating material may be deposited onto the metal layer 542. For example, in a single metal process, this would be the passivation layer that is used to protect the die during bonding and packaging. If it is a multi-metal process, then this would be a thin layer that is a precursor to the inter-metal dielectric (IMD) layer. This is, optionally, a representative of copper metallization. Silicon Oxy-Nitride (SiON), as disclosed herein, can be used in conjunction with an optional copper metallization.
Generally, in this embodiment, a nitride (SiN) contact etch stop layer (CESL) may be processed to be discontinuous, to reduce stress effects. This technique can also be used in conjunction with a silicon oxy-nitride (SiON) CESL. Generally, the liner can be cut, wherever it is flat and with adequate margins around contacts, using conventional photolithography techniques such as photoresist, masking, etching, and the like.
Generally, in
Generally, a charge storage stack 621 (compare 321, also 521), which may be an ONO stack, is disposed atop a channel 620 (compare 320, also 520) which is defined (located) between two (source or drain) diffusions 614 and 616 (compare 314 and 316, also 4\514 and 516) in a substrate 612 (compare 312, also 512). A gate electrode 628 (compare 328, also 528) is formed atop the ONO stack 621. Sidewall spacers 629 may be formed on opposite sides of the gate electrode 628. Further process steps, and structures resulting from the process steps will now be described, which generally involve structures 630 overlying the basic memory cell to provide for interconnect.
A layer of thin metal (cobalt or titanium or nickel) 632 may be deposited atop the diffusions 614 and 616 such as having a thickness in the range of 20 nm-200 nm. The metal is then silicided using a conventional salicidation process. (No patterning is necessary. Silicidation is self aligned to the exposed silicon/poly-silicon.) The layer 632 also covers the gate 628, where it is labeled “634”. This layer 632 is generally for the purpose of reducing the sheet resistance of the diffusion and poly-silicon areas.
Next, a thin film cover liner, generally designated 636, is deposited on the surface of the substrate 612, covering the entire NVM cell 600 (and neighboring cells on the wafer), including covering the gate electrode 628 and the two diffusions 614 and 616.
The cover liner 636 is deposited as a continuous layer, and may have a thickness in the range of 10 nm-200 nm.
The cover liner 636, which may act as a contact etch stop layer (CESL) may be silicon oxy-nitride (SiON), as discussed in the first embodiment, or may simply be conventional nitride (SiN).
After depositing the CESL 636, conventional photolithography techniques are used to pattern the layer 636 so that, rather than being continuous (as in the previous, first embodiment) it is segmented (discontinuous), having separate segments 636a and 636b of the CESL 636 remaining over the two diffusions, 614 and 616, respectively. Additionally, a segment 636c remains over the gate 628 (such as over the gate salicide 634).
Next, as in the previous (first) embodiment, an inter-layer dielectric (ILD) layer 638 is disposed over the cover liner 636. The ILD layer 638 may be oxide (SiO2), deposited by a conventional oxide deposition process to a thickness in the range of 700 nm-1200 nm.
Next, contact openings (or “vias”) 640 are formed through the ILD layer 638, such as by using a conventional contact etch process. This process etches the ILD material, and proceeds down to the oxy-nitride cover liner 636, which functions as a “contact etch stop layer” (CESL). The dashed line towards the bottom of the opening 640 illustrates that the contact etch step stops on the CESL 636. A subsequent conventional etch step, such as using a dry plasma reactive ion etch, may be performed to etch through the CESL 636 at the bottom of the opening 640 and to etch stop on silicon. This is a conventional process.
Next, the opening 640 may be filled (plugged) with metal, such as tungsten, or with poly (polysilicon) using a conventional deposition process, with excess metal or poly overfilling the opening 640 being polished off, such as by using a conventional chemical-mechanical polishing process, or by an etch-back process or other similar processes. This is a conventional process, and although the CESL 636 is shown at the bottom of the opening 640, it will be understood that it is removed prior to the next step of filling the opening with a conductive contact material. The conductive contact material is not specifically shown (it fills the opening 640), for illustrative clarity.
Because the CESL layer is segmented, although individual segments may accumulate stresses, such as from a subsequent 1000 deg-C. implant anneal step, since the segments are disconnected from one another, the effect on cell performance may be greatly reduced.
Next, a metal layer 642 may be deposited, and patterned, using conventional deposition and lithography processes, for the purpose of connecting the cell 600 to other cells (not shown, see
Finally, a thick layer 644 of either oxide or nitride or oxy-nitride, or other passivating material may be deposited onto the metal layer 642. For example, in a single metal process, this would be the passivation layer that is used to protect the die during bonding and packaging. If it is a multi-metal process, then this would be a thin layer that is a precursor to the inter-metal dielectric (IMD) layer.
Generally, in this embodiment, no nitride (SiN) contact etch stop layer (CESL) is used.
Generally, in
Generally, a charge storage stack 721 (compare 321), which may be an ONO stack, is disposed atop a channel 720 (compare 320) which is defined (located) between two (source or drain) diffusions 714 and 716 (compare 314 and 316) in a substrate 712 (compare 312). A gate electrode 728 (compare 328) is formed atop the ONO stack 721. Sidewall spacers 729 may be formed on opposite sides of the gate electrode 728. Further process steps, and structures resulting from the process steps will now be described, which generally involve structures 730 overlying the basic memory cell to provide for interconnect.
A layer of thin metal (cobalt or titanium or nickel) 732 may be deposited atop the diffusions 714 and 716, such as having a thickness in the range of 20 nm-200 nm. The metal is then silicided using a conventional salicidation process. (No patterning is necessary. Silicidation is self aligned to the exposed silicon/poly-silicon.) The layer 732 also covers the gate 728, where it is labeled “734”. This layer 732 is generally for the purpose of reducing the sheet resistance of the diffusion and poly-silicon areas.
Next, as in the previous (first) embodiment, an inter-layer dielectric (ILD) layer 738 is disposed over the cover liner 736. The ILD layer 738 may be oxide (SiO2), deposited by a conventional oxide deposition process to a thickness in the range of 700 nm-1200 nm.
Next, contact openings (or “vias”) 740 are formed through the ILD layer 738, such as by using a conventional contact etch process. Since there is no nitride liner to act as a contact etch stop, the metal silicide 732 or 734 may act as the contact etch stop.
Next, the opening 740 may be filled (plugged) with metal, such as tungsten, or with poly (polysilicon) using a conventional deposition process, with excess metal or poly overfilling the opening 740 being polished off, such as by using a conventional chemical-mechanical polishing process, or by an etch-back process or other similar processes. The conductive contact material is not specifically shown (it fills the opening 740), for illustrative clarity.
Next, a metal layer 742 may be deposited, and patterned, using conventional deposition and lithography processes, for the purpose of connecting the cell 700 to other cells (not shown, see
Finally, a thick layer 744 of either oxide or nitride or oxy-nitride, or other passivating material may be deposited onto the metal layer 742. For example, in a single metal process, this would be the passivation layer that is used to protect the die during bonding and packaging. If it is a multi-metal process, then this would be a thin layer that is a precursor to the inter-metal dielectric (IMD) layer.
Generally, in each of the three cells 800, a charge storage stack 821, which may be an ONO stack (which usually contains a trapping layer such as nitride), is disposed atop a channel 820 which is defined (located) between two (source or drain) diffusions 814 and 816 in a substrate 812. A gate electrode 828 is formed atop the ONO stack 821. Sidewall spacers 829 may be formed on opposite sides of the gate electrode 828.
Typically in SONOS, only the gate electrode is silicided. This is indicated by layer 834 of thin metal (cobalt or titanium or nickel, typically 20 nm-200 nm) covering the gate 828. Optionally, the gate electrode could be a silicide (such as tungsten silicide) or could be a metal (such as tungsten) sitting on top of polysilicon. Similarly, MONOS, TANOS and split-gate or other trapping layer structures may be produced as would be known to one of skill in the art.
Next, a thin film cover liner 836 is deposited on the surface of the substrate 812, covering the entire NVM cell 800 (and neighboring cells on the wafer), including covering the gate electrode 828 and the two diffusions 814 and 816.
The cover liner 836 is deposited as a continuous layer, and may have a thickness in the range of 10 nm-200 nm.
Whereas a cover liner is typically (in the prior art) silicon nitride (SiN), according to an embodiment of the disclosure the cover liner 836 is formed as a continuous layer of silicon oxy-nitride (SiON), and may have a thickness in the range of 10 nm-200 nm, such as 20 nm-70 nm.
SiON, as the chemical formulation implies, has oxygen incorporated into the silicon nitride film during the deposition process. Optionally, the oxygen is included by reacting N2O, NH3 and SiH4 in an N2 ambient. SiON exhibits less stress than Nitride and its contact etch stop properties can be tailored to correspond to that of silicon nitride. Besides its use as a passivation layer (it can be modified to allow or block UV transmission) it may also be used as gate oxide material (where it helps prevent boron out diffusion).
It may be noted that, when a thin film of SiON is applied as a liner structure, RAC characteristics may dramatically be improved, due to reduced stress and optionally protection from plasma induced charges.
Next, an inter-layer dielectric (ILD) layer 838 is disposed over the cover liner 836. The ILD layer 838 may optionally be oxide (SiO2), deposited by a conventional oxide deposition process to a thickness in the range of 700 nm-1200 nm.
Generally, in each of the three cells 900, a charge storage stack 921, which may be an ONO stack (which usually contains a trapping layer, such as nitride), is disposed on a substrate 912. A gate electrode 928 is formed atop the charge storage stack 921. Sidewall spacers 929 may be formed on opposite sides of the gate electrode 928. Further process steps, and structures resulting from the process steps will now be described, which generally involve structures 930 overlying the basic memory cell to provide for interconnect.
A layer of thin metal (cobalt or titanium or nickel) 934 may be deposited atop the gate and diffusions, such as having a thickness in the range of 20 nm-200 nm. The metal is then silicided using a conventional salicidation process. (No patterning is necessary. Silicidation is self-aligned to the exposed silicon/poly-silicon.) This layer 934 is generally for the purpose of reducing the sheet resistance of the diffusion and poly-silicon areas.
Next, a thin film cover liner 936 is deposited on the surface of the substrate 912, covering the entire NVM cell 900 (and neighboring cells on the wafer), including covering the gate electrode 928 and the two diffusions 914 and 916.
The cover liner 936 is deposited as a continuous layer, and may have a thickness in the range of 10 nm-200 nm.
Whereas a cover liner is typically (in the prior art) silicon nitride (SiN), according to an embodiment of the disclosure the cover liner 936 is formed as a continuous layer of silicon oxy-nitride (SiON), and may have a thickness in the range of 10 nm-200 nm, such as 20 nm-70 nm.
SiON, as the chemical formulation implies, has oxygen incorporated into the silicon nitride film during the deposition process. Optionally, the oxygen is included by reacting N2O, NH3 and SiH4 in an N2 ambient. SiON exhibits less stress than Nitride and its contact etch stop properties can be tailored to correspond to that of silicon nitride. Besides its use as a passivation layer (it can be modified to allow or block UV transmission) it may also be used as gate oxide material (where it helps prevent boron out diffusion).
It may be noted that, when a thin film of SiON is applied as a liner structure, RAC characteristics may dramatically be improved, due to reduced stress and optionally protection from plasma induced charges.
Next, an inter-layer dielectric (ILD) layer 938 is disposed over the cover liner 936. The ILD layer 938 may optionally be oxide (SiO2), deposited by a conventional oxide deposition process to a thickness in the range of 700 nm-1200 nm.
While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and sub-combinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced be interpreted to include all such modifications, permutations, additions and sub-combinations.