Patent Application
20150055720
1. Field
The present disclosure relates generally to a radio frequency (RF) front-end for a wireless communication system. More specifically, the present disclosure relates to an interface based on a programmable logic device for controlling various RF front-end components. Such a control interface increases flexibility and reduces cost.
2. Related Art
Traditional wireless communication systems are usually designed for a specific standard, such as GSM (Global System for Mobile Communications), Wideband Code Division Multiple Access (W-CDMA), Wi-Fi® (registered trademark of Wi-Fi alliance of Austin, Tex.), LTE (Long Term Evolution), just to name a few. Current demand for the convergence of wireless services, so that users can access different standards from the same wireless device, is driving the development of multi-standard and multi-band transceivers, which are capable of transmitting/receiving radio signals in the entire wireless communication spectrum (most are in a frequency range of from 300 MHz to 3.6 GHz).
The multi-standard requirement means an increased number of components (such as filters, switches, amplifiers, etc.) and, thus, an increased number of control signals sent from baseband chip to the RF front-end.
One embodiment of the present invention provides a system for controlling at least one RF front-end component. During operation, the system receives, at a programmable logic chip from a baseband chip, a command; identifies the RF front-end component based on an address indicated by the command; and sends a control signal included in the command to the identified RF front-end component via the second interface. The programmable logic chip is coupled to the baseband chip via a first interface, and is coupled to the at least one RF front-end component via a second interface.
In a variation on this embodiment, the first interface includes one of: a serial peripheral interface (SPI), an I2C interface, a general purpose input/output interface, and a serial one-wire interface.
In a variation on this embodiment, the programmable logic chip includes at least one of: a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), and a programmable logic device (PLA).
In a variation on this embodiment, the second interface includes one or more of: a serial peripheral interface (SPI), an I2C interface, a general purpose input/output interface, and a serial one-wire interface.
In a variation on this embodiment, the command includes at least one of: a write command and a read command.
In a further variation, in response to the read command, the system obtains a status reading from the identified RF front-end component, and sends the status reading to the baseband chip.
In a variation on this embodiment, the RF front-end component includes one or more of: a filter, a band-selection switch, a power amplifier, a low-noise amplifier, and an automatic gain control (AGC) circuitry.
The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Embodiments of the present invention provide an interface for flexible controlling of various wireless RF front-end modules. More specifically, a programmable logic chip, such as a complex programmable logic device (CPLD), is used to provide a control interface between the baseband chip and the various RF front-end components. A standard Serial Peripheral Interface (SPI) bus couples the programmable logic chip to the baseband chip, which significantly simplifies the design of the baseband chip. Each individual RF front-end module can be coupled to the programmable chip, and is mapped to an address. The baseband chip controls each individual RF front-end module by writing/reading to a corresponding address.
In this disclosure, the term “RF front-end component” or “RF front-end module” can refer to any component or module between the antenna and the digital baseband system in a radio. The front-end components or modules can include switches, filters, amplifiers, mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), RF IC chips, etc. The term “RF IC” can refer to an integrated circuit (IC) that includes one or more of the front-end components. An exemplary RF IC chip can be a transceiver IC chip, which may include modulators and filters.
Operations of transceiver 100 involve baseband DSP 108 sending various control signals to and receiving feedback signals from the various front-end components in RF front-end block 104 and the various components on RF IC chip 106. When designing RF IC chip 106, special care can be taken to ensure that a standard interface, such as a Serial Peripheral Interface (SPI) bus, can be used to enable baseband DSP 108 to control the various components, such as modulators/demodulators and ADCs/DACs, located on RF IC chip 106. However, as shown in
An alternative solution for controlling front-end components is to have baseband DSP chip 108 send commands to RF IC chip 106, which can in turn control the front-end components via a common interface, such as a Mobile Industry Processor Interface (MIPI) RF Front-End Control Interface (RFFE), on behalf of baseband DSP 108. The MIPI RFFE interface allows a master device to control up to 15 slaves on a single RFFE bus (which includes three control lines). However, currently there are few commercially available RF front-end components that are MIPI RFFE ready. As a result, the current control interface between the baseband chip and the RF front-end components relies on a mixture of dedicated I/O pins and MIPI RFFE, which still lacks the desired flexibility and expandability.
To address the need for a flexible and scalable control interface between the baseband chip and the RF front-end components, embodiments of the present invention provide a solution that uses a programmable logic chip as a bridge between the baseband chip and the FR front-end components.
In
Each front-end component that interfaces with programmable logic chip 210 can be mapped to an address, and signals for controlling a component can be sent to the component by writing to the address that corresponds to the component. Similarly, the status of the component can be obtained by reading from the corresponding address. For example, if baseband DSP chip 208 attempts to send a control command to the AGC circuitry, it needs to first find out the address of the AGC circuitry that is mapped by programmable logic chip 210, and then sends a write command to that address. Based on the address, programmable logic chip 210 identifies which I/O pins couple to the AGC circuitry, and then relays the control signal to the AGC circuitry via the identified I/O pins. Note that depending on the specifications of the front-end component, appropriate control signals are sent. For example, a control signal for a switch may be a simple binary signal for “on” and “off,” whereas a control signal for an AGC circuitry may involve multi-level signals.
In some embodiments, the address mapping can be programmed into programmable logic chip 210 before the front-end component is coupled to. For example, programmable logic chip 210 may map certain I/O pins to a particular address, and a front-end component that is coupled to programmable logic chip 210 via those I/O pins would be automatically mapped to the address. In some embodiments, the address mapping is programmed after the front-end component is coupled to programmable logic chip 210. Moreover, based on the specifications of the front-end component, programmable logic chip 210 is programmed to ensure that appropriate control signals can be delivered to the front-end component. To enable simultaneous write/read operations, in some embodiments, the interface between baseband DSP chip 208 and programmable logic chip 210 can include two sets of SPI buses.
In addition to the RF front-end components, programmable logic chip 210 may also interface with RF IC chip 206 in order to relay control signals from baseband DSP 208 to components on RF IC chip 206. In one embodiment, a standard interface, such as SPI, can be used to couple RF IC chip 206 to programmable logic chip 210. Like controlling the RF front-end components, components on RF IC chip 206 can also be mapped to different addresses on programmable logic chip 210, which is in charge of forwarding the command to the components based on the address. In one embodiment, each component on RF IC chip 206 can be identified by an SPI address (which can be indicated by chip-select signals). For example, if there are 10 components of RF IC chip 206, programmable logic chip 210 may include 10 chip-select lines, each for a component on RF IC chip 206. In an alternative embodiment, RF IC chip 206 directly interfaces with baseband DSP chip 208 via an SPI interface. Baseband DSP 208 may include multiple SP chip-selection lines, one for selecting programmable logic chip 210 and the others for selecting components on RF IC chip 206. In one embodiment, programmable logic chip 210 and RF IC chip 206 may be co-located on a same printed circuit board (PCB). In a further embodiment, programmable logic chip 210 and RF IC chip 206 can be integrated on a same IC chip with built-in control logic.
Note that by inserting a programmable logic chip between the baseband chip and the RF front-end components, embodiments of the present invention allow simple and flexible baseband chip designs. The designer of the baseband chip no longer needs to consider the various different interface requirements of the different RF front-end components. Instead, the baseband chip can adopt a standard interface that can be used to control different types of front-end components, and only needs to provide control signals for that standard interface. In addition, there is no longer a need to reserve extra I/O pins on the baseband chip in order to meet the demand for additional RF front-end components. The demand for more front-end components can be met by increasing the size or number of pins of the programmable logic chip, which is much cheaper than trying to increase the size or number of pins of the baseband chip. Another advantage of adopting the programmable logic chip is the decreased trace length for the control lines. In the conventional transceiver shown in
In addition to the architecture shown in
In the example shown in
In the example shown in
In addition to the transceiver IC chips, programmable logic chip 504 is coupled to various components on FEM 512 via different customized control and status feedback interfaces. The format of each control or status feedback interface is determined based on the specification of each front-end component. In the example shown in
During operation, baseband chip 502 sends an SPI write or read command to programmable logic chip 504. The command includes an address that can be mapped to one of the front-end components. Based on the address, programmable logic chip 504 relays the control signals to or collects feedback signals from a corresponding front-end component. For example, if an SPI write command includes an address that can be mapped to a power amplifier, programmable logic chip 504 then relays the control signals (which may include a series of control bits) to the corresponding amplifier via control interface 516. Similarly, if an SPI read command includes an address that can be mapped to a power detector, programmable logic chip 504 then obtains the current reading of the power detector via feedback interface 526 and send it back to baseband chip 502.
In general, compared with traditional schemes that rely on dedicated I/O pins to enable the baseband chip to control the various different RF front-end components, in embodiments of the present invention, the baseband chip only needs to provide control signals to a programmable logic chip via a standard interface. Note that such as an arrangement has significantly simplifies and standardizes the design of the baseband chip. Moreover, the programmable logic chip can be placed in a location that is proximate to the RF front-end components, thus significantly reducing the PCB routing complexity.
Note that the architecture shown in
In addition,
The methods and processes described in the detailed description section can be embodied as code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium.
Furthermore, the methods and processes described below can be included in hardware modules. For example, the hardware modules can include, but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices now known or later developed. When the hardware modules are activated, the hardware modules perform the methods and processes included within the hardware modules.
The foregoing descriptions of embodiments of the present invention have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit this disclosure. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. The scope of the present invention is defined by the appended claims.
