1. Field of the Invention
The present invention relates generally to digital control of power and supply systems, and relates more particularly to a communication interface between a digital micro-controller and analog power supply control.
2. Description of Related Art
Increase operability for control of power converters in a power management system has received increasing focus in recent years. Additional, sought after control features of power supplies appear to be gaining more prominence in the construction of power converters and power converter controllers, due to the demands of increase efficiency and reduced power losses. As the power density of power converters increases, additional control features help to maintain the integrity of power converters and their components. For example, a great deal of attention has been paid to over current conditions in power converters that may shorten the useful life of components in the converter or cause damage to system loads or components.
In a typical conventional PWM controller, control is achieved through the use of comparators in conjunction with analog to digital converters (ADCs). The comparators and ADCs provide an interface between analog and digital components, so that analog information is delivered to the controller, which converts the information to digital control logic, such as PWM signals, for application to a power switching stage.
Once of the difficulties in providing a digital control for a power converter is providing a simple and fast control signal from the digital processor to the power stage of the power converter to realize the advantages of the digital control. Often, there is a fair amount of latency associated with the analog to digital conversion of the fed back analog signals in the controller. Accordingly, an interface between the digital processor and the power stage of the converter should be as simple and fast as possible.
In accordance with the present invention, there is provided an interface between a digital controller and a power stage of a power converter that is substantially reduced to a single line. Information for driving the power stage is encoded in the signals provided on the single line. The power stage decodes the signals to provide switching commands for power switches in the power stage, as well as control actions based on system feedback. Accordingly, the present invention provides an analog/digital interface for a power converter that is highly functional, simple and fast.
According to a feature of the present invention, a simple interface between a digital and analog controller is provided to set the instantaneous switching frequency and duty cycle of the analog controller based on digital control represented by a digital signal. The digital signal has minimal complexity and is easily decoded to provide analog control information in the analog controller.
According to an aspect of the present invention, current limit control can be applied in the single signal, including the provision of a dynamic current limit, a retry count, reduced switching intervals and shutdown, for example. The control reads a current feedback signal to determine an appropriate response that can be modified for different situations.
According to another aspect of the present invention, the digital/analog interface control signal represents different information based on different operating modes. For example, the information in the control signal may be interpreted differently during a startup mode than in a steady state mode. The information may also be used differently in a current limit mode when an overcurrent condition is detected.
According to another feature of the present invention, the information encoded control line is operable to implement a volt-second clamp based on the input voltage and the duty ratio of a switch. As the input voltage increases, the volt-second clamp limits the duty cycle of the signal to protect the transformer from saturation in an isolated topology.
Another advantage of the present invention is realized through the use of ports provided on a digital processor that permits the digital processor to output signals that can influence feedback parameters, such as current limit thresholds, for example. The additional control provided by the digital processor permits a high level of responsive and programmability in the system, where previous realization typically relied on hard coded parameter values through passive component selection.
The present invention is described in greater detail below, with reference to the accompanying drawings:
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Interface between processor 62 and controller 65 is extremely simple and straight forward. A signal CLK provided from processor 62 to controller 65 encodes all of the control information for instructing controller 65 to drive the power switches in power stage 68. Signal CLK is a PWM signal that is also frequency modulated, in that the frequency information of the pulse train in signal CLK provides switching information for the power switch in power stage 68. By encoding the control information in a single signal, interface 64 is greatly simplified and extremely fast in facilitating control operations between processor 62 and controller 65. Although processor 62 is also shown as providing signals for PWM control, a current limit threshold and an enable, these signals are not essential for operation of analog controller 65. Accordingly, a single control line CLK can provide complete control information from processor 62 to controller 65.
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Once the power converter has moved from start up mode to steady state mode, the converter duty ratio is less than a limit imposed by processor 62. In this instance, output OUT has pulse widths determined by signal PWM. The pulse widths on signal CLK during steady state operation act as a safeguard or maximum duty cycle limit to impose a safety limit on the operation of the power converter. Note that feedback signal FB is maintained at a low level during the steady state operation.
When an overcurrent condition occurs, controller 65 enters a current limit mode, in which the duty cycle of the output OUT is limited. The current limit function provides cycle by cycle control to override the duty cycles of signal CLK, when the switch current reaches the current limit threshold. The current limit threshold is a value presented at the ILIM pin of controller 65. When the current limit circuit is activated, signal CLF goes to a high value for a remainder the switching period, and feedback is provided to controller 62 to provide an overcurrent close loop control.
It should be noted that the current limit functionality can be completely independent of signal CLK from processor 62. A current limit event can be latched in the memory of analog controller 65 until a following switching period initiated by processor 62. With this technique, controller 65 can protect the power stage in the event of a problem with processor 62. For example, if processor 62 stalls or freezes, such that signal CLK is left in a high state, the current limit circuit causes the power switch to be switched at a lower duty cycle in an overcurrent condition, regardless of signal CLK.
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Diagram 94 illustrates a dynamic volt-second clamp routine in which output voltage is measured to determine an output voltage error, DPWM. If the duty cycle voltage error is greater than the set duty cycle limit DVS, the routine permits the converter to operate beyond the limit for five cycles, in the example illustrated in diagram 94. This temporary operation beyond the set point limits can accommodate a fast transient response to avoid reduction of the duty ratio when the operational limits are exceeded for only a short period of time. Diagram 94 shows how the limit for the volt-second clamp can be dynamically changed by setting duty ration DLIM to the current duty ration DVS, and comparing that limit against the voltage error DPWM. If duty ration DLIM is less than the voltage error, than DLIM is used as the duty ratio limit, otherwise, voltage error DPWM is set to duty ratio DLIM, so that a maximum duty ratio can be adjusted.
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In an overload condition, the duty cycle of the power switch in the power stage is limited by the current limit circuit on a cycle by cycle basis. If the current sent signal reaches a limit set by the current limit threshold, the gate drive is immediately shut off to protect the power stage. Accordingly, a shut off threshold can be dynamically altered depending upon the type of loading or overcurrent event that the power converter experiences.
The present invention describes a simple and effective interface between a digital controller and an analog controller. The interface can be implemented in a single control line that carries frequency and pulse width information for driving the analog controller. This architecture is applicable to a number of situations in which analog systems are controlled with digital techniques. Accordingly, power converters, motor drives, lighting systems and other power applications are ready candidates for digital control with the interface provided according to the present invention.
Finally, it will be appreciated that modifications to and variations of the above-described system and method may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited except by the scope and spirit of the appended claims.