This application is related to U.S. patent application Ser. No. 10/945,623, filed Sep. 20, 2004; U.S. patent application Ser. No. 12/369,708, filed Feb. 11, 2009; and U.S. patent application Ser. No. 12/713,111, filed Feb. 25, 2010; all incorporated by reference herein.
This application is related to U.S. patent application Ser. No. 10/945,623, entitled “MEDIA ON DEMAND VIA PEERING,” by Aron Marking, filed Sep. 20, 2004, now abandoned; U.S. patent application Ser. No. 12/369,708, entitled “SIMPLE NON-AUTONOMOUS PEERING ENVIRONMENT, WATERMARKING AND AUTHENTICATION,” by Aaron Marking et al, filed Feb. 11, 2009, now issued as U.S. Pat. No. 8,775,811, and U.S. patent application Ser. No. 12/713,111, entitled “CONTENT DISTRIBUTION WITH RENEWABLE CONTENT PROTECTION,” by Aaron Marking et al, filed Feb. 25, 2010; all of which applications are hereby incorporated by reference herein.
The packaging of media content, such as video or audio content, into digital media files has made the exchange of the content very easy and convenient for users. However, users freely exchanging content may violate the content owner's property rights. Content owners also want to restrict the copying of copyright protected content. There are many examples of technologies that make the transfer of copyright protected content very difficult. When physical media is used to store content, permanently or temporarily, for example in electronic purchase, rental and subscription movie service business models, content owners or their licensees use a variety of cryptographic binding methods. These methods typically use a unique media or device identifier or similar player attributes in a cryptographic function to protect the content from being copied or transferred such that it may be said to be bound to the device. Generally, this binding of the content is based upon a particular playback device, which is undesirable for users. Users may want to play their content on a different device than the device that received the content or they may want to transfer it among several personal devices.
One approach involves peering of content, where users transfer data amongst themselves. In order to preserve copyrights and to avoid pirating of the content, a ‘non-autonomous’ peering system may be employed. In contrast to a typically peering system, where users transfer content freely, the system is ‘non-autonomous.’ Non-autonomous' as used here means that the system includes mechanisms that only allow transfer of the content with the assistance of a centralized authority, while allowing users to transfer media content between their own compliant devices. A peer in this system consists of an end-user owned device acting as the source for a transfer, while in most other systems content resides on a server for download.
Examples of a non-autonomous peering system can be found in U.S. Pat. No. 7,165,050, and US Patent Publication No. 20060064386, both titled, “Media on Demand Via Peering.” An example of methods of manufacturing and binding components usable in a non-autonomous peering system can be found in U.S. patent application Ser. No. 12/369,708, “Simple Non-Autonomous Environment, Watermarking And Authentication,” filed Feb. 11, 2009. U.S. patent application Ser. Nos. 12/369,708, and 12/713,111 discuss the use of a peering system in conjunction with flash memory devices.
With the increasingly less expensive and wide proliferation of flash memory devices, a very real possibility arises of pirates using flash memory devices to clone valid devices originating from the content providers or legitimate users of a peering system. The pirates can reproduce a huge amount of content on cloned devices with very simple hardware and in a very short period of time.
The below discussion uses several terms that may become confusing. The discussion uses the term ‘memory’ and memory device’ to refer to a non-volatile memory device that contains ‘content.’ ‘Content’ includes any type of experiential content and includes, but is not limited to, movies, television shows, recorded performances, video files, audio files, and games. The memory device may include removable memory, such as flash memory drives, so-called ‘thumb’ drives, memory cards, embedded flash memory including spinning and solid state hard drives, and memory sticks, but no limitation is intended, nor should any be implied by these examples. The memory device will be referred to here as ‘content’ memory, because it resides separately from on-board memory of a playback device, although it may be internal to the playback device.
The memory device may interface with a ‘playback device,’ where a playback device is any device having a controller, also referred to as a processor or a system on a chip (SoC), a memory and the ability to interface with the media, whether as embedded media or removable media. Examples include, but are not limited to, televisions, video projectors, digital video recorders, set-top boxes, kiosks, personal computers, and mobile computing devices including smart phones, media players, in-car players, netbooks and tablet computers.
As stated above, the memory device 20 may take one of many different forms, including CompactFlash; MultiMedia Cards (MMC), including Reduced Size—MMC; Secure Digital (SD) cards, including mini-SD and micro-SD; and Memory Sticks. These of course are merely examples of the different memory formats and form factors, which may also be embodied in memory devices such as 20 that connect to the playback device by an external connector 22, such as Universal Serial Bus (USB) connectors, and those that comply with IEEE standard 1394, also referred to as ‘firewire.’ In the embodiment of embedded memory including hard disks, the content memory device may communicate with the controller using IDE (Integrated Drive Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Serial Computer System Interface), SAS (Serial Attached SCSI) or USB interfaces.
The memory device will typically be a ‘flash’ memory device, meaning an electrically programmable/erasable non-volatile memory device. These types of devices may be manufactured according to many different metal and semiconductor technologies. Generally, they fall within two different types of operational technologies, those NOR (not OR) flash memory and NAND (not AND) memory devices. Currently, the prevalent type of flash memory is NAND flash memory, but NOR flash memory devices are well within the scope of the embodiments discussed here.
The SNAP system uses the physical defects inherent in NAND flash media to bind content to NAND flash. These defects in NAND Flash are called Bad Blocks. NAND Flash is a type of non-volatile solid-state memory containing 2 distinct physical storage areas: a Data area composed of pages physically grouped into Blocks, and a “Spare” area for the storage of logical and physical metadata pertaining to the Data area and the data stored therein. While the configuration of these two areas may vary from Fabricator to Fabricator, both areas are present in all NAND Flash chips. NAND Flash chips are programmed on a page-by-page basis and erased in a block-wise manner in an effort to enhance performance.
Due to the inherent manufacturing methods used to make NAND Flash memory, it is common for NAND Flash chips to contain up to 5.5% defects at the time of manufacture. This is necessitated in order for chip fabricators to maintain commercially viable production yields. Since NAND Flash memory is erased on a block-by-block basis, any defect detected either during a page program cycle, or a block erase cycle dictates that the entire block of memory be identified as “Bad” in order to avoid potential data corruption. Defective blocks are identified during rigorous post manufacturing testing, by the chip fabricator, by programming a specific value (typically OOOh) into the block's spare area. Runtime detected bad blocks are marked with a different value (typically FFFh for 16 bit blocks) to the spare area.
Any type of flash memory device, whether based upon complementary metal-oxide semiconductor technologies, or other types of memory technologies, is within the scope of the embodiments here, as many of them have similar characteristics as to their organization and some of their operations. This includes single level cell (SLC) or multilevel cell (MLC) technologies.
For example, in NAND flash memory, programming the memory changes bits from a logic one to a logic zero. Erasure resets all bits to back to one. The memory is organized into pages and blocks. Erasure happens a block at a time, with block sizes typically being 64, 128 or 256 KB. NAND flash devices may also include bad block management, a process by which bad blocks are identified and mapped either at runtime or at manufacture. Many devices also now include wear leveling, where the writing of data is rotated among blocks to prolong the life of the memory cells that will eventually degrade over repeated write/read cycles.
In NAND flash devices, each block consists of a number of pages, each page may have a typical size of 512, 2,048, or 4,096 bytes in size plus a few bytes to store an error correcting code (ECC) checksum and other metadata necessary for the operation of the memory array. Reading and programming of these devices is typically done on a page basis. Erasure is done on a block basis. NAND devices typically also have bad block management by the device driver software, or by a separate controller chip. SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map. The overall memory capacity gradually shrinks as more blocks are marked as bad. These set aside blocks for mapping tables or the memory region in which the power-up (runtime) maps are stored constitute the defined region.
Most NAND devices are shipped from the factory with some bad blocks which are typically identified and marked according to a specified bad block marking strategy. By allowing some bad blocks, the manufacturers achieve far higher yields than would be possible if all blocks had to be verified good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.
Generally, manufacturers of flash and other storage media use a method of bad block identification that allows the device to identify bad blocks of physical memory following manufacture. By doing so, the manufacturer can still sell the device and it will operate as intended, as the bad blocks are marked and identified for any processing device that accesses the remaining ‘good’ blocks of memory.
During post manufacture testing, each block of physical memory undergoes multiple ‘program,’ ‘read’ and ‘erase’ operations. When any or all of the pages that make up a memory block fails, the entire block is marked bad by writing a specific value (e.g. ‘ooh’) in pages of the bad block, as well as within the Spare Area related to the block.
These bad blocks detected at manufacture are differentiated from the bad blocks detected during subsequent consumer operation of the device. Bad blocks identified during consumer operation are identified by writing a different value (e.g. Toh′) in the pages and spare area of the block.
Since the pattern of bad blocks identified at the time of manufacturing is random, this information provides a unique value usable to provide a unique authentication and cryptography mechanism. The pattern of bad blocks may be combined with the unique media ID of the device to create a unique authentication value. It may also be possible to identify a specific page which has failed within a block of memory, the value of which may also be usable to enhance the robustness of this authentication. This would allow for a unique authentication value at manufacture, but some sort of infrastructure may be helpful to ensure that this unique value is monitored and tracked to prevent it from being forged or otherwise copied.
While the embodiments herein may be applied to either NAND or NOR flash memories, no such limitation is intended nor should it be implied. The embodiments here could be applied to any type of memory device that has bad block management and the ability to use bad block maps and known data patterns to determine an expected data pattern when validating the memory device. Memory devices include hard disk drives, both ‘traditional’ spinning disks with readers and solid state hard drives.
Within the memory array, the manufacturer or content provider that has provided the content stored by the memory device has defined a region 24. The region may consist of some set of blocks, pages, or sectors. The region has a known defect map, either generated by a SNAP server before content is delivered to the media, or determined at manufacture of the memory device. If the defect map has been determined at manufacture of the memory device, the memory device may store the defect map in a second region 26 of the memory device.
By using the defect maps of the individual memory devices, the content provider will have a characteristic of the memory array usable to validate the memory device and therefore unlock the content. Validation of the memory device allows the content providers to ensure that only authorized memory devices carry their content, as opposed to devices to which their content has been copied in violation of their copyrights. This discussion may refer to these devices as ‘cloned’ devices.
In order to replicate the content and still allow the memory device to appear valid, the pirates would have to determine the exact location of the defined region, have access to a known data pattern used in validation and the defect map of the memory device. The computing power to determine this will typically prohibit a pirate from having the capability of producing memory devices that validate in the playback devices and allow playing of the content.
In the case where the known data pattern or defect map is provided by the manufacturer or content provider, the defect map will typically be signed to allow authentication/validation. For example, the manufacturer may provide the defect map in the metadata that accompanies the memory device and may have already written the known data pattern to the defined region in the memory.
The playback device would then access the known data pattern at 34, where accessing the known data pattern may involve retrieving it from the playback device memory, generating the known data pattern or receiving it in real-time. As mentioned above the known data pattern may be stored at 36, but this is optional.
Once the device has the known data pattern, it writes the known data pattern to the defined region in the memory device at 40. The playback device then reads data from the defined region at 42. The data read from the defined region should correlate to the known data pattern altered in a manner determined by the defect map. For example, in the known data pattern, the playback device writes a 1 to the memory cell corresponding to bit 3. However, because of the defect map, the playback device ‘knows’ that the cell storing bit 3 has a defect. Therefore, the expected data pattern will return the known data pattern, except that bit 3 will be a 0 instead of a 1. This simplified example demonstrates how the defect map produces a unique data pattern upon reading from the defined region. The discussion will refer to the read data pattern altered by the defect map as the ‘expected data pattern’, generated by the playback device at 50.
In the embodiment where the known data pattern and/or defect map have been provided by the manufacturer, the process may skip from the receiving of the known data pattern and defect map to the reading of the data from the defined region at 42. This process may occur in several ways. For example, the playback device may read the data from the defined region using the error correction code to determine the known data pattern. Then the playback device may read the data from the defined region without using the error correction code. These patterns would then be used in the following comparison.
One should note that the expected data pattern may not actually reside in the playback device as a stored entity. The playback device may read the data back from the defined region and compare it to the known data pattern, then check the read data pattern against the defect map. A multitude of ways exists to make the comparison between the read data pattern and the expected data pattern at 44, all of which are within the scope of the embodiments here.
At 46, the playback device determines if the comparison result of the two patterns meets some correlation criteria, as they may not match exactly. For example, the defect in bit 3 may result in the data bit having the correct value when read back or having the opposite value. Note that the memory cells can be modeled by independent random variables, each with a certain probability of being defective (different cells having different probabilities). This is a well-studied problem in statistical analysis, and a standard correlation function used in this case is the Chi Square test. However, other correlation functions, including ad hoc functions, are within the scope of this invention. The process accounts for these kinds of unknown results by providing some correlation measure that has a high enough value that the memory device validates even though the patterns do not match exactly.
Indeed, in some cases, the patterns would actually be expected to not match exactly. In NAND flash devices, some devices may have intermittent defects, meaning that from read to read, a bit with an intermittent error may change state. This would result in the read data pattern to vary slightly from the expected data pattern. For example, a defect map may identify bit 3 of a particular portion of the memory to have an intermittent data error. In the known data pattern, bit 3 may be written as a data 1. The expected data pattern may expect a 0 at bit 3 because it has a defect. However, because it is an intermittent defect, bit 3 may return a 0 the first read and a 1 the second read.
This anomaly can be accounted for using a correlation measure such that the read data pattern correlation would vary from read to read. If it did not vary from read to read, where the read data pattern is the exact same each read, it may actually indicate that it is a cloned device. It would take considerably more logic circuitry and computing power to mimic the intermittent data errors.
In this manner, content providers use an inherent characteristic of the memory device to validate the memory devices. Pirates would have to find memory devices that have the same defect maps or divine some way of spoofing a memory device defect map, get access to the known data pattern, and know the exact location of the defined region to replicate pirated content across cloned devices. The computing power this requires would prohibit the vast majority of pirating efforts.
Although there has been described to this point a particular embodiment for a method and apparatus for validating memory devices containing content, it is not intended that such specific references be considered as limitations upon the scope of this invention except in-so-far as set forth in the following claims.
|4510572||Franzel et al.||Apr 1985||A|
|4577289||Comerford et al.||Mar 1986||A|
|5742757||Hamadani et al.||Apr 1998||A|
|6029259||Sollish et al.||Feb 2000||A|
|6161052||Charlton et al.||Dec 2000||A|
|6253193||Ginter et al.||Jun 2001||B1|
|6289292||Charlton et al.||Sep 2001||B1|
|6557125||Rochat et al.||Apr 2003||B1|
|6654904||Andoh et al.||Nov 2003||B1|
|6701528||Arsenault et al.||Mar 2004||B1|
|6775817||Ono et al.||Aug 2004||B2|
|6850379||Andoh et al.||Feb 2005||B2|
|7017044||Carpenter et al.||Mar 2006||B1|
|7076468||Hillegass et al.||Jul 2006||B2|
|7103574||Peinado et al.||Sep 2006||B1|
|7496540||Irwin et al.||Feb 2009||B2|
|7584258||Hudson et al.||Sep 2009||B2|
|7594275||Zhu et al.||Sep 2009||B2|
|7639849||Kimpe et al.||Dec 2009||B2|
|7949913||Norrod et al.||May 2011||B2|
|8724408||Ho et al.||May 2014||B2|
|20010016836||Boccon-Gibod et al.||Aug 2001||A1|
|20020023248||Suzuki et al.||Feb 2002||A1|
|20020052053||Ono et al.||May 2002||A1|
|20020122266||Andoh et al.||Sep 2002||A1|
|20020150251||Asano et al.||Oct 2002||A1|
|20020199099||Shirai et al.||Dec 2002||A1|
|20030063405||Jin et al.||Apr 2003||A1|
|20030140088||Robinson et al.||Jul 2003||A1|
|20030145093||Oren et al.||Jul 2003||A1|
|20030187679||Odgers et al.||Oct 2003||A1|
|20040024688||Bi et al.||Feb 2004||A1|
|20040091114||Carter et al.||May 2004||A1|
|20040103305||Ginter et al.||May 2004||A1|
|20050010531||Kushainagar et al.||Jan 2005||A1|
|20050060745||Riedi et al.||Mar 2005||A1|
|20050149759||Vishwanath et al.||Jul 2005||A1|
|20050177624||Oswald et al.||Aug 2005||A1|
|20050188214||Worley et al.||Aug 2005||A1|
|20060200414||Roberts, Jr.||Sep 2006||A1|
|20060262147||Kimpe et al.||Nov 2006||A1|
|20070124602||Wald et al.||May 2007||A1|
|20070180153||Cornwell et al.||Aug 2007||A1|
|20070233933||Wang et al.||Oct 2007||A1|
|20080133938||Kocher et al.||Jun 2008||A1|
|20090013195||Ochi et al.||Jan 2009||A1|
|20090049257||Khatri et al.||Feb 2009||A1|
|20090049351||Norrod et al.||Feb 2009||A1|
|20090158044||Kirovski et al.||Jun 2009||A1|
|20090204778||Marking et al.||Aug 2009||A1|
|20090300413||Chang et al.||Dec 2009||A1|
|20100088750||Okamoto et al.||Apr 2010||A1|
|20100218000||Marking et al.||Aug 2010||A1|
|20100251044||Khatri et al.||Sep 2010||A1|
|20100299458||Marking et al.||Nov 2010||A1|
|“Of.” Webster's Third New International Dictionary, Unabridged, Merriam-Webster, Incorporated, 1993. [online][retrieved on Apr. 9, 2011]. Retrieved from: <http://lionreference.chadwyck.com/searchFulltext.do?id=23720595&idType=offset&divLevel=2&queryld=../session/1302503939_28935&area=mwd&forward=refshelf&trail=refshelf >.|
|Chip Repairer Memory Corp Tweaks Its Product Line and Prays for Prices to Start Hardening Again. (1996). Computergram International, (2919). Retrieved on Mar. 25, 2020 from URL: <http://dialog.proquest.com/professional/docview/1084773237?accountid=131444> (Year: 1996).|
|European Search Report dated Jan. 3, 2013, Application No. 09710597.7.|
|Extended European Search Report (EESR) dated Jul. 29, 2013 for European Patent Application 10800679.2.|
|Japanese Office Action (with English translation) dated Sep. 10, 2013 for Japanese Patent Application No. 2012-520841.|
|Japanese Office Action (with English translation) dated Aug. 20, 2013 for Japanese Patent Application No. 2010-546108.|
|Japanese Office Action dated Feb. 18, 2014 in related Japanese Patent Application No. 2012-520841.|
|European Examination Report dated Mar. 10, 2014 in related European Patent Application No. 10800679.2.|
|Chinese Office Action dated Mar. 27, 2014 in related Chinese Patent Application No. 201080039520.3.|
|Japanese Office Action (with English translation) dated Apr. 2, 2013 for Japanese Patent Application No. 2011-552162.|
|PCT International Search Report & Written Opinion dated Sep. 7, 2010 for PCT Patent Application No. PCT/US2010/042483.|
|Non-Final Office Action dated Apr. 5, 2019 for U.S. Appl. No. 14/995,114.|
|20100299458 A1||Nov 2010||US|