Patent Application
20220094930
This patent document relates to video coding and decoding techniques, devices and systems.
In spite of the advances in video compression, digital video still accounts for the largest bandwidth use on the internet and other digital communication networks. As the number of connected user devices capable of receiving and displaying video increases, it is expected that the bandwidth demand for digital video usage will continue to grow.
Devices, systems and methods related to digital video coding, and specifically, methods on multiple transforms for video coding, are described. The described methods may be applied to both the existing video coding standards (e.g., High Efficiency Video Coding (HEVC)) and future video coding standards (e.g., Versatile Video Coding (VVC)) or codecs.
In yet another representative aspect, the disclosed technology may be used to provide an example method for video processing. This method includes selecting, as part of a multiple transform selection (MTS) process, a common transform as both a vertical transform and a horizontal transform, and applying, as part of performing a conversion between a current block of a video and a bitstream representation of the video, the vertical transform and the horizontal transform to the current block.
In yet another representative aspect, the disclosed technology may be used to provide an example method for video processing. This method includes selecting, for a current block of a video as part of a multiple transform selection (MTS) process, one or more transforms that exclude a Discrete Sine Transform of Type VIII (DST VIII), and applying, as part of performing a conversion between the current block and a bitstream representation of the video, the one or more transforms to the current block based on the current block being coded with a sub-block transform (SBT).
In yet another representative aspect, the disclosed technology may be used to provide an example method for video processing. This method includes selecting, for a current block of a video, a vertical transform and a horizontal transform as part of an MTS process, wherein the current block is coded with a sub-block transform (SBT) based on a size of a transform block (TB) being smaller than a size of the current block, wherein the TB has a height (H) and a width (W), and wherein H and W are positive integers, and performing, based on the selecting, a conversion between the current block and a bitstream representation of the video.
In yet another representative aspect, the disclosed technology may be used to provide an example method for video processing. This method includes making a decision, for a current block of a video and based on one or more messages signaled in a bitstream representation of the video, regarding applying a transform coefficient zero-out process, and performing, based on the decision, a conversion between the current block and the bitstream representation, wherein the one or more messages are signaled in a video parameter set (VPS), a sequence parameter set (SPS), a picture parameter set (PPS), an adaptation parameter set (APS), a decoder parameter set (DPS), a slice header, a picture header, a sequence header, a tile group header, a tile, a coding tree unit (CTU) row, a CTU, a coding unit (CU), a prediction unit (PU), or a transform unit (TU).
In yet another representative aspect, the disclosed technology may be used to provide an example method for video processing. This method includes making a decision, for a current block of a video and based on a size and a type of a transform, regarding applying a transform coefficient zero-out, and performing, based on the decision, a conversion between the current block and the bitstream representation.
In yet another representative aspect, the disclosed technology may be used to provide an example method for video processing. This method includes making a decision, for a current block of a video and based on an implicit transform of a multiple transform selection (MTS) process, regarding applying a transform coefficient zero-out, and performing, based on the decision, a conversion between the current block and the bitstream representation, wherein an implicit MTS process includes using a characteristic of the current block to determine a transform used during the conversion.
In yet another representative aspect, the above-described method is embodied in the form of processor-executable code and stored in a computer-readable program medium.
In yet another representative aspect, a device that is configured or operable to perform the above-described method is disclosed. The device may include a processor that is programmed to implement this method.
In yet another representative aspect, a video decoder apparatus may implement a method as described herein.
The above and other aspects and features of the disclosed technology are described in greater detail in the drawings, the description and the claims.
Due to the increasing demand of higher resolution video, video coding methods and techniques are ubiquitous in modern technology. Video codecs typically include an electronic circuit or software that compresses or decompresses digital video, and are continually being improved to provide higher coding efficiency. A video codec converts uncompressed video to a compressed format or vice versa. There are complex relationships between the video quality, the amount of data used to represent the video (determined by the bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data losses and errors, ease of editing, random access, and end-to-end delay (latency). The compressed format usually conforms to a standard video compression specification, e.g., the High Efficiency Video Coding (HEVC) standard (also known as H.265 or MPEG-H Part 2), the Versatile Video Coding (VVC) standard to be finalized, or other current and/or future video coding standards.
Embodiments of the disclosed technology may be applied to existing video coding standards (e.g., HEVC, H.265) and future standards to improve runtime performance. Section headings are used in the present document to improve readability of the description and do not in any way limit the discussion or the embodiments (and/or implementations) to the respective sections only.
Color space, also known as the color model (or color system), is an abstract mathematical model which simply describes the range of colors as tuples of numbers, typically as 3 or 4 values or color components (e.g. RGB). Basically speaking, color space is an elaboration of the coordinate system and sub-space.
For video compression, the most frequently used color spaces are YCbCr and RGB.
YCbCr, Y′CbCr, or Y Pb/Cb Pr/Cr, also written as YCBCR or Y′CBCR, is a family of color spaces used as a part of the color image pipeline in video and digital photography systems. Y′ is the luma component and CB and CR are the blue-difference and red-difference chroma components. Y′ (with prime) is distinguished from Y, which is luminance, meaning that light intensity is nonlinearly encoded based on gamma corrected RGB primaries.
Chroma subsampling is the practice of encoding images by implementing less resolution for chroma information than for luma information, taking advantage of the human visual system's lower acuity for color differences than for luminance.
4:4:4 Format. Each of the three Y′CbCr components have the same sample rate, thus there is no chroma subsampling. This scheme is sometimes used in high-end film scanners and cinematic post production.
4:2:2 Format. The two chroma components are sampled at half the sample rate of luma: the horizontal chroma resolution is halved. This reduces the bandwidth of an uncompressed video signal by one-third with little to no visual difference
4:2:0 Format. In 4:2:0, the horizontal sampling is doubled compared to 4:1:1, but as the Cb and Cr channels are only sampled on each alternate line in this scheme, the vertical resolution is halved. The data rate is thus the same. Cb and Cr are each subsampled at a factor of 2 both horizontally and vertically. There are three variants of 4:2:0 schemes, having different horizontal and vertical siting.
To capture the arbitrary edge directions presented in natural video, the number of directional intra modes is extended from 33, as used in HEVC, to 65. The additional directional modes are depicted as red dotted arrows in
Conventional angular intra prediction directions are defined from 45 degrees to −135 degrees in clockwise direction as shown in
In HEVC, every intra-coded block has a square shape and the length of each of its side is a power of 2. Thus, no division operations are required to generate an intra-predictor using DC mode. In VTV2, blocks can have a rectangular shape that necessitates the use of a division operation per block in the general case. To avoid division operations for DC prediction, only the longer side is used to compute the average for non-square blocks.
In some embodiments, conventional angular intra prediction directions are defined from 45 degrees to −135 degrees in clockwise direction. In VTM2, several conventional angular intra prediction modes are adaptively replaced with wide-angle intra prediction modes for non-square blocks. The replaced modes are signaled using the original method and remapped to the indexes of wide angular modes after parsing. The total number of intra prediction modes for a certain block is unchanged, e.g., 67, and the intra mode coding is unchanged.
To support these prediction directions, the top reference with length 2 W+1, and the left reference with length 2H+1, are defined as shown in the examples in
In some embodiments, the mode number of replaced mode in wide-angular direction mode is dependent on the aspect ratio of a block. The replaced intra prediction modes are illustrated in Table 1.
As shown in
In the VTM2, the results of intra prediction of planar mode are further modified by a position dependent intra prediction combination (PDPC) method. PDPC is an intra prediction method which invokes a combination of the un-filtered boundary reference samples and HEVC style intra prediction with filtered boundary reference samples. PDPC is applied to the following intra modes without signaling: planar, DC, horizontal, vertical, bottom-left angular mode and its eight adjacent angular modes, and top-right angular mode and its eight adjacent angular modes.
The prediction sample pred(x,y) is predicted using an intra prediction mode (DC, planar, angular) and a linear combination of reference samples according to the Equation as follows:
pred(x,y)=(wL×R−1,y+wT×Rx,−1−wTL×R−1,−1+(64−wL−wT+wTL)×pred(xy)+32)>>shift
Herein, Rx,−1, R−1,y represent the reference samples located at the top and left of current sample (x, y), respectively, and R−1,−1 represents the reference sample located at the top-left corner of the current block.
In some embodiments, and if PDPC is applied to DC, planar, horizontal, and vertical intra modes, additional boundary filters are not needed, as required in the case of HEVC DC mode boundary filter or horizontal/vertical mode edge filters.
In some embodiments, the PDPC weights are dependent on prediction modes and are shown in Table 2, where S=shift.
In JVET-M0102, ISP is proposed, which divides luma intra-predicted blocks vertically or horizontally into 2 or 4 sub-partitions depending on the block size dimensions, as shown in Table 3.
For each of these sub-partitions, a residual signal is generated by entropy decoding the coefficients sent by the encoder and then invert quantizing and invert transforming them. Then, the sub-partition is intra predicted and finally the corresponding reconstructed samples are obtained by adding the residual signal to the prediction signal. Therefore, the reconstructed values of each sub-partition will be available to generate the prediction of the next one, which will repeat the process and so on. All sub-partitions share the same intra mode.
Based on the intra mode and the split utilized, two different classes of processing orders are used, which are referred to as normal and reversed order. In the normal order, the first sub-partition to be processed is the one containing the top-left sample of the CU and then continuing downwards (horizontal split) or rightwards (vertical split). As a result, reference samples used to generate the sub-partitions prediction signals are only located at the left and above sides of the lines. On the other hand, the reverse processing order either starts with the sub-partition containing the bottom-left sample of the CU and continues upwards or starts with sub-partition containing the top-right sample of the CU and continues leftwards.
BDPCM is proposed in JVET-M0057. Due to the shape of the horizontal (resp. vertical) predictors, which use the left (A) (resp. top (B)) pixel for prediction of the current pixel, the most throughput-efficient way of processing the block is to process all the pixels of one column (resp. line) in parallel, and to process these columns (resp. lines) sequentially. In order to increase throughput, we introduce the following process: a block of width 4 is divided into two halves with a horizontal frontier when the predictor chosen on this block is vertical, and a block of height 4 is divided into two halves with a vertical frontier when the predictor chosen on this block is horizontal.
When a block is divided, samples from one area are not allowed to use pixels from another area to compute the prediction: if this situation occurs, the prediction pixel is replaced by the reference pixel in the prediction direction. This is shown on
Because of this property, it becomes now possible to process a 4×4 block in 2 cycles, and a 4×8 or 8×4 block in 4 cycles, and so on, as shown on
Table 4 summarizes the number of cycles required to process the block, depending on the block size. It is trivial to show that any block which has both dimensions larger or equal to 8 can be processed in 8 pixels per cycle or more.
In JVET-N0413, quantized residual domain BDPCM (denote as RBDPCM hereinafter) is proposed. The intra prediction is done on the entire block by sample copying in prediction direction (horizontal or vertical prediction) similar to intra prediction. The residual is quantized and the delta between the quantized residual and its predictor (horizontal or vertical) quantized value is coded.
For a block of size M (rows)×N (cols), let ri,j, 0≤i≤M−1, 0≤j≤N−1. be the prediction residual after performing intra prediction horizontally (copying left neighbor pixel value across the the predicted block line by line) or vertically (copying top neighbor line to each line in the predicted block) using unfiltered samples from above or left block boundary samples. Let Q(ri,j), 0≤i≤M−1, 0≤j≤N−1 denote the quantized version of the residual ri,j, where residual is difference between original block and the predicted block values. Then the block DPCM is applied to the quantized residual samples, resulting in modified M×N array {tilde over (R)} with elements {tilde over (r)}i,j. When vertical BDPCM is signaled:
For horizontal prediction, similar rules apply, and the residual quantized samples are obtained by
The residual quantized samples {tilde over (r)}i,j are sent to the decoder.
On the decoder side, the above calculations are reversed to produce Q(ri,j), 0≤i≤M−1, 0≤j≤N−1. For vertical prediction case,
Q(ri,j)=Σk=0i{tilde over (r)}k,j, 0≤i≤(M−1), 0≤j≤(N−1)
For horizontal case,
Q(ri,j)=Σk=0i{tilde over (r)}i,k, 0≤i≤(M−1), 0≤j≤(N−1)
The invert quantized residuals, Q−1(Q(ri,j)) are added to the intra block prediction values to produce the reconstructed sample values.
One of the benefits of this scheme is that inverting the DPCM can be done on the fly during coefficient parsing simply adding the predictor as the coefficients are parsed or it can be performed after parsing.
Transform skip is always used in quantized residual domain BDPCM. 2.9 Multiple Transform Set (MTS) in VVC
In VTM4, large block-size transforms, up to 64×64 in size, are enabled, which is primarily useful for higher resolution video, e.g., 1080p and 4K sequences. High frequency transform coefficients are zeroed out for the transform blocks with size (width or height, or both width and height) equal to 64, so that only the lower-frequency coefficients are retained. For example, for an M×N transform block, with M as the block width and N as the block height, when M is equal to 64, only the left 32 columns of transform coefficients are kept. Similarly, when N is equal to 64, only the top 32 rows of transform coefficients are kept. When transform skip mode is used for a large block, the entire block is used without zeroing out any values.
In addition to DCT-II which has been employed in HEVC, a Multiple Transform Selection (MTS) scheme is used for residual coding both inter and intra coded blocks. It uses multiple selected transforms from the DCT8/DST7. The newly introduced transform matrices are DST-VII and DCT-VIII. The Table 4 below shows the basis functions of the selected DST/DCT.
In order to keep the orthogonality of the transform matrix, the transform matrices are quantized more accurately than the transform matrices in HEVC. To keep the intermediate values of the transformed coefficients within the 16-bit range, after horizontal and after vertical transform, all the coefficients are to have 10-bit.
In order to control MTS scheme, separate enabling flags are specified at SPS level for intra and inter, respectively. When MTS is enabled at SPS, a CU level flag is signalled to indicate whether MTS is applied or not. Here, MTS is applied only for luma. The MTS CU level flag is signalled when the following conditions are satisfied.
If MTS CU flag is equal to zero, then DCT2 is applied in both directions. However, if MTS CU flag is equal to one, then two other flags are additionally signalled to indicate the transform type for the horizontal and vertical directions, respectively. Transform and signalling mapping table as shown in Table 5. When it comes to transform matrix precision, 8-bit primary transform cores are used. Therefore, all the transform cores used in HEVC are kept as the same, including 4-point DCT-2 and DST-7, 8-point, 16-point and 32-point DCT-2. Also, other transform cores including 64-point DCT-2, 4-point DCT-8, 8-point, 16-point, 32-point DST-7 and DCT-8, use 8-bit primary transform cores.
To reduce the complexity of large size DST-7 and DCT-8, High frequency transform coefficients are zeroed out for the DST-7 and DCT-8 blocks with size (width or height, or both width and height) equal to 32. Only the coefficients within the 16×16 lower-frequency region are retained.
As in HEVC, the residual of a block can be coded with transform skip mode. To avoid the redundancy of syntax coding, the transform skip flag is not signalled when the CU level MTS_CU_flag is not equal to zero. The block size limitation for transform skip is the same to that for MTS in JEM4, which indicate that transform skip is applicable for a CU when both block width and height are equal to or less than 32.
Implicit MTS is a recent tool in VVC. The variable implicitMtsEnabled is derived as follows:
In VVC Draft v6, if the current coding block is luma component and implicitMtsEnabled is equal to 1, the implicit MTS transform selection is decided by the following formula:
trTypeHor=(nTbW>=4&& nTbW<=16)?DST7:DCT2 (8-965)
trTypeVer=(nTbH>=4&&nTbH<=16)?DST7:DCT2 (8-966)
where trTypeHor and trTypeVer specify the horizontal and vertical transform kernels, and nTbW and nTbH specify the width and height of the transform block. The two formulas indicate that the implicit MTS transform is selected from the following pairs: {DST7, DST7}, {DST7, DCT2}, {DCT2, DST7}, {DCT2, DCT2}
In JEM, secondary transform is applied between forward primary transform and quantization (at encoder) and between de-quantization and invert primary transform (at decoder side). As shown in
Application of a non-separable transform is described as follows using input as an example. To apply the non-separable transform, the 4×4 input block X
is first represented as a vector :
=[X00 X01 X02 X03 X10 X11 X12 X13 X20 X21 X22 X23 X30 X31 X32 X33]T
The non-separable transform is calculated as =T·
, where
indicates the transform coefficient vector, and Tis a 16×16 transform matrix. The 16×1 coefficient vector
is subsequently re-organized as 4×4 block using the scanning order for that block (horizontal, vertical or diagonal). The coefficients with smaller index will be placed with the smaller scanning index in the 4×4 coefficient block. There are totally 35 transform sets and 3 non-separable transform matrices (kernels) per transform set are used. The mapping from the intra prediction mode to the transform set is pre-defined. For each transform set, the selected non-separable secondary transform (NSST) candidate is further specified by the explicitly signalled secondary transform index. The index is signalled in a bit-stream once per Intra CU after transform coefficients.
The RST (a.k.a. Low Frequency Non-Separable Transform (LFNST)) was introduced in JVET-K0099 and 4 transform set (instead of 35 transform sets) mapping introduced in JVET-L0133. In this JVET-N0193, 16×64 (further reduced to 16×48) and 16×16 matrices are employed. For notational convenience, the 16×64 (reduced to 16×48) transform is denoted as RST8×8 and the 16×16 one as RST4×4.
The main idea of a Reduced Transform (RT) is to map an N dimensional vector to an R dimensional vector in a different space, where R/N (R<N) is the reduction factor.
The RT matrix is an R×N matrix as follows:
where the R rows of the transform are R bases of the N dimensional space. The invert transform matrix for RT is the transpose of its forward transform. The forward and invert RT are depicted in
In this contribution, the RST8×8 with a reduction factor of 4 (¼ size) is applied. Hence, instead of 64×64, which is conventional 8×8 non-separable transform matrix size, 16×64 direct matrix is used. In other words, the 64×16 invert RST matrix is used at the decoder side to generate core (primary) transform coefficients in 8×8 top-left regions. The forward RST8×8 uses 16×64 (or 8×64 for 8×8 block) matrices so that it produces non-zero coefficients only in the top-left 4×4 region within the given 8×8 region. In other words, if RST is applied then the 8×8 region except the top-left 4×4 region will have only zero coefficients. For RST4×4, 16×16 (or 8×16 for 4×4 block) direct matrix multiplication is applied.
An invert RST is conditionally applied when the following two conditions are satisfied:
If both width (W) and height (H) of a transform coefficient block is greater than 4, then the RST8×8 is applied to the top-left 8×8 region of the transform coefficient block. Otherwise, the RST4×4 is applied on the top-left min(8, W)×min(8, H) region of the transform coefficient block.
If RST index is equal to 0, RST is not applied. Otherwise, RST is applied, of which kernel is chosen with the RST index. The RST selection method and coding of the RST index are explained later.
Furthermore, RST is applied for intra CU in both intra and inter slices, and for both Luma and Chroma. If a dual tree is enabled, RST indices for Luma and Chroma are signaled separately. For inter slice (the dual tree is disabled), a single RST index is signaled and used for both Luma and Chroma.
In 13th JVET meeting, Intra Sub-Partitions (ISP), as a new intra prediction mode, was adopted. When ISP mode is selected, RST is disabled and RST index is not signaled, because performance improvement was marginal even if RST is applied to every feasible partition block. Furthermore, disabling RST for ISP-predicted residual could reduce encoding complexity.
A RST matrix is chosen from four transform sets, each of which consists of two transforms. Which transform set is applied is determined from intra prediction mode as the following:
(1) If one of three CCLM modes is indicated, transform set 0 is selected.
(2) Otherwise, transform set selection is performed according to the following table:
The index to access the above table, denoted as IntraPredMode, have a range of [−14, 83], which is a transformed mode index used for wide angle intra prediction.
As a further simplification, 16×48 matrices are applied instead of 16×64 with the same transform set configuration, each of which takes 48 input data from three 4×4 blocks in a top-left 8×8 block excluding right-bottom 4×4 block (as shown in
The forward RST8×8 with R=16 uses 16×64 matrices so that it produces non-zero coefficients only in the top-left 4×4 region within the given 8×8 region. In other words, if RST is applied then the 8×8 region except the top-left 4×4 region generates only zero coefficients. As a result, RST index is not coded when any non-zero element is detected within 8×8 block region other than top-left 4×4 (which is depicted in
Usually, before applying the invert RST on a 4×4 sub-block, any coefficient in the 4×4 sub-block may be non-zero. However, it is constrained that in some cases, some coefficients in the 4×4 sub-block must be zero before invert RST is applied on the sub-block.
Let nonZeroSize be a variable. It is required that any coefficient with the index no smaller than nonZeroSize when it is rearranged into a 1-D array before the invert RST must be zero.
When nonZeroSize is equal to 16, there is no zero-out constrain on the coefficients in the top-left 4×4 sub-block.
In JVET-N0193, when the current block size is 4×4 or 8×8, nonZeroSize is set equal to 8 (that is, coefficients with the scanning index in the range [8, 15] as show in
Sequence parameter set RBSP syntax
sps_st_enabled_flag equal to 1 specifies that st_idx may be present in the residual coding syntax for intra coding units. sps_st_enabled_flag equal to 0 specifies that st_idx is not present in the residual coding syntax for intra coding units.
st_idx[x0][y0] specifies which secondary transform kernel is applied between two candidate kernels in a selected transform set. st_idx[x0][y0] equal to 0 specifies that the secondary transform is not applied. The array indices x0, y0 specify the location (x, y0) of the top-left sample of the considered transform block relative to the top-left sample of the picture. When st_idx[x0][y0] is not present, st_idx[x0][y0] is inferred to be equal to 0.
Inputs to this process are:
Output of this process is the (nTbW)x(nTbH) array r[x][y] of residual samples with x=0 . . . nTbW−1, y=0 . . . nTbH−1.
If st_idx[xTbY][yTbY] is not equal to 0, the following applies:
1. The variables nStSize, log 2StSize, numStX, numStY, and nonZeroSize are derived as follows:
2. For xSbIdx=0 . . . numStX−1 and ySbIdx=0 . . . numStY−1, the following applies:
xC=(xSbIdx<<<log 2StSize)+DiagScanOrder[log 2StSize][log 2StSize][x][0]
yC=(ySbIdx<<<log 2StSize)+DiagScanOrder[log 2StSize][log 2StSize][x][1]u[x]=d[xC][yC]
d[(xSbIdx<<log 2StSize)+x][(ySbIdx<<log 2StSize)+y]=(y<4)?v[x+(y<<<log 2StSize)]:((x<4)?v[32+x+((y−4)<2)]: d[(xSbIdx<<log 2StSize)+x][(ySbIdx<<log 2StSize)+y])
d[(xSbIdx<<log 2StSize)+x][(ySbIdx<<log 2StSize)+y]=(y<4)?v[y+(x<<<log 2StSize)]:((x<4)?v[32+(y−4)+(x<<2)]: d[(xSbIdx<<log 2StSize)+x][(ySbIdx<<log 2StSize)+y])
Inputs to this process are:
The list of transformed samples y[i] with i=0 . . . nTrS−1 is derived as follows:
y[i]=Clip3(CoeffMin,CoeffMax,((Σj=0nonzerosize−1secTransMatrix[j][i]*x[j])+64)>>7)
with i=0 . . . nTrS−1
Inputs to this process are:
The transformation matrix secTransMatrix is derived based on nTrS, stTrSetIdx, and stIdx as follows:
In HEVC, the scaled transform coefficient d′ is calculated as
d′=Clip3(coeffMin,coeffMax,d),
where d is the scaled transform coefficient before clipping.
For luma component,
coeffMin=CoeffMinY,coeffMax=CoeffMaxY;
For chroma components,
coeffMin=CoeffMinC,coeffMax=CoeffMaxC.
Herein,
CoeffMinY=−(1<<(extended_precisionprocessing_flag?Max(15,BitDepthY+6):15))
CoeffMinC=−(1<<<(extended_precision_processing_flag?Max(15,BitDepthC+6):15))
CoeffMaxY=(1<<(extended_precisionprocessing_flag?Max(15,BitDepthY+6):15))−1
CoeffMaxC=(1<(extended_precision_processing_flag?Max(15,BitDepthC+6):15))−1
extended_precision_processing_flag is a syntax element signaled in SPS.
Affine linear weighted intra prediction (ALWIP, or matrix based intra prediction (MIP)) is proposed in JVET-N0217.
In JVET-N0217, two tests are conducted. In test 1, ALWIP is designed with a memory restriction of 8K bytes and at most 4 multiplications per sample. Test 2 is similar to test 1, but further simplifies the design in terms of memory requirement and model architecture.
For an inter-predicted CU with cu_cbf equal to 1, cu_sbt_flag may be signaled to indicate whether the whole residual block or a sub-part of the residual block is decoded. In the former case, inter MTS information is further parsed to determine the transform type of the CU. In the latter case, a part of the residual block is coded with inferred adaptive transform and the other part of the residual block is zeroed out. The SBT is not applied to the combined inter-intra mode.
In sub-block transform, position-dependent transform is applied on luma transform blocks in SBT-V and SBT-H (chroma TB always using DCT-2). The two positions of SBT-H and SBT-V are associated with different core transforms. More specifically, the horizontal and vertical transforms for each SBT position is specified in
SRCC has been adopted into AVS-3. With SRCC, a bottom-right position (SRx, SRy) as shown in
The current design of MTS has the following problems:
The signaled index may cause overhead bits.
Some combinations of transforms may not be efficient in MTS and SBT.
The decision of implicit MTS may not be efficient. In current VVC, implicitMtsEnabled is dependent on sps_mts_enabled_flag equal to 1. However, when sps_mts_enabled_flag is equal to 0, implicitMtsEnabled may also need to be applied.
In current VVC, the transform skip (TS) flag is coded regardless whether the current block is coded with QR-BDPCM mode or not. However, when QR-BDPCM is enabled, there is no need to apply transforms. Therefore, the signaling of TS flag is redundant when one block is coded with QR-BDPCM.
In current VVC, the transform skip flag is context coded with one context which may be also utilized for coding the bin which indicates whether the transform matric is DCT2. The shared context may be less efficient.
There are 5 context coded bins using 9 contexts required to code the transform matrix indices which impacts the parsing throughput.
QR-BDPCM/TS may be also applicable to chroma blocks. How to better determine the usage of QR-BDPCM/TS need to be further studied.
Embodiments of the presently disclosed technology overcome drawbacks of existing implementations, thereby providing video coding with higher coding efficiencies but lower computational complexity. Methods for multiple transforms, and as described in the present document, may enhance both existing and future video coding standards, is elucidated in the following examples described for various implementations. The examples of the disclosed technology provided below explain general concepts, and are not meant to be interpreted as limiting. In an example, unless explicitly indicated to the contrary, the various features described in these examples may be combined.
In the following examples, it is assumed that:
It is proposed to decide the transform (horizontal and/or vertical transform) applied to one block according to decoded coefficients without receiving transform indices.
The examples described above may be incorporated in the context of the methods described below, e.g., methods 1745, 1750, 1755, 1760, 1765 and 1770, which may be implemented at a video encoder and/or decoder.
The method 1745 includes, at step 1747, applying, as part of performing a conversion between a current block of a video and a bitstream representation of the video, the vertical transform and the horizontal transform to the current block.
The method 1750 includes, at step 1752, applying, as part of performing a conversion between the current block and a bitstream representation of the video, the one or more transforms to the current block based on the current block being coded with a sub-block transform (SBT).
The method 1755 includes, at step 1757, performing, based on the selecting, a conversion between the current block and a bitstream representation of the video.
The method 1760 includes, at step 1762, performing, based on the decision, a conversion between the current block and the bitstream representation. In some embodiments, the one or more messages are signaled in a video parameter set (VPS), a sequence parameter set (SPS), a picture parameter set (PPS), an adaptation parameter set (APS), a decoder parameter set (DPS), a slice header, a picture header, a sequence header, a tile group header, a tile, a coding tree unit (CTU) row, a CTU, a coding unit (CU), a prediction unit (PU), or a transform unit (TU).
The method 1765 includes, at step 1767, performing, based on the decision, a conversion between the current block and the bitstream representation.
The method 1770 includes, at step 1772, performing, based on the decision, a conversion between the current block and the bitstream representation. In some embodiments, an implicit MTS process includes using a characteristic of the current block to determine a transform used during the conversion.
In the following embodiments, additions are indicated using bolded double braces, e.g., {{a}} indicates that “a” has been added, whereas deletions are indicated using bolded double brackets, e.g., [[a]] indicates that “a” has been deleted.
The working draft specified in JVET-N1001-v7 may be changed as below.
The working draft specified in JVET-N1001-v8 may be changed as below.
Alternatively, the following may apply:
The working draft specified in JVET-N1001-v8 may be changed as below.
9.5.3.8 Binarization Process for tu_mts_idx
Input to this process is a request for a binarization for the syntax element tu_mts_idx. Output of this process is the binarization of the syntax element.
The binarization for the syntax element tu_mts_idx is specified in Table 9-14.
The working draft specified in JVET-N1001-v8 may be changed as below.
9.5.4.2 Derivation Process for ctxTable, ctxIdx and bypassFlag
The working draft specified in JVET-N1001-v8 may be changed as below.
9.5.4.3 Derivation Process for ctxTable, ctxIdx and bypassFlag
The working draft specified in JVET-N1001-v8 may be changed as below.
9.5.4.4 Derivation Process for ctxTable, ctxIdx and bypassFlag
The working draft specified in JVET-N1001-v8 may be changed as below.
9.5.4.5 Derivation Process for ctxTable, ctxIdx and bypassFlag
The working draft specified in JVET-N1001-v8 may be changed as below.
9.5.4.6 Derivation Process for ctxTable, ctxIdx and bypassFlag
Alternatively, the following may apply:
The working draft specified in JVET-O2001-vC may be changed as below.
The variable implicitMtsEnabled is derived as follows:
The working draft specified in JVET-O2001-vC may be changed as below.
The variable implicitMtsEnabled is derived as follows:
The working draft specified in JVET-O2001-vC may be changed as below.
The working draft specified in JVET-O2001-vC may be changed as below.
1.4.3.3 Sequence Parameter Set RBSP Semantics
[[sps_mts_enabled_flag equal to 1 specifies that sps_explicit_mts_intra_enabled_flag is present in the sequence parameter set RBSP syntax and that sps_explicit_mts_inter_enabled_flag is present in the sequence parameter set RBSP syntax. sps_mts_enabled_flag equal to 0 specifies that sps_explicit_mts_intra_enabled_flag is not present in the sequence parameter set RBSP syntax and that sps_explicit_mts_inter_enabled_flag is not present in the sequence parameter set RBSP syntax.]]
The variable implicitMtsEnabled is derived as follows:
The working draft specified in JVET-O2001-vC may be changed as below.
The variable implicitMtsEnabled is derived as follows:
The working draft specified in JVET-O2001-vC may be changed as below.
This embodiment is to apply transform coefficient zero-out according to the SPS flag sps_mts_enabled_flag.
The working draft specified in JVET-O2001-v14 may be changed as below.
In some embodiments, the following technical solutions can be implemented:
B1. A method for video processing, comprising selecting, as part of a multiple transform selection (MTS) process, a common transform as both a vertical transform and a horizontal transform; and applying, as part of performing a conversion between a current block of a video and a bitstream representation of the video, the vertical transform and the horizontal transform to the current block.
B2. The method of solution B1, wherein the common transform is either a first type of transform or a second type of transform.
B3. The method of solution B2, wherein the first type of transform is a Discrete Cosine Transform of Type II (DCT-II).
B4. The method of solution B2, wherein the second type of transform is a Discrete Sine Transform of Type VII (DST-VII).
B5. The method of solution B1, wherein a signaling for the MTS process comprises at most one flag for the current block.
B6. The method of solution B5, wherein the common transform is a Discrete Cosine Transform of Type II (DCT-II) when the flag is zero, and wherein the common transform is a Discrete Sine Transform of Type VII (DST-VII) when the flag is one.
B7. The method of solution B5, wherein the common transform is a Discrete Cosine Transform of Type II (DCT-II) when the flag is one, and wherein the common transform is a Discrete Sine Transform of Type VII (DST-VII) when the flag is zero.
B8. The method of any of solutions B1 to B7, wherein the current block has a height (H) and a width (W), and wherein H and W are positive integers.
B9. The method of solution B8, wherein W≥T1 and H≥T2, and T1 and T2 are integers.
B10. The method of solution B9, wherein T1=T2=8.
B11. The method of solution B8, wherein W≤T1 and H≤T2, and T1 and T2 are integers.
B12. The method of solution B11, wherein T1=T2=16.
B13. The method of solution B8, wherein min(W, H)≥T1, and T1 is an integer.
B14. The method of solution B13, wherein T1=8.
B15. The method of solution B8, wherein max(W, H)≤T1, and T1 is an integer.
B16. The method of solution B15, wherein T1=32.
B17. The method of solution B8, wherein W×H≥T1, and T1 is an integer.
B18. The method of solution B17, wherein T1=64.
B19. The method of solution B8, wherein W×H≤T1, and T1 is an integer.
B20. The method of solution B19, wherein T1=256.
B21. A method for video processing, comprising selecting, for a current block of a video as part of a multiple transform selection (MTS) process, one or more transforms that exclude a Discrete Sine Transform of Type VIII (DST VIII); and applying, as part of performing a conversion between the current block and a bitstream representation of the video, the one or more transforms to the current block based on the current block being coded with a sub-block transform (SBT).
B22. The method of solution B21, wherein the one or more transforms consist of a Discrete Cosine Transform of Type II (DCT-II) and a Discrete Sine Transform of Type VII (DST-VII).
B23. The method of solution B21, wherein the one or more transforms comprise a horizontal transform and a vertical transform.
B24. The method of solution B23, wherein the SBT is applied in a vertical direction, wherein the horizontal transform comprises a Discrete Cosine Transform of Type II (DCT-II), and wherein the vertical transform comprises a Discrete Sine Transform of Type VII (DST-VII).
B25. The method of solution B23, wherein the SBT is applied in a horizontal direction, wherein the vertical transform comprises a Discrete Cosine Transform of Type II (DCT-II), and wherein the horizontal transform comprises a Discrete Sine Transform of Type VII (DST-VII).
B26. A method for video processing, comprising selecting, for a current block of a video, a vertical transform and a horizontal transform as part of a multiple transform selection (MTS) process, wherein the current block is coded with a sub-block transform (SBT) based on a size of a transform block (TB) being smaller than a size of the current block, wherein the TB has a height (H) and a width (W), and wherein H and W are positive integers; and performing, based on the selecting, a conversion between the current block and a bitstream representation of the video.
B27. The method of solution B26, wherein the SBT is applied in a vertical direction, wherein the vertical transform comprises a Discrete Sine Transform of Type VII (DST-VII) and the horizontal transform comprises a Discrete Cosine Transform of Type II (DCT-II) when W>T1, wherein the vertical transform comprises a Discrete Sine Transform of Type VII (DST-VII) and the horizontal transform comprises a Discrete Cosine Transform of Type VIII (DCT-VIII) when W<T1, and wherein T1 is a positive integer.
B28. The method of solution B26, wherein the SBT is applied in a horizontal direction, wherein the horizontal transform comprises a Discrete Sine Transform of Type VII (DST-VII) and the vertical transform comprises a Discrete Cosine Transform of Type II (DCT-II) when H≥T1, wherein the horizontal transform comprises a Discrete Sine Transform of Type VII (DST-VII) and the vertical transform comprises a Discrete Cosine Transform of Type VIII (DCT-VIII) when H<T1, and wherein T1 is a positive integer.
B29. The method of solution B27 or B28, wherein T1=8.
B30. A method for video processing, comprising making a decision, for a current block of a video and based on one or more messages signaled in a bitstream representation of the video, regarding applying a transform coefficient zero-out process; and performing, based on the decision, a conversion between the current block and the bitstream representation, wherein the one or more messages are signaled in a video parameter set (VPS), a sequence parameter set (SPS), a picture parameter set (PPS), an adaptation parameter set (APS), a decoder parameter set (DPS), a slice header, a picture header, a sequence header, a tile group header, a tile, a coding tree unit (CTU) row, a CTU, a coding unit (CU), a prediction unit (PU), or a transform unit (TU).
B31. The method of solution B30, wherein the one or more messages comprise a flag that controls a usage of a multiple transform selection (MTS) process for the current block.
B32. The method of solution B30, wherein the one or more messages comprise a flag that controls a usage of a sub-block transform (SBT) on the current block.
B33. The method of solution B30, wherein the decision is further based on a dimension of a transform block (TB).
B34. The method of solution B30, wherein the transform coefficient zero-out is not applied for a transform block (TB) with specified dimensions when a multiple transform selection (MTS) process is not applied.
B35. The method of solution B30, wherein the transform coefficient zero-out is applied for a transform block (TB) with specified dimensions when a multiple transform selection (MTS) process is applied.
B36. A method for video processing, comprising making a decision, for a current block of a video and based on a size and a type of a transform, regarding applying a transform coefficient zero-out; and performing, based on the decision, a conversion between the current block and the bitstream representation.
B37. The method of solution B36, wherein the transform coefficient zero-out is applied when the transform is a Discrete Cosine Transform of Type II (DCT-II) and a size of the transform is M×64 or 64×N, and wherein M and N are positive integers.
B38. The method of solution B37, wherein M≤64 and N≤64.
B39. The method of solution B36, wherein the transform coefficient zero-out is applied when the transform is a Discrete Cosine Transform of Type VIII (DCT-VIII) or a Discrete Sine Transform of Type VII (DST-VII) and a size of the transform is M×32 or 32×N, and wherein M and N are positive integers.
B40. The method of solution B37, wherein M<32 and N<32.
B41. The method of solution B36, wherein the transform coefficient zero-out is not applied when the current block is coded using a transform skip mode.
B42. A method for video processing, comprising making a decision, for a current block of a video and based on an implicit transform of a multiple transform selection (MTS) process, regarding applying a transform coefficient zero-out; and performing, based on the decision, a conversion between the current block and the bitstream representation, wherein an implicit MTS process includes using a characteristic of the current block to determine a transform used during the conversion.
B43. The method of solution B42, wherein the transform coefficient zero-out is applied when a transform block (TB) of size M×32 or 32×N is coded with the implicit transform, and wherein M and N are positive integers.
B44. The method of solution B43, wherein M<32 and N<32.
B45. The method of any of solutions B1 to B44, wherein the conversion generates the current block from the bitstream representation.
B46. The method of any of solutions B1 to B44, wherein the conversion generates the bitstream representation from the current block.
B47. An apparatus in a video system comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to implement the method in any one of solutions B1 to B46.
B48. A computer program product stored on a non-transitory computer readable media, the computer program product including program code for carrying out the method in any one of solutions B1 to B46.
In some embodiments, the video coding methods may be implemented using an apparatus that is implemented on a hardware platform as described with respect to
Some embodiments of the disclosed technology include making a decision or determination to enable a video processing tool or mode. In an example, when the video processing tool or mode is enabled, the encoder will use or implement the tool or mode in the processing of a block of video, but may not necessarily modify the resulting bitstream based on the usage of the tool or mode. That is, a conversion from the block of video to the bitstream representation of the video will use the video processing tool or mode when it is enabled based on the decision or determination. In another example, when the video processing tool or mode is enabled, the decoder will process the bitstream with the knowledge that the bitstream has been modified based on the video processing tool or mode. That is, a conversion from the bitstream representation of the video to the block of video will be performed using the video processing tool or mode that was enabled based on the decision or determination.
Some embodiments of the disclosed technology include making a decision or determination to disable a video processing tool or mode. In an example, when the video processing tool or mode is disabled, the encoder will not use the tool or mode in the conversion of the block of video to the bitstream representation of the video. In another example, when the video processing tool or mode is disabled, the decoder will process the bitstream with the knowledge that the bitstream has not been modified using the video processing tool or mode that was enabled based on the decision or determination.
The system 1900 may include a coding component 1904 that may implement the various coding or encoding methods described in the present document. The coding component 1904 may reduce the average bitrate of video from the input 1902 to the output of the coding component 1904 to produce a coded representation of the video. The coding techniques are therefore sometimes called video compression or video transcoding techniques. The output of the coding component 1904 may be either stored, or transmitted via a communication connected, as represented by the component 1906. The stored or communicated bitstream (or coded) representation of the video received at the input 1902 may be used by the component 1908 for generating pixel values or displayable video that is sent to a display interface 1910. The process of generating user-viewable video from the bitstream representation is sometimes called video decompression. Furthermore, while certain video processing operations are referred to as “coding” operations or tools, it will be appreciated that the coding tools or operations are used at an encoder and corresponding decoding tools or operations that reverse the results of the coding will be performed by a decoder.
Examples of a peripheral bus interface or a display interface may include universal serial bus (USB) or high definition multimedia interface (HDMI) or Displayport, and so on. Examples of storage interfaces include SATA (serial advanced technology attachment), PCI, IDE interface, and the like. The techniques described in the present document may be embodied in various electronic devices such as mobile phones, laptops, smartphones or other devices that are capable of performing digital data processing and/or video display.
From the foregoing, it will be appreciated that specific embodiments of the presently disclosed technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the presently disclosed technology is not limited except as by the appended claims.
Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing unit” or “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
| Number | Date | Country | Kind |
|---|---|---|---|
| PCT/CN2019/090261 | Jun 2019 | CN | national |
| PCT/CN2019/101793 | Aug 2019 | CN | national |
This application is a continuation of International Patent Application No. PCT/CN2020/094905, filed on Jun. 8, 2020, which claims the priority to and benefits of International Patent Application No. PCT/CN2019/090261 filed on Jun. 6, 2019 and International Patent Application No. PCT/CN2019/101793 filed on Aug. 21, 2019. All the aforementioned patent applications are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2020/094905 | Jun 2020 | US |
| Child | 17457473 | US |
